USPTO Art Unit 2899 Prosecution Statistics

Art Unit Information

Art Unit: 2899
Group: 2890
Tech Center: 2800
Total Cases: 10,554
Last Active: August 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19308943SEMICONDUCTOR DEVICE STRUCTURE WITH EFFICIENT HEAT-REMOVAL STRUCTURES ACROSS THE CHIP AND MONOLITHIC FABRICATION METHOD THEREFORAugust 2025February 2026Allow610NoNo
19263700METHOD OF MANUFACTURING A PHOTONIC DEVICEJuly 2025October 2025Allow301YesNo
192321843D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSJune 2025March 2026Allow900NoNo
19224621LARGE-AREA/WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING INTERCALATION DOPING OF SYNTHESIZED AND PATTERNED GRAPHENEMay 2025February 2026Allow920NoNo
192225563D LIGHT-EMITTING DIODE AND ASSOCIATED MANUFACTURING METHODMay 2025September 2025Allow401YesNo
19186366MULTI-DIE SEMICONDUCTOR WAFER USING SILICON WAFER SUBSTRATE EMBEDMENTApril 2025September 2025Allow500NoNo
19186013ELECTRICAL BRIDGE PACKAGE WITH INTEGRATED OFF-BRIDGE PHOTONIC CHANNEL INTERFACEApril 2025September 2025Allow510NoNo
19062467HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAMEFebruary 2025August 2025Allow610NoNo
19047173METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEFebruary 2025April 2025Allow200NoNo
19099227FLUX AND METHOD FOR PRODUCING ELECTRONIC COMPONENTJanuary 2025October 2025Allow900NoNo
18997405METHOD FOR CHIP PACKAGING WITH HIGH-DENSITY CONNECTION LAYER, AND CHIP PACKAGING STRUCTUREJanuary 2025August 2025Allow710NoNo
19004392SUBSTRATE AND MANUFACTURING METHOD THEREOFDecember 2024October 2025Allow910NoNo
190041333D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSDecember 2024June 2025Allow500NoNo
18991037COLD PLATE AND MANIFOLD INTEGRATION FOR HIGH RELIABILITYDecember 2024May 2025Allow510NoNo
18873329METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMBERDecember 2024March 2025Allow300NoNo
18967100SYSTEMS AND METHODS FOR COOLING ELECTRONIC CIRCUITSDecember 2024June 2025Allow610YesNo
18967029SYSTEMS AND METHODS FOR COOLING ELECTRONIC CIRCUITSDecember 2024May 2025Allow510NoNo
18869882SOLAR CELL AND PREPARATION METHOD THEREFORNovember 2024January 2026Allow1401NoNo
18954308EMBEDDED COMPONENT INTERPOSER OR SUBSTRATE COMPRISING DISPLACEMENT COMPENSATION TRACES (DCTs) AND METHOD OF MAKING THE SAMENovember 2024May 2025Allow610NoNo
18947649THREE-DIMENSIONAL STACKED SEMICONDUCTOR DEVICE INCLUDING SIMPLIFIED SOURCE/DRAIN CONTACT AREANovember 2024February 2025Allow300NoNo
18948080SEMICONDUCTOR DEVICE INCLUDING INTERCONNECT STRUCTURE WITH METAL BRIDGE PATTERN CONNECTING ADJACENT METAL LINESNovember 2024April 2025Allow501NoNo
18945645ISOLATION STACK FOR A BIPOLAR TRANSISTOR AND RELATED METHODSNovember 2024July 2025Allow810NoNo
18946251FIELD PLATE STRUCTURE TO REDUCE SELF-HEATING IN TRANSISTOR AND RELATED METHODNovember 2024July 2025Allow811YesNo
18938407MEMORY DEVICE STRUCTURES THAT INCLUDE A CAPACITORNovember 2024September 2025Allow1011YesNo
18861583METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICEOctober 2024July 2025Allow910NoNo
18928253BOND FORCE CONCENTRATOROctober 2024March 2025Allow410YesNo
18909899MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATEOctober 2024September 2025Abandon1120NoNo
18907840HIGH-VOLTAGE SEMICONDUCTOR DEVICE STRUCTURESOctober 2024April 2025Allow610NoNo
18907770LATERALLY-DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES WITH A FIELD PLATEOctober 2024February 2025Allow411NoNo
18900000SEMICONDUCTOR DEVICE INCLUDING BOTTOM ISOLATION STRUCTURE FOR PREVENTING CURRENT LEAKAGESeptember 2024July 2025Allow1011NoNo
18898541COOLING CHANNEL SHAPE WITH SUBSTANTIALLY CONSTANT CROSS SECTIONAL AREASeptember 2024October 2025Allow1240YesNo
18850628ALL-IN-ONE DRY DEVELOPMENT FOR METAL-CONTAINING PHOTORESISTSeptember 2024December 2025Allow1420YesNo
18887789SEMICONDUCTOR DEVICE INCLUDING BACKSIDE CONTACT STRUCTURE FORMED BASED ON WIDE PLACEHOLDER STRUCTURESeptember 2024February 2026Allow1741YesNo
18886289SEMICONDUCTOR DEVICE INCLUDING INTERCONNECT STRUCTURE WITH PLANARIZATION STOP LAYERSeptember 2024December 2024Allow300NoNo
18883078OPTICALLY FUNCTIONAL MULTILAYER STRUCTURE AND RELATED METHOD OF MANUFACTURESeptember 2024June 2025Allow920YesNo
18882721Power Semiconductor Apparatus and Bonding Method ThereofSeptember 2024February 2025Allow511NoNo
18824948SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOFSeptember 2024March 2025Allow611YesNo
18823808DEVICE STRUCTURES FOR A HIGH-VOLTAGE SEMICONDUCTOR DEVICESeptember 2024April 2025Allow811NoNo
18820847SEMICONDUCTOR DEVICE INCLUDING METAL LINES HAVING MULTI-LAYER STRUCTUREAugust 2024March 2026Allow1951YesNo
18821747LEAD FRAME AND METHOD FOR STACKING DISCRETE COMPONENTS TO BE EMBEDDED IN SEMICONDUCTOR DEVICEAugust 2024November 2024Allow200NoNo
18814958BI-DIRECTIONAL SEMICONDUCTOR-CONTROLLED RECTIFIER WITH DUAL-LEVEL ISOLATION STRUCTURES AND METHODAugust 2024July 2025Allow1011NoNo
18841018PURE COPPER MATERIAL, INSULATING SUBSTRATE, AND ELECTRONIC DEVICEAugust 2024February 2025Allow600NoNo
18814235FIELD-EFFECT TRANSISTORS WITH HETEROGENOUS DOPED REGIONS IN THE SUBSTRATE OF A SILICON-ON-INSULATOR SUBSTRATEAugust 2024June 2025Allow911NoNo
18812553VARIABLE COMPOSITION TERNARY COMPOUND SEMICONDUCTOR ALLOYS, STRUCTURES, AND DEVICESAugust 2024July 2025Allow1110NoNo
18811589WAFER WARPAGE REGULATION EPOXY FUNCTIONAL FILM, AND PREPARATION METHOD AND APPLICATION THEREOFAugust 2024January 2025Allow500NoNo
18811327Manufacturing Process for Lidar System with Individualized Semiconductor Optical Amplifier DiesAugust 2024May 2025Allow911YesNo
18802233IC STRUCTURE WITH MFMIS MEMORY CELL AND CMOS TRANSISTORAugust 2024March 2025Allow710NoNo
18796069Electrostatic Discharge Protection Structure, Semiconductor Power Device and Manufacturing Method ThereofAugust 2024April 2025Allow801NoNo
18793277OPTIMIZATION OF THE THERMAL PERFORMANCE OF THE 3D ICS UTILIZING THE INTEGRATED CHIP-SIZE DOUBLE-LAYER OR MULTI-LAYER MICROCHANNELSAugust 2024January 2025Allow500NoNo
18835123PHOTOCURABLE RESIN COMPOSITION CONTAINING SELF-CROSSLINKABLE POLYMERAugust 2024February 2025Allow700NoNo
18785179METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEJuly 2024February 2026Allow1810NoNo
18784639FLUID CHANNEL GEOMETRY OPTIMIZATIONS TO IMPROVE COOLING EFFICIENCYJuly 2024April 2025Allow830YesNo
18773873LIGHT-EMITTING DEVICEJuly 2024October 2025Allow1500NoNo
18729437SURFACE RELIEF WAVEGUIDES WITH HIGH REFRACTIVE INDEX RESISTJuly 2024October 2024Allow300NoNo
18772247PACKAGE STRUCTURESJuly 2024July 2025Allow1210YesNo
18771052SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUSJuly 2024May 2025Allow1110NoNo
18771675METHOD OF MANUFACTURING EUV PHOTO MASKSJuly 2024February 2026Allow1910NoNo
18770582SYSTEMS AND METHODS FOR SUCTION PAD ASSEMBLIESJuly 2024January 2026Allow1920YesNo
18769385LIGHT EMITTING DEVICE FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAMEJuly 2024January 2026Allow1830NoNo
18769153PACKAGE STRUCTUREJuly 2024March 2026Allow2010NoNo
18766529PROCESS FOR MANUFACTURING AN ELECTROLUMINESCENT DEVICEJuly 2024December 2024Allow510YesNo
18764192ELECTRONIC DEVICEJuly 2024April 2025Allow1010YesNo
18762896LARGE DIAMETER SILICON CARBIDE WAFERSJuly 2024July 2025Allow1310NoNo
18761580SEMICONDUCTOR PACKAGEJuly 2024December 2025Allow1710YesNo
18761785ANTI-FLARE SEMICONDUCTOR PACKAGES AND RELATED METHODSJuly 2024May 2025Allow1010NoNo
18761884ARCHITECTURE FOR COMPUTING SYSTEM PACKAGEJuly 2024February 2025Allow700NoNo
18760072SYSTEMS AND METHODS FOR FABRICATING SILICON DIE STACKS FOR ELECTRON EMITTER ARRAY CHIPSJuly 2024January 2026Allow1910NoNo
18760330LIGHT EMITTING DEVICE AND DISPLAY APPARATUS HAVING THE SAMEJuly 2024January 2026Allow1930NoNo
18760817Semiconductor Device and Method of ManufactureJuly 2024September 2025Allow1510NoNo
18758069HIGH-VOLTAGE SEMICONDUCTOR DEVICE STRUCTURESJune 2024October 2024Allow310NoNo
18758423PACKAGES WITH THICK RDLS AND THIN RDLS STACKED ALTERNATINGLYJune 2024October 2025Allow1510NoNo
18756363MEMORY ARRAY CIRCUIT AND METHOD OF MANUFACTURING SAMEJune 2024May 2025Allow1010NoNo
18753873IMAGING DEVICEJune 2024March 2025Allow800NoNo
18751086ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024January 2025Allow700NoNo
18751101ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024February 2025Allow700NoNo
18748765SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PADJune 2024November 2025Allow1700NoNo
18748007METHOD OF MAKING A FAN-OUT SEMICONDUCTOR ASSEMBLY WITH AN INTERMEDIATE CARRIERJune 2024March 2025Allow920NoNo
18746717APPARATUS AND METHOD FOR MANUFACTURING METAL GATE STRUCTURESJune 2024May 2025Allow1110NoNo
18743313METHOD OF PRODUCING ASSEMBLY OF STACKED ELEMENTS HAVING RESIN LAYER WITH FILLERSJune 2024June 2025Allow1210YesNo
18742543LIGHT EMITTING DIODES WITH ALUMINUM-CONTAINING LAYERS INTEGRATED THEREIN AND ASSOCIATED METHODSJune 2024October 2025Allow1611YesNo
18742278INTERPOSER INCLUDING A COPPER EDGE SEAL RING STRUCTURE AND METHODS OF FORMING THE SAMEJune 2024January 2026Allow1910NoNo
18743027PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJune 2024October 2025Allow1610NoNo
18741188CHIP STRUCTURE AND METHOD FOR FORMING THE SAMEJune 2024July 2025Allow1310NoNo
18739890CLEAVE SYSTEMS HAVING SPRING MEMBERS FOR CLEAVING A SEMICONDUCTOR STRUCTURE AND METHODS FOR CLEAVING SUCH STRUCTURESJune 2024February 2025Allow800YesNo
18740456PACKAGES WITH ELECTRICAL FUSESJune 2024October 2025Allow1610NoNo
18739344TRANSISTOR STRUCTURE WITH AIR GAP AND METHOD OF FABRICATING THE SAMEJune 2024July 2025Allow1320NoNo
18739882Heat Dissipation StructuresJune 2024May 2025Allow1110NoNo
18738707METHODS OF REDUCING PARASITIC CAPACITANCE IN SEMICONDUTOR DEVICESJune 2024July 2025Allow1410NoNo
18738526Deposition Equipment with Adjustable Temperature SourceJune 2024December 2025Allow1810NoNo
18738256PATTERNING INTERCONNECTS AND OTHER STRUCTURES BY PHOTO-SENSITIZING METHODJune 2024April 2025Allow1010NoNo
18736766SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEJune 2024March 2025Allow900NoNo
18735584Light-Emitting Element, Light-Emitting Device, Display Device, Lighting Device, and Electronic DeviceJune 2024September 2025Allow1610NoNo
18717235HERRINGBONE MICROSTRUCTURE SURFACE PATTERN FOR FLEXOGRAPHIC PRINTING PLATESJune 2024March 2025Allow910NoNo
18732009METHOD FOR FABRICATING ELECTRONIC PACKAGEJune 2024June 2025Allow1210NoNo
18680896USING SPECTROSCOPIC MEASUREMENTS FOR SUBSTRATE TEMPERATURE MONITORINGMay 2024January 2025Allow700NoNo
18679437MAGNETORESISTIVE RANDOM ACCESS MEMORYMay 2024January 2025Allow710NoNo
18676343PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFMay 2024February 2026Allow2110NoNo
18674581MANIFOLD DESIGNS FOR EMBEDDED LIQUID COOLING IN A PACKAGEMay 2024October 2024Allow510NoNo
18674129UNIT PIXEL HAVING LIGHT EMITTING DEVICE, PIXEL MODULE AND DISPLAYING APPARATUSMay 2024December 2024Allow700NoNo
18672010SEMICONDUCTOR DEVICEMay 2024July 2025Allow1410NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2899.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
102
Examiner Affirmed
59
(57.8%)
Examiner Reversed
43
(42.2%)
Reversal Percentile
85.3%
Higher than average

What This Means

With a 42.2% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
306
Allowed After Appeal Filing
111
(36.3%)
Not Allowed After Appeal Filing
195
(63.7%)
Filing Benefit Percentile
72.4%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 36.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2899 - Prosecution Statistics Summary

Executive Summary

Art Unit 2899 is part of Group 2890 in Technology Center 2800. This art unit has examined 10,554 patent applications in our dataset, with an overall allowance rate of 89.5%. Applications typically reach final disposition in approximately 21 months.

Comparative Analysis

Art Unit 2899's allowance rate of 89.5% places it in the 89% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2899 receive an average of 1.58 office actions before reaching final disposition (in the 27% percentile). The median prosecution time is 21 months (in the 94% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.