USPTO Examiner CLARK JASMINE JHIHAN B - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19186366MULTI-DIE SEMICONDUCTOR WAFER USING SILICON WAFER SUBSTRATE EMBEDMENTApril 2025September 2025Allow500NoNo
19062467HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAMEFebruary 2025August 2025Allow610NoNo
19099227FLUX AND METHOD FOR PRODUCING ELECTRONIC COMPONENTJanuary 2025October 2025Allow900NoNo
18967100SYSTEMS AND METHODS FOR COOLING ELECTRONIC CIRCUITSDecember 2024June 2025Allow610YesNo
18841018PURE COPPER MATERIAL, INSULATING SUBSTRATE, AND ELECTRONIC DEVICEAugust 2024February 2025Allow600NoNo
18760072SYSTEMS AND METHODS FOR FABRICATING SILICON DIE STACKS FOR ELECTRON EMITTER ARRAY CHIPSJuly 2024January 2026Allow1910NoNo
18751086ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024January 2025Allow700NoNo
18751101ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024February 2025Allow700NoNo
18748765SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PADJune 2024November 2025Allow1700NoNo
18740456PACKAGES WITH ELECTRICAL FUSESJune 2024October 2025Allow1610NoNo
18674581MANIFOLD DESIGNS FOR EMBEDDED LIQUID COOLING IN A PACKAGEMay 2024October 2024Allow510NoNo
18670309INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIEMay 2024June 2025Allow1310NoNo
18659400SEMICONDUCTOR PACKAGE INCLUDING NON-CONDUCTIVE FILM AND METHOD FOR FORMING THE SAMEMay 2024June 2025Allow1310YesNo
18632548SEMICONDUCTOR PACKAGES USING PACKAGE IN PACKAGE SYSTEMS AND RELATED METHODSApril 2024May 2025Allow1310NoNo
18617137DATA PROCESSING SYSTEMS INCLUDING OPTICAL COMMUNICATION MODULESMarch 2024November 2024Allow800NoNo
18614579STACKED DIE MODULES FOR SEMICONDUCTOR DEVICE ASSEMBLIES AND METHODS OF MANUFACTURING STACKED DIE MODULESMarch 2024October 2025Allow1810NoNo
18438658SEMICONDUCTOR PACKAGE INCLUDING PLURALITY OF SEMICONDUCTOR CHIPS AND METHOD FOR MANUFACTURING THE SAMEFebruary 2024May 2025Allow1510YesNo
18425936STACKED INTEGRATED CIRCUITS WITH REDISTRIBUTION LINESJanuary 2024July 2025Allow1811NoNo
18426124SEMICONDUCTOR DEVICE PACKAGEJanuary 2024June 2025Allow1610NoNo
18423166SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFJanuary 2024July 2025Allow1811NoNo
18411176PROCESSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, PROCESSING APPARATUS, AND RECORDING MEDIUMJanuary 2024May 2025Allow1610NoNo
18408506SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2024July 2025Allow1800NoNo
18400784STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGEDecember 2023May 2025Allow1610NoNo
18399478STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURESDecember 2023January 2025Allow1210NoNo
18542672Shielding of Packaged Magnetic Random Access MemoryDecember 2023February 2025Allow1410YesNo
18518187Integrated Circuit Package and MethodNovember 2023October 2025Allow2310NoNo
18512567INTEGRATED COOLING ASSEMBLIES INCLUDING SIGNAL REDISTRIBUTION AND METHODS OF MANUFACTURING THE SAMENovember 2023November 2024Allow1210YesNo
18508321SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICENovember 2023March 2025Allow1610YesNo
18288636LAYERED BONDING MATERIAL, SEMICONDUCTOR PACKAGE, AND POWER MODULEOctober 2023May 2024Allow600NoNo
18486950SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTINGOctober 2023April 2025Allow1810NoNo
18484571PACKAGE STRUCTURE WITH UNDERFILLOctober 2023September 2025Allow2320NoNo
18480660SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYEROctober 2023February 2025Allow1610YesNo
18374972MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERSSeptember 2023July 2025Allow2210NoNo
18372846SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICESeptember 2023November 2024Allow1400NoNo
18371222WIRE BOND WIRES FOR INTERFERENCE SHIELDINGSeptember 2023December 2024Allow1410NoNo
18282005SYSTEMS AND METHODS FOR FABRICATING SILICON DIE STACKS FOR ELECTRON EMITTER ARRAY CHIPSSeptember 2023March 2024Allow610NoNo
18239549MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERSAugust 2023March 2025Allow1910NoNo
18455971SEMICONDUCTOR DEVICEAugust 2023April 2025Allow2010NoNo
18450216SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEAugust 2023February 2025Allow1810NoNo
18447528HETEROGENOUS BONDING LAYERS FOR DIRECT SEMICONDUCTOR BONDINGAugust 2023March 2025Allow1910YesNo
18232345NOVEL IMAGE SENSOR DEVICEAugust 2023June 2025Allow2220NoNo
18362433RECONSTITUTED SUBSTRATE STRUCTURE AND FABRICATION METHODS FOR HETEROGENEOUS PACKAGING INTEGRATIONJuly 2023March 2025Allow1910YesNo
18361924PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJuly 2023October 2025Allow2720YesNo
18359024PACKAGE STRUCTUREJuly 2023May 2025Allow2110NoNo
18225931SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THEREOFJuly 2023February 2026Allow3110NoNo
18357520Info Packages Including Thermal Dissipation BlocksJuly 2023July 2024Allow1200NoNo
18356187SEMICONDUCTOR DIE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGEJuly 2023January 2025Allow1811YesNo
18352270SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJuly 2023December 2024Allow1700NoNo
18351478SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAMEJuly 2023December 2024Allow1701NoNo
18218589SUBSTRATE-FREE SEMICONDUCTOR DEVICE ASSEMBLIES WITH MULTIPLE SEMICONDUCTOR DEVICES AND METHODS FOR MAKING THE SAMEJuly 2023September 2024Allow1511NoNo
18346321MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)July 2023September 2024Allow1510NoNo
18344981SEMICONDUCTOR PACKAGEJune 2023March 2026Allow3310NoNo
18209851POWER CHIP PACKAGING STRUCTUREJune 2023December 2025Allow3000NoNo
18334062STACKED SEMICONDUCTOR PACKAGEJune 2023January 2026Allow3110YesNo
18203952SEMICONDUCTOR MEMORY DEVICEMay 2023January 2025Allow1910NoNo
18201837SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTUREMay 2023August 2025Allow2700NoNo
18322567INVERTED LEADS FOR PACKAGED ISOLATION DEVICESMay 2023February 2025Allow2110NoNo
18140985SEMICONDUCTOR PACKAGEApril 2023December 2024Allow1910YesNo
18139872SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEApril 2023December 2024Allow2010NoNo
18138538SEMICONDUCTOR DEVICEApril 2023August 2025Allow2800NoNo
18303300SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPSApril 2023July 2024Allow1500NoNo
18302165Electronics Card Including Multi-Chip ModuleApril 2023September 2024Allow1710NoNo
18130197SEMICONDUCTOR PACKAGEApril 2023July 2025Allow2700NoNo
18194780DUAL-SIDE COOLING SEMICONDUCTOR PACKAGES AND RELATED METHODSApril 2023July 2024Allow1610NoNo
18178235SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGEMarch 2023June 2025Allow2800NoNo
18022915CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE BOARD COMPRISING SAMEFebruary 2023November 2025Allow3300NoNo
18172336POWER MODULEFebruary 2023August 2025Allow2900NoNo
18171566INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIEFebruary 2023February 2024Allow1210NoNo
18170078SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERSFebruary 2023July 2024Allow1710NoNo
18109787SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEFebruary 2023January 2024Allow1110NoNo
18166931MULTI-CHIP PACKAGEFebruary 2023June 2024Allow1600YesNo
18098782SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOFJanuary 2023December 2025Allow3400NoNo
18097481MEMORY SYSTEM PACKAGING STRUCTURE, AND METHOD FOR FORMING THE SAMEJanuary 2023October 2025Allow3310NoNo
18154329SEMICONDUCTOR PACKAGE FIXTURE AND METHODS OF MANUFACTURINGJanuary 2023December 2025Allow3611YesNo
18147212BONDED STRUCTURESDecember 2022July 2024Allow1910NoNo
18145282STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURESDecember 2022February 2024Allow1410YesNo
18074671ADHESIVE MEMBER AND DISPLAY DEVICE INCLUDING THE SAMEDecember 2022February 2024Allow1410NoNo
18060226SEMICONDUCTOR PACKAGE INCLUDING POSTNovember 2022June 2025Allow3000NoNo
17983531SEMICONDUCTOR DEVICENovember 2022April 2025Allow2900NoNo
17980556SEMICONDUCTOR SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOFNovember 2022April 2024Allow1710NoNo
17938891SEMICONDUCTOR PACKAGE DEVICEOctober 2022September 2025Allow3510YesNo
17936937PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMESeptember 2022September 2025Allow3510YesNo
17876466SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEJuly 2022September 2025Allow3811NoNo
17876504Semiconductor Package with Side Wall InterconnectionJuly 2022December 2025Allow4000NoNo
17870235INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIEJuly 2022August 2025Allow3710NoNo
17862459SEMICONDUCTOR PACKAGEJuly 2022July 2025Allow3610YesNo
17792255DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY PANEL, AND DISPLAY DEVICEJuly 2022September 2025Allow3810NoNo
17859291ELECTRONIC PACKAGE AND SUBSTRATE STRUCTURE THEREOFJuly 2022January 2025Allow3100NoNo
17857057SEMICONDUCTOR PACKAGES FOR STACKED MEMORY-ON-PACKAGE (SMOP) AND METHODS OF MANUFACTURING THE SAMEJuly 2022November 2025Allow4101NoNo
17809991BONDED ASSEMBLY INCLUDING INTERCONNECT-LEVEL BONDING PADS AND METHODS OF FORMING THE SAMEJune 2022July 2025Allow3700NoNo
17809675INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING WIRE BOND CHANNEL OVER PACKAGE SUBSTRATE, AND RELATED FABRICATION METHODSJune 2022June 2025Allow3610NoNo
17844815SEMICONDUCTOR PACKAGEJune 2022December 2024Allow3000NoNo
17833696DISPLAY PANEL AND DISPLAY APPARATUSJune 2022March 2025Allow3410NoNo
17830861SEMICONDUCTOR PACKAGE WITH IMPROVED HEAT DISTRIBUTIONJune 2022May 2025Allow3610NoNo
17828844SEMICONDUCTOR DEVICE WITH INDUCTIVE COMPONENT AND METHOD OF FORMINGMay 2022May 2025Allow3610YesNo
17752937BONDED SUBSTRATE AND BONDED SUBSTRATE MANUFACTURING METHODMay 2022November 2024Allow3000NoNo
17824481METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTUREMay 2022February 2025Allow3310NoNo
17778871POWER MODULE AND POWER CONVERSION DEVICEMay 2022June 2025Abandon3710NoNo
17664133IMAGE SENSOR PACKAGING STRUCTURES AND RELATED METHODSMay 2022September 2025Allow4011YesNo
17742383HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAMEMay 2022December 2024Allow3210NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CLARK, JASMINE JHIHAN B.

Strategic Value of Filing an Appeal

Total Appeal Filings
2
Allowed After Appeal Filing
2
(100.0%)
Not Allowed After Appeal Filing
0
(0.0%)
Filing Benefit Percentile
98.1%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 100.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner CLARK, JASMINE JHIHAN B - Prosecution Strategy Guide

Executive Summary

Examiner CLARK, JASMINE JHIHAN B works in Art Unit 2899 and has examined 206 patent applications in our dataset. With an allowance rate of 98.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner CLARK, JASMINE JHIHAN B's allowance rate of 98.5% places them in the 92% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by CLARK, JASMINE JHIHAN B receive 0.88 office actions before reaching final disposition. This places the examiner in the 6% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by CLARK, JASMINE JHIHAN B is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.7% benefit to allowance rate for applications examined by CLARK, JASMINE JHIHAN B. This interview benefit is in the 21% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 41.0% of applications are subsequently allowed. This success rate is in the 92% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 91.7% of cases where such amendments are filed. This entry rate is in the 98% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 96% percentile among all examiners. Of these withdrawals, 50.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 29.4% are granted (fully or in part). This grant rate is in the 17% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 2.9% of allowed cases (in the 79% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 50.2% of allowed cases (in the 97% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.