Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 19186366 | MULTI-DIE SEMICONDUCTOR WAFER USING SILICON WAFER SUBSTRATE EMBEDMENT | April 2025 | September 2025 | Allow | 5 | 0 | 0 | No | No |
| 19062467 | HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAME | February 2025 | August 2025 | Allow | 6 | 1 | 0 | No | No |
| 19099227 | FLUX AND METHOD FOR PRODUCING ELECTRONIC COMPONENT | January 2025 | October 2025 | Allow | 9 | 0 | 0 | No | No |
| 18967100 | SYSTEMS AND METHODS FOR COOLING ELECTRONIC CIRCUITS | December 2024 | June 2025 | Allow | 6 | 1 | 0 | Yes | No |
| 18841018 | PURE COPPER MATERIAL, INSULATING SUBSTRATE, AND ELECTRONIC DEVICE | August 2024 | February 2025 | Allow | 6 | 0 | 0 | No | No |
| 18760072 | SYSTEMS AND METHODS FOR FABRICATING SILICON DIE STACKS FOR ELECTRON EMITTER ARRAY CHIPS | July 2024 | January 2026 | Allow | 19 | 1 | 0 | No | No |
| 18751086 | ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS | June 2024 | January 2025 | Allow | 7 | 0 | 0 | No | No |
| 18751101 | ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS | June 2024 | February 2025 | Allow | 7 | 0 | 0 | No | No |
| 18748765 | SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD | June 2024 | November 2025 | Allow | 17 | 0 | 0 | No | No |
| 18740456 | PACKAGES WITH ELECTRICAL FUSES | June 2024 | October 2025 | Allow | 16 | 1 | 0 | No | No |
| 18674581 | MANIFOLD DESIGNS FOR EMBEDDED LIQUID COOLING IN A PACKAGE | May 2024 | October 2024 | Allow | 5 | 1 | 0 | No | No |
| 18670309 | INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE | May 2024 | June 2025 | Allow | 13 | 1 | 0 | No | No |
| 18659400 | SEMICONDUCTOR PACKAGE INCLUDING NON-CONDUCTIVE FILM AND METHOD FOR FORMING THE SAME | May 2024 | June 2025 | Allow | 13 | 1 | 0 | Yes | No |
| 18632548 | SEMICONDUCTOR PACKAGES USING PACKAGE IN PACKAGE SYSTEMS AND RELATED METHODS | April 2024 | May 2025 | Allow | 13 | 1 | 0 | No | No |
| 18617137 | DATA PROCESSING SYSTEMS INCLUDING OPTICAL COMMUNICATION MODULES | March 2024 | November 2024 | Allow | 8 | 0 | 0 | No | No |
| 18614579 | STACKED DIE MODULES FOR SEMICONDUCTOR DEVICE ASSEMBLIES AND METHODS OF MANUFACTURING STACKED DIE MODULES | March 2024 | October 2025 | Allow | 18 | 1 | 0 | No | No |
| 18438658 | SEMICONDUCTOR PACKAGE INCLUDING PLURALITY OF SEMICONDUCTOR CHIPS AND METHOD FOR MANUFACTURING THE SAME | February 2024 | May 2025 | Allow | 15 | 1 | 0 | Yes | No |
| 18425936 | STACKED INTEGRATED CIRCUITS WITH REDISTRIBUTION LINES | January 2024 | July 2025 | Allow | 18 | 1 | 1 | No | No |
| 18426124 | SEMICONDUCTOR DEVICE PACKAGE | January 2024 | June 2025 | Allow | 16 | 1 | 0 | No | No |
| 18423166 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | January 2024 | July 2025 | Allow | 18 | 1 | 1 | No | No |
| 18411176 | PROCESSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, PROCESSING APPARATUS, AND RECORDING MEDIUM | January 2024 | May 2025 | Allow | 16 | 1 | 0 | No | No |
| 18408506 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | January 2024 | July 2025 | Allow | 18 | 0 | 0 | No | No |
| 18400784 | STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE | December 2023 | May 2025 | Allow | 16 | 1 | 0 | No | No |
| 18399478 | STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURES | December 2023 | January 2025 | Allow | 12 | 1 | 0 | No | No |
| 18542672 | Shielding of Packaged Magnetic Random Access Memory | December 2023 | February 2025 | Allow | 14 | 1 | 0 | Yes | No |
| 18518187 | Integrated Circuit Package and Method | November 2023 | October 2025 | Allow | 23 | 1 | 0 | No | No |
| 18512567 | INTEGRATED COOLING ASSEMBLIES INCLUDING SIGNAL REDISTRIBUTION AND METHODS OF MANUFACTURING THE SAME | November 2023 | November 2024 | Allow | 12 | 1 | 0 | Yes | No |
| 18508321 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE | November 2023 | March 2025 | Allow | 16 | 1 | 0 | Yes | No |
| 18288636 | LAYERED BONDING MATERIAL, SEMICONDUCTOR PACKAGE, AND POWER MODULE | October 2023 | May 2024 | Allow | 6 | 0 | 0 | No | No |
| 18486950 | SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING | October 2023 | April 2025 | Allow | 18 | 1 | 0 | No | No |
| 18484571 | PACKAGE STRUCTURE WITH UNDERFILL | October 2023 | September 2025 | Allow | 23 | 2 | 0 | No | No |
| 18480660 | SEMICONDUCTOR PACKAGE INCLUDING MOLDING LAYER | October 2023 | February 2025 | Allow | 16 | 1 | 0 | Yes | No |
| 18374972 | MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERS | September 2023 | July 2025 | Allow | 22 | 1 | 0 | No | No |
| 18372846 | SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE | September 2023 | November 2024 | Allow | 14 | 0 | 0 | No | No |
| 18371222 | WIRE BOND WIRES FOR INTERFERENCE SHIELDING | September 2023 | December 2024 | Allow | 14 | 1 | 0 | No | No |
| 18282005 | SYSTEMS AND METHODS FOR FABRICATING SILICON DIE STACKS FOR ELECTRON EMITTER ARRAY CHIPS | September 2023 | March 2024 | Allow | 6 | 1 | 0 | No | No |
| 18239549 | MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERS | August 2023 | March 2025 | Allow | 19 | 1 | 0 | No | No |
| 18455971 | SEMICONDUCTOR DEVICE | August 2023 | April 2025 | Allow | 20 | 1 | 0 | No | No |
| 18450216 | SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | August 2023 | February 2025 | Allow | 18 | 1 | 0 | No | No |
| 18447528 | HETEROGENOUS BONDING LAYERS FOR DIRECT SEMICONDUCTOR BONDING | August 2023 | March 2025 | Allow | 19 | 1 | 0 | Yes | No |
| 18232345 | NOVEL IMAGE SENSOR DEVICE | August 2023 | June 2025 | Allow | 22 | 2 | 0 | No | No |
| 18362433 | RECONSTITUTED SUBSTRATE STRUCTURE AND FABRICATION METHODS FOR HETEROGENEOUS PACKAGING INTEGRATION | July 2023 | March 2025 | Allow | 19 | 1 | 0 | Yes | No |
| 18361924 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME | July 2023 | October 2025 | Allow | 27 | 2 | 0 | Yes | No |
| 18359024 | PACKAGE STRUCTURE | July 2023 | May 2025 | Allow | 21 | 1 | 0 | No | No |
| 18225931 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THEREOF | July 2023 | February 2026 | Allow | 31 | 1 | 0 | No | No |
| 18357520 | Info Packages Including Thermal Dissipation Blocks | July 2023 | July 2024 | Allow | 12 | 0 | 0 | No | No |
| 18356187 | SEMICONDUCTOR DIE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE | July 2023 | January 2025 | Allow | 18 | 1 | 1 | Yes | No |
| 18352270 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | July 2023 | December 2024 | Allow | 17 | 0 | 0 | No | No |
| 18351478 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME | July 2023 | December 2024 | Allow | 17 | 0 | 1 | No | No |
| 18218589 | SUBSTRATE-FREE SEMICONDUCTOR DEVICE ASSEMBLIES WITH MULTIPLE SEMICONDUCTOR DEVICES AND METHODS FOR MAKING THE SAME | July 2023 | September 2024 | Allow | 15 | 1 | 1 | No | No |
| 18346321 | MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM) | July 2023 | September 2024 | Allow | 15 | 1 | 0 | No | No |
| 18344981 | SEMICONDUCTOR PACKAGE | June 2023 | March 2026 | Allow | 33 | 1 | 0 | No | No |
| 18209851 | POWER CHIP PACKAGING STRUCTURE | June 2023 | December 2025 | Allow | 30 | 0 | 0 | No | No |
| 18334062 | STACKED SEMICONDUCTOR PACKAGE | June 2023 | January 2026 | Allow | 31 | 1 | 0 | Yes | No |
| 18203952 | SEMICONDUCTOR MEMORY DEVICE | May 2023 | January 2025 | Allow | 19 | 1 | 0 | No | No |
| 18201837 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE | May 2023 | August 2025 | Allow | 27 | 0 | 0 | No | No |
| 18322567 | INVERTED LEADS FOR PACKAGED ISOLATION DEVICES | May 2023 | February 2025 | Allow | 21 | 1 | 0 | No | No |
| 18140985 | SEMICONDUCTOR PACKAGE | April 2023 | December 2024 | Allow | 19 | 1 | 0 | Yes | No |
| 18139872 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | April 2023 | December 2024 | Allow | 20 | 1 | 0 | No | No |
| 18138538 | SEMICONDUCTOR DEVICE | April 2023 | August 2025 | Allow | 28 | 0 | 0 | No | No |
| 18303300 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS | April 2023 | July 2024 | Allow | 15 | 0 | 0 | No | No |
| 18302165 | Electronics Card Including Multi-Chip Module | April 2023 | September 2024 | Allow | 17 | 1 | 0 | No | No |
| 18130197 | SEMICONDUCTOR PACKAGE | April 2023 | July 2025 | Allow | 27 | 0 | 0 | No | No |
| 18194780 | DUAL-SIDE COOLING SEMICONDUCTOR PACKAGES AND RELATED METHODS | April 2023 | July 2024 | Allow | 16 | 1 | 0 | No | No |
| 18178235 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | March 2023 | June 2025 | Allow | 28 | 0 | 0 | No | No |
| 18022915 | CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE BOARD COMPRISING SAME | February 2023 | November 2025 | Allow | 33 | 0 | 0 | No | No |
| 18172336 | POWER MODULE | February 2023 | August 2025 | Allow | 29 | 0 | 0 | No | No |
| 18171566 | INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE | February 2023 | February 2024 | Allow | 12 | 1 | 0 | No | No |
| 18170078 | SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERS | February 2023 | July 2024 | Allow | 17 | 1 | 0 | No | No |
| 18109787 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | February 2023 | January 2024 | Allow | 11 | 1 | 0 | No | No |
| 18166931 | MULTI-CHIP PACKAGE | February 2023 | June 2024 | Allow | 16 | 0 | 0 | Yes | No |
| 18098782 | SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF | January 2023 | December 2025 | Allow | 34 | 0 | 0 | No | No |
| 18097481 | MEMORY SYSTEM PACKAGING STRUCTURE, AND METHOD FOR FORMING THE SAME | January 2023 | October 2025 | Allow | 33 | 1 | 0 | No | No |
| 18154329 | SEMICONDUCTOR PACKAGE FIXTURE AND METHODS OF MANUFACTURING | January 2023 | December 2025 | Allow | 36 | 1 | 1 | Yes | No |
| 18147212 | BONDED STRUCTURES | December 2022 | July 2024 | Allow | 19 | 1 | 0 | No | No |
| 18145282 | STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURES | December 2022 | February 2024 | Allow | 14 | 1 | 0 | Yes | No |
| 18074671 | ADHESIVE MEMBER AND DISPLAY DEVICE INCLUDING THE SAME | December 2022 | February 2024 | Allow | 14 | 1 | 0 | No | No |
| 18060226 | SEMICONDUCTOR PACKAGE INCLUDING POST | November 2022 | June 2025 | Allow | 30 | 0 | 0 | No | No |
| 17983531 | SEMICONDUCTOR DEVICE | November 2022 | April 2025 | Allow | 29 | 0 | 0 | No | No |
| 17980556 | SEMICONDUCTOR SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF | November 2022 | April 2024 | Allow | 17 | 1 | 0 | No | No |
| 17938891 | SEMICONDUCTOR PACKAGE DEVICE | October 2022 | September 2025 | Allow | 35 | 1 | 0 | Yes | No |
| 17936937 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | September 2022 | September 2025 | Allow | 35 | 1 | 0 | Yes | No |
| 17876466 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | July 2022 | September 2025 | Allow | 38 | 1 | 1 | No | No |
| 17876504 | Semiconductor Package with Side Wall Interconnection | July 2022 | December 2025 | Allow | 40 | 0 | 0 | No | No |
| 17870235 | INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIE | July 2022 | August 2025 | Allow | 37 | 1 | 0 | No | No |
| 17862459 | SEMICONDUCTOR PACKAGE | July 2022 | July 2025 | Allow | 36 | 1 | 0 | Yes | No |
| 17792255 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY PANEL, AND DISPLAY DEVICE | July 2022 | September 2025 | Allow | 38 | 1 | 0 | No | No |
| 17859291 | ELECTRONIC PACKAGE AND SUBSTRATE STRUCTURE THEREOF | July 2022 | January 2025 | Allow | 31 | 0 | 0 | No | No |
| 17857057 | SEMICONDUCTOR PACKAGES FOR STACKED MEMORY-ON-PACKAGE (SMOP) AND METHODS OF MANUFACTURING THE SAME | July 2022 | November 2025 | Allow | 41 | 0 | 1 | No | No |
| 17809991 | BONDED ASSEMBLY INCLUDING INTERCONNECT-LEVEL BONDING PADS AND METHODS OF FORMING THE SAME | June 2022 | July 2025 | Allow | 37 | 0 | 0 | No | No |
| 17809675 | INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING WIRE BOND CHANNEL OVER PACKAGE SUBSTRATE, AND RELATED FABRICATION METHODS | June 2022 | June 2025 | Allow | 36 | 1 | 0 | No | No |
| 17844815 | SEMICONDUCTOR PACKAGE | June 2022 | December 2024 | Allow | 30 | 0 | 0 | No | No |
| 17833696 | DISPLAY PANEL AND DISPLAY APPARATUS | June 2022 | March 2025 | Allow | 34 | 1 | 0 | No | No |
| 17830861 | SEMICONDUCTOR PACKAGE WITH IMPROVED HEAT DISTRIBUTION | June 2022 | May 2025 | Allow | 36 | 1 | 0 | No | No |
| 17828844 | SEMICONDUCTOR DEVICE WITH INDUCTIVE COMPONENT AND METHOD OF FORMING | May 2022 | May 2025 | Allow | 36 | 1 | 0 | Yes | No |
| 17752937 | BONDED SUBSTRATE AND BONDED SUBSTRATE MANUFACTURING METHOD | May 2022 | November 2024 | Allow | 30 | 0 | 0 | No | No |
| 17824481 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE | May 2022 | February 2025 | Allow | 33 | 1 | 0 | No | No |
| 17778871 | POWER MODULE AND POWER CONVERSION DEVICE | May 2022 | June 2025 | Abandon | 37 | 1 | 0 | No | No |
| 17664133 | IMAGE SENSOR PACKAGING STRUCTURES AND RELATED METHODS | May 2022 | September 2025 | Allow | 40 | 1 | 1 | Yes | No |
| 17742383 | HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME | May 2022 | December 2024 | Allow | 32 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CLARK, JASMINE JHIHAN B.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 100.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner CLARK, JASMINE JHIHAN B works in Art Unit 2899 and has examined 206 patent applications in our dataset. With an allowance rate of 98.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.
Examiner CLARK, JASMINE JHIHAN B's allowance rate of 98.5% places them in the 92% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by CLARK, JASMINE JHIHAN B receive 0.88 office actions before reaching final disposition. This places the examiner in the 6% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by CLARK, JASMINE JHIHAN B is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +1.7% benefit to allowance rate for applications examined by CLARK, JASMINE JHIHAN B. This interview benefit is in the 21% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 41.0% of applications are subsequently allowed. This success rate is in the 92% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 91.7% of cases where such amendments are filed. This entry rate is in the 98% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.
This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 96% percentile among all examiners. Of these withdrawals, 50.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 29.4% are granted (fully or in part). This grant rate is in the 17% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 2.9% of allowed cases (in the 79% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 50.2% of allowed cases (in the 97% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.