USPTO Examiner HARRISTON WILLIAM A - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19308943SEMICONDUCTOR DEVICE STRUCTURE WITH EFFICIENT HEAT-REMOVAL STRUCTURES ACROSS THE CHIP AND MONOLITHIC FABRICATION METHOD THEREFORAugust 2025February 2026Allow610NoNo
18954308EMBEDDED COMPONENT INTERPOSER OR SUBSTRATE COMPRISING DISPLACEMENT COMPENSATION TRACES (DCTs) AND METHOD OF MAKING THE SAMENovember 2024May 2025Allow610NoNo
18945645ISOLATION STACK FOR A BIPOLAR TRANSISTOR AND RELATED METHODSNovember 2024July 2025Allow810NoNo
18743027PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJune 2024October 2025Allow1610NoNo
18741188CHIP STRUCTURE AND METHOD FOR FORMING THE SAMEJune 2024July 2025Allow1310NoNo
18672010SEMICONDUCTOR DEVICEMay 2024July 2025Allow1410NoNo
18668505DISPLAY DEVICE HAVING A BENDING REGIONMay 2024June 2025Allow1310NoNo
18660190SEMICONDUCTOR DIEMay 2024October 2025Allow1710NoNo
18655989REDISTRIBUTION LINES WITH PROTECTION LAYERS AND METHOD FORMING SAMEMay 2024June 2025Allow1300NoNo
18648933SEMICONDUCTOR DEVICEApril 2024March 2025Allow1100NoNo
18641836REDISTRIBUTION LAYERS AND METHODS OF FABRICATING THE SAME IN SEMICONDUCTOR DEVICESApril 2024November 2025Allow1910NoNo
18635274SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE BUMPSApril 2024May 2025Allow1310NoNo
18627896SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARSApril 2024May 2025Allow1310NoNo
18612193SEMICONDUCTOR PACKAGE INCLUDING A REDISTRIBUTION SUBSTRATE AND A METHOD OF FABRICATING THE SAMEMarch 2024April 2025Allow1310NoNo
18604691PACKAGE COMPONENT WITH STEPPED PASSIVATION LAYERMarch 2024January 2026Allow2220NoNo
18591881SEMICONDUCTOR PACKAGE AND METHODFebruary 2024April 2025Allow1310NoNo
18586866SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEFebruary 2024September 2025Allow1800NoNo
18411314SEMICONDUCTOR PACKAGE SYSTEM AND METHODJanuary 2024April 2025Allow1510NoNo
18409778SEMICONDUCTOR PACKAGE HAVING A HIGH RELIABILITYJanuary 2024August 2024Allow800NoNo
18399220ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGESDecember 2023September 2025Allow2030NoNo
18545082SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEDecember 2023August 2024Allow800NoNo
18530286SEMICONDUCTOR DIE INCLUDING STRESS-RESISTANT BONDING STRUCTURES AND METHODS OF FORMING THE SAMEDecember 2023April 2025Allow1710NoNo
18526057SEMICONDUCTOR DEVICE AND METHODDecember 2023March 2025Allow1520NoNo
18519097ARRAY SUBSTRATE AND DISPLAY DEVICENovember 2023July 2024Allow800NoNo
18513649INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAMENovember 2023July 2025Allow2020NoNo
18491551SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEOctober 2023May 2024Allow700NoNo
18477686SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMESeptember 2023December 2024Abandon1510NoNo
18374595MICROELECTRONIC ASSEMBLIESSeptember 2023July 2024Allow900NoNo
18372533SUBSTRATE INTEGRATED THIN FILM CAPACITORS USING AMORPHOUS HIGH-K DIELECTRICSSeptember 2023August 2025Allow2330NoNo
18235271INTEGRATED COOLING ASSEMBLIES FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAMEAugust 2023October 2024Allow1410NoNo
18451156MICROELECTRONIC ASSEMBLIESAugust 2023December 2024Allow1620NoNo
18446905SEMICONDUCTOR DEVICE AND METHODAugust 2023June 2024Allow1000NoNo
18231185BUMP COPLANARITY FOR SEMICONDUCTOR DEVICE ASSEMBLY AND METHODS OF MANUFACTURING THE SAMEAugust 2023July 2024Allow1210NoNo
18229172ELECTRONIC DEVICE, PACKAGE STRUCTURE AND ELECTRONIC MANUFACTURING METHODAugust 2023January 2025Allow1710NoNo
18358164THROUGH SUBSTRATE VIA LANDING ON FRONT END OF LINE STRUCTUREJuly 2023January 2026Allow3010NoNo
18226210PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEJuly 2023June 2024Allow1110NoNo
18355098Semiconductor Device and Method of ManufactureJuly 2023March 2025Allow2010NoNo
183514143D NAND MEMORY DEVICE DEVICES AND RELATED ELECTRONIC SYSTEMSJuly 2023September 2024Allow1410NoNo
18350445THROUGH-SUBSTRATE-VIA IN PHOTOSENSITIVE MODULEJuly 2023February 2026Allow3110NoNo
18218673SEMICONDUCTOR PACKAGEJuly 2023February 2026Allow3110NoNo
18270840PACKAGE STRUCTURE FOR REDUCING WARPAGE OF PLASTIC PACKAGE WAFER AND METHOD FOR MANUFACTURING THE SAMEJuly 2023October 2025Allow2710NoNo
18215830SEMICONDUCTOR PACKAGE USING SUBSTRATE BLOCK INTEGRATIONJune 2023February 2026Allow3110NoNo
18216561SEMICONDUCTOR PACKAGE USING SUBSTRATE BLOCK INTEGRATIONJune 2023January 2026Allow3110NoNo
18338095REDISTRIBUTION LINES WITH PROTECTION LAYERS AND METHOD FORMING SAMEJune 2023February 2024Allow800NoNo
18334693SEMICONDUCTOR DEVICEJune 2023February 2024Allow800NoNo
18331241FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHINGJune 2023June 2024Allow1300NoNo
18324744HYBRID BONDED INTERCONNECT BRIDGINGMay 2023May 2024Allow1210NoNo
18322566DISPLAY DEVICE HAVING A BENDING REGIONMay 2023January 2024Allow800NoNo
18308648THREE-DIMENSIONAL FUNCTIONAL INTEGRATIONApril 2023April 2024Allow1210NoNo
18308433SEMICONDUCTOR PACKAGE INCLUDING AN INTERPOSER AND METHOD OF FABRICATING THE SAMEApril 2023March 2024Allow1110YesNo
18300045INTERCONNECT STRUCTURE FOR ADVANCED PACKAGING AND METHOD FOR THE SAMEApril 2023December 2025Allow3310NoNo
18132571FAN-OUT STACKED SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGING METHOD THEREOFApril 2023December 2025Allow3310NoNo
18296793SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEApril 2023February 2025Allow2300NoNo
18129120SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEMarch 2023November 2023Allow700NoNo
18027074THREE-DIMENSIONAL STACKED PROCESSING SYSTEMSMarch 2023December 2025Allow3310NoNo
18120587SEMICONDUCTOR PACKAGEMarch 2023February 2024Allow1210NoNo
18182246SEMICONDUCTOR PACKAGE HAVING A HIGH RELIABILITYMarch 2023September 2023Allow700NoNo
18119397SEMICONDUCTOR PACKAGEMarch 2023November 2023Allow800NoNo
18119270PACKAGE STRUCTUREMarch 2023January 2026Allow3410NoNo
18174784SEMICONDUCTOR PACKAGE AND METHODFebruary 2023November 2023Allow900NoNo
18171428PACKAGE DIES INCLUDING VERTICAL INTERCONNECTS FOR SIGNAL AND POWER DISTRIBUTION IN A THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) PACKAGEFebruary 2023January 2026Allow3510NoNo
18170857SEMICONDUCTOR PACKAGES HAVING VIASFebruary 2023December 2023Allow1000NoNo
18169976ELECTRONIC COMPONENT, MODULE, AND METHOD OF MANUFACTURING ELECTRONIC COMPONENTFebruary 2023June 2025Allow2800NoNo
18169161SEMICONDUCTOR PACKAGESFebruary 2023September 2023Allow700NoNo
18109337FLIP-CHIP BONDING STRUCTURE AND SUBSTRATE THEREOFFebruary 2023December 2025Allow3410NoNo
18167095PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAMEFebruary 2023January 2026Allow3510NoNo
18107800Package Having an Electronic Component and an Encapsulant Encapsulating a Dielectric Layer and a Semiconductor Die of the Electronic ComponentFebruary 2023May 2024Allow1620NoNo
18166960Redistribution Layers And Methods Of Fabricating The Same In Semiconductor DevicesFebruary 2023December 2023Allow1010NoNo
18159132METHOD OF MANUFACTURING PACKAGE UNIT, PACKAGE UNIT, ELECTRONIC MODULE, AND EQUIPMENTJanuary 2023August 2023Allow600NoNo
181568483DIC STRUCTURE AND METHODS OF FORMINGJanuary 2023January 2024Allow1210NoNo
18154615SUBSTRATES FOR SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH IMPROVED THERMAL PERFORMANCE AND METHODS FOR MAKING THE SAMEJanuary 2023October 2024Allow2110NoNo
18094794SEMICONDUCTOR PACKAGEJanuary 2023August 2023Allow700NoNo
18151545INTEGRATED CIRCUIT PACKAGES AND METHODSJanuary 2023December 2025Allow3510NoNo
18069318SEMICONDUCTOR PACKAGEDecember 2022November 2025Allow3510YesNo
18085397FULLY MOLDED BRIDGE INTERPOSER AND METHOD OF MAKING THE SAMEDecember 2022June 2023Allow600NoNo
18066487INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEDecember 2022August 2023Allow800NoNo
18078096STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEDecember 2022January 2026Allow3710NoNo
18063413SEMICONDUCTOR PACKAGEDecember 2022August 2025Allow3210NoNo
18076529SEMICONDUCTOR DEVICEDecember 2022June 2023Allow700NoNo
18063029APPARATUS AND METHOD OF MANUFACTURING SOLDER BUMPDecember 2022April 2024Allow1620YesNo
18060574STRUCTURE AND PROCESS FOR WARPAGE REDUCTIONDecember 2022December 2025Allow3610YesNo
17993638CHIP SCALE PACKAGENovember 2022November 2023Allow1120NoNo
18056564DOUBLE-SIDED LAMINATE PACKAGE WITH 3D INTERCONNECTION STRUCTURENovember 2022January 2026Allow3810NoNo
17987132SEMICONDUCTOR DEVICENovember 2022March 2026Allow4011YesNo
17986995SEMICONDUCTOR PACKAGENovember 2022December 2025Allow3711NoNo
17980914Integrated Circuit Package and MethodNovember 2022November 2023Allow1310NoNo
17975054METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICEOctober 2022March 2026Allow4120NoNo
17964583REVERSE EMBEDDED POWER STRUCTURE FOR GRAPHICAL PROCESSING UNIT CHIPS AND SYSTEM-ON-CHIP DEVICE PACKAGESOctober 2022December 2025Allow3810NoNo
17959352SEMICONDUCTOR PACKAGEOctober 2022April 2025Allow3000NoNo
17960057SUBSTRATE INTEGRATED THIN FILM CAPACITORS USING AMORPHOUS HIGH-K DIELECTRICSOctober 2022July 2023Allow910NoNo
17936037Semiconductor Device and Method of Stacking Hybrid Substrates with Embedded Electric ComponentsSeptember 2022August 2025Allow3511NoNo
17935613SEMICONDUCTOR DEVICE WITH REINFORCED DIELECTRIC AND METHOD THEREFORSeptember 2022December 2025Allow3810NoNo
17949460SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMESeptember 2022July 2023Allow900NoNo
17823461FABRICATING AN ELECTROCONDUCTIVE CONTACT ON A TOP LAYER OF A TUNNELING MAGNETORESISTANCE ELEMENT USING TWO HARD MASKSAugust 2022February 2025Allow3000NoNo
17898398PRINT-READY WAFERS WITH BOTTOM-ANCHORED COMPONENTSAugust 2022February 2026Allow4110NoNo
17897206PACKAGE STRUCTUREAugust 2022January 2026Allow4120NoNo
17817478SEMICONDUCTOR DEVICEAugust 2022March 2023Allow700NoNo
17875644Interfacial Layer Between Fin and Source/Drain RegionJuly 2022March 2023Allow800NoNo
17815515Semiconductor Device and Method of ManufactureJuly 2022June 2023Allow1000NoNo
17872028PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAMEJuly 2022March 2024Allow2010NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner HARRISTON, WILLIAM A.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
5
Examiner Affirmed
2
(40.0%)
Examiner Reversed
3
(60.0%)
Reversal Percentile
83.8%
Higher than average

What This Means

With a 60.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
15
Allowed After Appeal Filing
5
(33.3%)
Not Allowed After Appeal Filing
10
(66.7%)
Filing Benefit Percentile
53.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner HARRISTON, WILLIAM A - Prosecution Strategy Guide

Executive Summary

Examiner HARRISTON, WILLIAM A works in Art Unit 2899 and has examined 824 patent applications in our dataset. With an allowance rate of 93.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner HARRISTON, WILLIAM A's allowance rate of 93.1% places them in the 80% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by HARRISTON, WILLIAM A receive 1.52 office actions before reaching final disposition. This places the examiner in the 27% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by HARRISTON, WILLIAM A is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -1.1% benefit to allowance rate for applications examined by HARRISTON, WILLIAM A. This interview benefit is in the 10% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 31.2% of applications are subsequently allowed. This success rate is in the 64% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 54.6% of cases where such amendments are filed. This entry rate is in the 81% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 40.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 37% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 64.3% of appeals filed. This is in the 44% percentile among all examiners. Of these withdrawals, 44.4% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 37.8% are granted (fully or in part). This grant rate is in the 26% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.5% of allowed cases (in the 60% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.3% of allowed cases (in the 52% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.