USPTO Examiner JEAN BAPTISTE WILNER - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
192321843D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSJune 2025March 2026Allow900NoNo
190041333D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSDecember 2024June 2025Allow500NoNo
18772247PACKAGE STRUCTURESJuly 2024July 2025Allow1210YesNo
18771052SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUSJuly 2024May 2025Allow1110NoNo
18738707METHODS OF REDUCING PARASITIC CAPACITANCE IN SEMICONDUTOR DEVICESJune 2024July 2025Allow1410NoNo
18736766SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEJune 2024March 2025Allow900NoNo
18668941SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUSMay 2024April 2025Allow1110NoNo
18643474INTERPOSER, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAMEApril 2024April 2025Allow1110YesNo
18631900SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAMEApril 2024February 2025Allow1000NoNo
18626594SEMICONDUCTOR DEVICEApril 2024June 2024Allow200NoNo
18615151SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUSMarch 2024June 2025Allow1410NoNo
18614499OLED PANEL LOWER PART PROTECTION FILM, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS COMPRISING SAMEMarch 2024December 2024Allow900NoNo
18593775HYBRID BACKSIDE THERMAL STRUCTURES FOR ENHANCED IC PACKAGESMarch 2024July 2025Allow1710NoNo
18438158UNDERFILL FILM FOR SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAMEFebruary 2024January 2025Allow1110NoNo
18429471METHOD OF FABRICATING SEMICONDUCTOR PACKAGEFebruary 2024April 2025Allow1410YesNo
18402755APPARATUS INCLUDING INTEGRATED SEGMENTS AND METHODS OF MANUFACTURING THE SAMEJanuary 2024November 2025Allow2221NoNo
18396302SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERNDecember 2023September 2024Allow910NoNo
18544747INTEGRATED CIRCUIT CHIP INCLUDING A PASSIVATION NITRIDE LAYER IN CONTACT WITH A HIGH VOLTAGE BONDING PAD AND METHOD OF MAKINGDecember 2023July 2025Allow1920NoNo
18567143DISPLAY PANEL AND DISPLAY DEVICEDecember 2023March 2026Allow2700NoNo
18520996Source/Drain Metal Contact and Formation ThereofNovember 2023June 2025Allow1810NoNo
18516969SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMENovember 2023January 2026Allow2621YesNo
18513167Asymmetric Stackup Structure for SoC Package SubstratesNovember 2023February 2025Allow1510NoNo
18509801Seal Ring Designs Supporting Efficient Die to Die RoutingNovember 2023May 2025Allow1810NoNo
18508807SEMICONDUCTOR PACKAGENovember 2023April 2025Allow1710YesNo
18386345METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH WIRE BONDNovember 2023August 2024Allow1010NoNo
18497691DIE WITH METAL PILLARSOctober 2023March 2025Allow1710YesNo
18488627SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAMEOctober 2023March 2026Allow2900NoNo
18488990METHOD FOR CREATING A WETTABLE SURFACE FOR IMPROVED RELIABILITY IN QFN PACKAGESOctober 2023November 2024Allow1300NoNo
18380404SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEOctober 2023October 2024Allow1210NoNo
18485291SEMICONDUCTOR DEVICEOctober 2023July 2025Allow2120NoNo
18483977METHOD OF SOLDERING A SEMICONDUCTOR CHIP TO A CHIP CARRIEROctober 2023June 2024Allow900NoNo
18474234PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFSeptember 2023January 2025Allow1610YesNo
18449253METHOD FOR ASSEMBLING EIC TO PIC TO BUILD AN OPTICAL ENGINEAugust 2023January 2026Allow2901NoNo
18447968Storage Layers For Wafer BondingAugust 2023January 2025Allow1810YesNo
18447467CIRCUIT DEVICES WITH GATE SEALSAugust 2023April 2025Allow2020NoNo
18366844BOND PAD STRUCTURE COUPLED TO MULTIPLE INTERCONNECT CONDUCTIVE\ STRUCTURES THROUGH TRENCH IN SUBSTRATEAugust 2023February 2025Allow1810NoNo
182289073D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSAugust 2023December 2024Allow1610YesNo
18363458Semiconductor Package and Methods of Forming the SameAugust 2023September 2024Allow1410NoNo
18363731METHOD OF FABRICATING SEMICONDUCTOR PACKAGEAugust 2023November 2024Allow1610YesNo
18360169SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREJuly 2023January 2025Allow1810NoNo
18225286Grain Structure Engineering for Metal Gapfill MaterialsJuly 2023December 2025Allow2900NoNo
18357421Supporting InFO Packages to Reduce WarpageJuly 2023March 2025Allow2020YesNo
18357500Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication ThereofJuly 2023March 2025Allow2011NoNo
18356843Protection Structures for Bonded WafersJuly 2023November 2024Allow1510NoNo
18217898VIA FORMED IN A WAFER USING A FRONT-SIDE AND A BACK-SIDE PROCESSJuly 2023March 2026Allow3310NoNo
18346573FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH PROTECTION LAYER AND METHOD FOR FORMING THE SAMEJuly 2023January 2025Allow1810NoNo
18213759SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOFJune 2023January 2025Allow1810NoNo
18209173THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAMEJune 2023October 2024Allow1610NoNo
18329347SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO INTERCONNECT STRUCTURESJune 2023November 2024Allow1810NoNo
18326554SEMICONDUCTOR PACKAGEMay 2023March 2026Allow3410YesNo
18321439SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUSMay 2023August 2024Allow1510NoNo
18197800Semiconductor Package and Method for Fabricating a Semiconductor PackageMay 2023September 2024Allow1610NoNo
18141519SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGEMay 2023March 2026Allow3410YesNo
18309218THERMAL MANAGEMENT SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICESApril 2023February 2026Allow3410YesNo
18140960SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAMEApril 2023November 2025Allow3010YesNo
181381103D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSApril 2023June 2023Allow200NoNo
18302884PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE, AND METHOD OF FABRICATING THE SAMEApril 2023February 2026Allow3410YesNo
18303345INTEGRATED CIRCUIT ASSEMBLY WITH HYBRID BONDINGApril 2023March 2025Allow2320NoNo
18301374SEMICONDUCTOR PACKAGEApril 2023February 2026Allow3410YesNo
18249351METHOD AND DEVICE FOR PRODUCING A SEMICONDUCTOR COMPONENTApril 2023November 2025Allow3110NoNo
18135035SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEApril 2023February 2026Allow3410YesNo
18132500Differential Sensing With Biofet SensorsApril 2023February 2025Allow2211NoNo
18127206STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCEMarch 2023February 2025Allow2320YesNo
18190206COMPENSATION METHOD FOR WAFER BONDINGMarch 2023February 2026Allow3420NoNo
18188621DIE BONDING TOOL WITH TILTABLE BOND HEAD FOR IMPROVED BONDING AND METHODS FOR PERFORMING THE SAMEMarch 2023August 2025Allow2901NoNo
18123967METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTUREMarch 2023August 2025Allow2930YesNo
18043731ADHESIVE AGENT FOR SEMICONDUCTORS, AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAMEMarch 2023February 2026Allow3610NoNo
18170270PIXEL CIRCUIT AND METHOD OF OPERATING THE SAME IN AN ALWAYS-ON MODEFebruary 2023October 2024Allow2010NoNo
18108984Module with Gas Flow-Inhibiting Sealing at Module Interface to Mounting BaseFebruary 2023June 2025Allow2830NoNo
18106883BONDING AND TRANSFERRING METHOD FOR DIE PACKAGE STRUCTURESFebruary 2023July 2025Allow2900NoNo
18099777Multitier Arrangements of Integrated Devices, and Methods of Forming Sense/Access LinesJanuary 2023July 2024Allow1810NoNo
18153847Packaged Semiconductor Device and Method of Forming ThereofJanuary 2023September 2024Allow2110NoNo
18151663Adding Sealing Material to Wafer edge for Wafer BondingJanuary 2023September 2025Allow3201NoNo
18151622PACKAGED MULTI-CHIP SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAMEJanuary 2023June 2024Allow1710NoNo
180922533D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSDecember 2022April 2023Allow300NoNo
18085746SEMICONDUCTOR CHIP, CHIP SYSTEM, METHOD OF FORMING A SEMICONDUCTOR CHIP, AND METHOD OF FORMING A CHIP SYSTEMDecember 2022January 2026Allow3720NoNo
18081047NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUITDecember 2022May 2024Allow1700NoNo
18064641SELECTIVE UNDERFILL ASSEMBLY AND METHOD THEREFORDecember 2022September 2024Allow2110NoNo
18064624Fan-Out Wafer Level Package StructureDecember 2022August 2024Allow2010NoNo
18076364INTEGRATED MECHANICAL AIDS FOR HIGH ACCURACY ALIGNABLE-ELECTRICAL CONTACTSDecember 2022June 2024Allow1820NoNo
18076210VIA FORMED USING A PARTIAL PLUG THAT STOPS BEFORE A SUBSTRATEDecember 2022December 2025Allow3711YesNo
18054172SEMICONDUCTOR DEVICENovember 2022April 2024Allow1700NoNo
17982524PIXEL DEVICE FOR LED DISPLAY AND LED DISPLAY APPARATUS HAVING THE SAMENovember 2022February 2026Allow4030YesNo
17980571SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOFNovember 2022September 2025Allow3510YesNo
17971321INTERPOSER, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE INTERPOSEROctober 2022September 2024Allow2320NoNo
18048513Solder Ball Application for Singular DieOctober 2022March 2024Allow1710NoNo
17970964MANUFACTURING METHOD OF DIAMOND COMPOSITE WAFEROctober 2022December 2025Allow3810NoNo
17969402DIODE AND BIPOLAR JUNCTION TRANSISTOR FOR 3D SFET WITH BSPDN STRUCTUREOctober 2022February 2026Allow4030YesNo
17918038SUBSTRATE BONDING METHODOctober 2022January 2025Allow2800NoNo
17962131SEMICONDUCTOR DIE HAVING AN OPTICAL DETECTION MARKER AND METHOD OF PRODUCING THE SEMICONDUCTOR DIEOctober 2022July 2025Allow3300NoNo
17938135Stacked Integrated Circuit DeviceOctober 2022April 2025Allow3000NoNo
17959585CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICESOctober 2022November 2024Allow2610NoNo
17957926INTEGRATED CIRCUIT PACKAGES WITH HYBRID BONDED DIES AND METHODS OF MANUFACTURING THE SAMESeptember 2022January 2026Allow3911YesNo
17952925SEMICONDUCTOR PACKAGE HAVING IMPROVED HEAT DISSIPATION CHARACTERISTICSSeptember 2022July 2025Allow3300NoNo
17951523DEVICE AND PROCESS FOR IMPLEMENTING SILICON CARBIDE (SIC) SURFACE MOUNT DEVICESSeptember 2022February 2026Allow4111NoNo
17934346Thermally Enhanced Chip-on-Wafer or Wafer-on-Wafer BondingSeptember 2022July 2025Allow3410NoNo
17946883STACKED SEMICONDUCTOR METHOD AND APPARATUSSeptember 2022November 2025Allow3811YesNo
17931796MANUFACTURING METHOD OF SEMICONDUCTOR CHIPSeptember 2022May 2025Allow3200NoNo
17899541Semiconductor Device with a Nickel Comprising Layer and Method for Fabricating the SameAugust 2022March 2025Allow3001NoNo
17898421METHOD FOR PRODUCING A 3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDSAugust 2022December 2022Allow300NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner JEAN BAPTISTE, WILNER.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
6
Examiner Affirmed
2
(33.3%)
Examiner Reversed
4
(66.7%)
Reversal Percentile
87.1%
Higher than average

What This Means

With a 66.7% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
32
Allowed After Appeal Filing
11
(34.4%)
Not Allowed After Appeal Filing
21
(65.6%)
Filing Benefit Percentile
56.6%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 34.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner JEAN BAPTISTE, WILNER - Prosecution Strategy Guide

Executive Summary

Examiner JEAN BAPTISTE, WILNER works in Art Unit 2899 and has examined 564 patent applications in our dataset. With an allowance rate of 93.8%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 23 months.

Allowance Patterns

Examiner JEAN BAPTISTE, WILNER's allowance rate of 93.8% places them in the 81% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by JEAN BAPTISTE, WILNER receive 1.60 office actions before reaching final disposition. This places the examiner in the 31% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by JEAN BAPTISTE, WILNER is 23 months. This places the examiner in the 87% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -3.4% benefit to allowance rate for applications examined by JEAN BAPTISTE, WILNER. This interview benefit is in the 7% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 29.2% of applications are subsequently allowed. This success rate is in the 55% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 33.5% of cases where such amendments are filed. This entry rate is in the 50% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 130.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 84% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 80.6% of appeals filed. This is in the 74% percentile among all examiners. Of these withdrawals, 52.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 20.7% are granted (fully or in part). This grant rate is in the 11% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.7% of allowed cases (in the 64% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.9% of allowed cases (in the 67% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.