USPTO Examiner STEVENSON ANDRE C - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19047173METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEFebruary 2025April 2025Allow200NoNo
18664595METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICEMay 2024April 2025Allow1110NoNo
18660179WARPAGE-REDUCING SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD OF THE SAMEMay 2024March 2025Allow1010NoNo
18640167HYBRID BONDING WITH UNIFORM PATTERN DENSITYApril 2024May 2025Allow1301NoNo
18634295INTEGRATED CIRCUIT INCLUDING TRANSISTORS AND A METHOD OF MANUFACTURING THE SAMEApril 2024April 2025Allow1210NoNo
18625061GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP APPROACHApril 2024April 2025Allow1210NoNo
18436365VERTICAL THIN-FILM TRANSISTOR AND APPLICATION AS BIT-LINE CONNECTOR FOR 3-DIMENSIONAL MEMORY ARRAYSFebruary 2024January 2025Allow1110NoNo
18416585METHOD OF FABRICATING A SEMICONDUCTOR DEVICEJanuary 2024October 2024Allow910NoNo
18403523FORMATION OF TRANSISTOR GATESJanuary 2024February 2025Allow1410NoNo
18530759METHOD FOR FABRICATING LAYER STRUCTURE HAVING TARGET TOPOLOGICAL PROFILEDecember 2023October 2024Allow1010NoNo
18523637NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESSNovember 2023January 2025Allow1410NoNo
18513545METHODS FOR WAFER BONDINGNovember 2023October 2024Allow1110NoNo
18502110SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICENovember 2023January 2025Allow1410NoNo
18384455INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIESOctober 2023December 2024Allow1310NoNo
18378688SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEOctober 2023September 2024Allow1100NoNo
18472261SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMESeptember 2023November 2024Allow1410NoNo
18370198CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATIONSeptember 2023November 2024Allow1410NoNo
18447685PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECTAugust 2023March 2025Allow1901YesNo
18232289METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICEAugust 2023January 2025Allow1710NoNo
18366460REDUCING K VALUES OF DIELECTRIC FILMS THROUGH ANNEALAugust 2023May 2025Allow2120NoNo
18230712SURFACE OXIDATION CONTROL OF METAL GATES USING CAPPING LAYERAugust 2023January 2025Allow1710NoNo
18230052SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEAugust 2023September 2024Allow1410NoNo
18223923SPOT HEATING BY MOVING A BEAM WITH HORIZONTAL ROTARY MOTIONJuly 2023November 2024Allow1611NoNo
18216468SPIN ON CARBON COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEJune 2023July 2024Allow1310NoNo
18197833SYSTEMS AND METHODS FOR THE USE OF FRAUD PREVENTION FLUID TO PREVENT CHIP FRAUDMay 2023May 2024Allow1211YesNo
18311016Semiconductor Device and MethodMay 2023May 2025Allow2411NoNo
18302434Low-k Feature Formation Processes and Structures Formed TherebyApril 2023November 2024Allow1920NoNo
18123596Void Elimination for Gap-Filling In High-Aspect Ratio TrenchesMarch 2023May 2024Allow1410NoNo
18186567Profile Control In Forming Epitaxy Regions for TransistorsMarch 2023June 2024Allow1510NoNo
18178140Dummy Fin Profile Control to Enlarge Gate Process WindowMarch 2023June 2024Allow1510NoNo
18108526ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOSFebruary 2023May 2024Allow1510NoNo
18165007Gate Formation Of Semiconductor DevicesFebruary 2023September 2024Allow1911NoNo
18092219METHODS FOR FORMING A TOPOGRAPHICALLY SELECTIVE SILICON OXIDE FILM BY A CYCLICAL PLASMA-ENHANCED DEPOSITION PROCESSDecember 2022June 2024Allow1710NoNo
17991380SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFNovember 2022March 2024Allow1510NoNo
17961617MANUFACTURING METHOD FOR LIQUID CRYSTAL DISPLAY DEVICEOctober 2022March 2024Allow1710NoNo
17951589LDMOS DEVICE AND METHOD FOR FABRICATING THE SAMESeptember 2022April 2025Allow3001NoNo
17893796Method of Forming 3-Dimensional SpacerAugust 2022June 2025Allow3301NoNo
17893209SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOFAugust 2022May 2025Allow3301NoNo
17888649INTEGRATED CIRCUIT INCLUDING TRANSISTORS AND A METHOD OF MANUFACTURING THE SAMEAugust 2022December 2023Allow1610NoNo
17888314STAIRCASE ETCH CONTROL IN FORMING THREE-DIMENSIONAL MEMORY DEVICEAugust 2022June 2024Allow2220YesNo
17819660METHOD OF PROCESSING WAFERAugust 2022February 2025Allow3000YesNo
17876487SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJuly 2022August 2024Allow2511NoNo
17868786SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEJuly 2022June 2025Allow3520NoNo
17867835METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICEJuly 2022June 2025Allow3511NoNo
17787604DISPLAY SUBSTRATE, PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUSJune 2022June 2025Allow3510NoNo
17841479CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATIONJune 2022June 2023Allow1200NoNo
17805557Fan-Out Interconnect Structure and Methods Forming the SameJune 2022March 2024Allow2120NoNo
17832675SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEJune 2022May 2024Allow2321YesNo
17827648METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE WITH OUTER ELECTRODE EXTENSIONMay 2022January 2025Allow3201NoNo
17825798Gate Structure Fabrication Techniques for Reducing Gate Structure WarpageMay 2022June 2025Allow3720NoNo
17751406SEMICONDUCTOR APPARATUS AND DEVICEMay 2022March 2025Allow3410NoNo
17778274LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING LIGHT EMITTING DIODE DISPLAY DEVICEMay 2022September 2024Allow2800NoNo
17746263MANUFACTURING METHOD OF DISPLAY DEVICE AND HOLDING SUBSTRATEMay 2022May 2025Allow3620NoNo
17745612SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEMay 2022December 2024Allow3101NoNo
17776127uLED CHIP, uLED SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, EL INSPECTION METHOD FOR uLED SUBSTRATE, AND EL INSPECTION APPARATUSMay 2022September 2024Allow2900YesNo
17775772Composite Wavelength ConverterMay 2022April 2025Allow3511NoNo
17770253DISPLAY PANEL, MANUFACTURING METHOD AND DISPLAY DEVICEApril 2022February 2025Allow3410NoNo
17696277SUBSTRATE POLISHING APPARATUS, SUBSTRATE POLISHING METHOD USING THE SAME, AND SEMICONDUCTOR FABRICATION METHOD INCLUDING THE SAMEMarch 2022May 2025Allow3811NoNo
17688103SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD OF USING THE SAMEMarch 2022February 2025Allow3501NoNo
17682234AIR-REPLACED SPACER FOR SELF-ALIGNED CONTACT SCHEMEFebruary 2022March 2024Allow2411NoNo
17651881Hybrid Bonding with Uniform Pattern DensityFebruary 2022January 2024Allow2321NoNo
17636113THIN-FILM COMPONENTS FOR INTEGRATED CIRCUITSFebruary 2022June 2025Allow4020NoNo
17648420METHOD OF FORMING OXIDE LAYER AND SEMICONDUCTOR STRUCTUREJanuary 2022October 2024Abandon3310NoNo
17644135WAFER BONDING METHOD AND BONDED WAFERDecember 2021April 2025Allow4001NoNo
17531245METHOD FOR MAKING HIGH-VOLTAGE THICK GATE OXIDENovember 2021December 2023Allow2510NoNo
17455246IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAMENovember 2021October 2024Allow3511YesNo
17442141SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMESeptember 2021March 2025Allow4111NoNo
17480075PIXEL ARRANGEMENT STRUCTURE AND DISPLAY PANELSeptember 2021June 2024Allow3310NoNo
17480055DISPLAY SUBSTRATE AND DISPLAY APPARATUSSeptember 2021October 2024Allow3710NoNo
17475646METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ETCHING METHODSeptember 2021August 2024Abandon3520NoNo
17447332SEMICONDUCTOR MEMORY DEVICESeptember 2021February 2025Allow4130YesNo
17447169METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURESeptember 2021June 2024Allow3310NoNo
17446744MANUFACTURING METHOD OF DEVICE CHIPSeptember 2021August 2024Allow3510YesNo
17465744SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFSeptember 2021February 2024Allow2900NoNo
17435221DISPLAY SUBSTRATE AND DISPLAY DEVICEAugust 2021July 2024Allow3500YesNo
17459885PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECTAugust 2021January 2024Allow2811YesNo
17460097METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICEAugust 2021February 2024Allow3001YesNo
17412359PASSIVATION STRUCTURE FOR A THIN FILM TRANSISTORAugust 2021March 2025Allow4221NoNo
17401574SEAM REMOVAL IN HIGH ASPECT RATIO GAP-FILLAugust 2021July 2024Allow3521NoYes
17398127SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTUREAugust 2021March 2024Allow3110NoNo
17398075METHOD FOR FORMING SILICON DIOXIDE FILM AND METHOD FOR FORMING METAL GATEAugust 2021March 2024Allow3120NoNo
17397482METHOD FOR FABRICATING SEMICONDUCTOR DEVICEAugust 2021February 2024Allow3021NoNo
17396690MEMORY, SUBSTRATE STRUCTURE OF THE MEMORY, AND METHOD FOR PREPARING THE SUBSTRATE STRUCTURE OF THE MEMORYAugust 2021February 2024Allow3020YesNo
17426323Light-Emitting Device, Light-Emitting Apparatus, Electronic Device, Display Device, and Lighting DeviceJuly 2021June 2024Allow3401NoNo
17387447Forming a Protective Layer to Prevent Formation of Leakage PathsJuly 2021April 2024Allow3230YesNo
17310132LOW STRESS FILMS FOR ADVANCED SEMICONDUCTOR APPLICATIONSJuly 2021January 2025Allow4221NoNo
17377833GROUP III NITRIDE BASED LED STRUCTURES INCLUDING MULTIPLE QUANTUM WELLS WITH BARRIER-WELL UNIT INTERFACE LAYERSJuly 2021December 2023Allow2920YesYes
17377135SILICON NITRIDE FILMS HAVING REDUCED INTERFACIAL STRAINJuly 2021August 2024Allow3721NoNo
17369841CMP SAFE ALIGNMENT MARKJuly 2021November 2024Allow4031NoNo
17369936WARPAGE-REDUCING SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD OF THE SAMEJuly 2021April 2024Allow3340NoNo
17360982METHOD OF DEPOSITING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAMEJune 2021January 2024Allow3120NoNo
17359947SELECTIVE CARBON DEPOSITION ON TOP AND BOTTOM SURFACES OF SEMICONDUCTOR SUBSTRATESJune 2021June 2024Allow3521YesNo
17347786Amorphous Silicon-Based Scavenging And Sealing EOTJune 2021July 2024Allow3720NoYes
17340818Conductive Capping For Work Function Layer and Method Forming SameJune 2021June 2024Allow3630YesYes
17333592Reducing K Values of Dielectric Films Through AnnealMay 2021September 2024Allow3941YesNo
17246209PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINERApril 2021March 2024Allow3420NoYes
17214417INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOFMarch 2021December 2023Allow3330YesNo
17202146SEMICONDUCTOR DEVICE HAVING STI REGIONMarch 2021October 2024Allow4431NoNo
17200169MICROELECTRONIC DEVICES WITH NITROGEN-RICH INSULATIVE STRUCTURESMarch 2021November 2023Allow3221NoNo
17192865METHOD FOR FABRICATING LAYER STRUCTURE HAVING TARGET TOPOLOGICAL PROFILEMarch 2021October 2023Allow3230YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner STEVENSON, ANDRE C.

Strategic Value of Filing an Appeal

Total Appeal Filings
11
Allowed After Appeal Filing
7
(63.6%)
Not Allowed After Appeal Filing
4
(36.4%)
Filing Benefit Percentile
90.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 63.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner STEVENSON, ANDRE C - Prosecution Strategy Guide

Executive Summary

Examiner STEVENSON, ANDRE C works in Art Unit 2899 and has examined 256 patent applications in our dataset. With an allowance rate of 98.4%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 22 months.

Allowance Patterns

Examiner STEVENSON, ANDRE C's allowance rate of 98.4% places them in the 95% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by STEVENSON, ANDRE C receive 1.31 office actions before reaching final disposition. This places the examiner in the 26% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by STEVENSON, ANDRE C is 22 months. This places the examiner in the 82% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -1.0% benefit to allowance rate for applications examined by STEVENSON, ANDRE C. This interview benefit is in the 8% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 31.3% of applications are subsequently allowed. This success rate is in the 56% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 60.3% of cases where such amendments are filed. This entry rate is in the 82% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 66.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 54% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 95% percentile among all examiners. Of these withdrawals, 44.4% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 46.2% are granted (fully or in part). This grant rate is in the 52% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 1.2% of allowed cases (in the 70% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 3.2% of allowed cases (in the 72% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.