USPTO Examiner TYNES JR. LAWRENCE C - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18796069Electrostatic Discharge Protection Structure, Semiconductor Power Device and Manufacturing Method ThereofAugust 2024April 2025Allow801NoNo
18761884ARCHITECTURE FOR COMPUTING SYSTEM PACKAGEJuly 2024February 2025Allow700NoNo
18760817Semiconductor Device and Method of ManufactureJuly 2024September 2025Allow1510NoNo
18758423PACKAGES WITH THICK RDLS AND THIN RDLS STACKED ALTERNATINGLYJune 2024October 2025Allow1510NoNo
18656112LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE HAVING THE SAMEMay 2024June 2025Allow1300NoNo
18635347Integrated Circuit with a Fin and Gate Structure and Method Making the SameApril 2024January 2025Allow900NoNo
18631966INTEGRATED CIRCUIT PACKAGE AND METHODApril 2024March 2025Allow1100NoNo
18629424DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGEApril 2024June 2025Allow1410YesNo
18609836GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATEMarch 2024August 2025Allow1710NoNo
18603181OPTOELECTRONIC PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAMEMarch 2024September 2025Allow1810NoNo
18602033SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMarch 2024April 2025Allow1310NoNo
18586549PACKAGE AND MANUFACTURING METHOD THEREOFFebruary 2024September 2024Allow700NoNo
18388712IMAGE SENSOR AND A METHOD OF MANUFACTURING THE SAMENovember 2023February 2026Allow2700NoNo
18387127METHOD FOR MANUFACTURING ORGANIC SEMICONDUCTOR ELEMENTNovember 2023March 2026Allow2800NoNo
18385667SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESOctober 2023December 2024Allow1400NoNo
18494710CONTROL OF WAFER BOW IN MULTIPLE STATIONSOctober 2023March 2026Allow2900NoNo
18487216IMAGE SENSOR DEVICEOctober 2023March 2025Allow1710YesNo
18378803LATE SRAM CUT WITH BACKSIDE CONTACTOctober 2023February 2026Allow2800NoNo
18477258TRENCH MOSFET AND MANUFACTURING METHOD THEREFORSeptember 2023February 2026Allow2800NoNo
18477138SILICON CARBIDE SEMICONDUCTOR DEVICESeptember 2023February 2026Allow2900NoNo
18475546SEMICONDUCTOR PACKAGESSeptember 2023May 2025Allow2010NoNo
18372977LASER-FORMED INTERCONNECTS FOR REDUNDANT DEVICESSeptember 2023January 2026Allow2810NoNo
18234914SEMICONDUCTOR PACKAGEAugust 2023August 2025Allow2420YesNo
18231614METHOD OF REPAIRING LIGHT EMITTING DEVICE AND DISPLAY PANEL HAVING REPAIRED LIGHT EMITTING DEVICEAugust 2023April 2025Allow2110NoNo
18365997ARCHED MEMBRANE STRUCTURE FOR MEMS DEVICEAugust 2023September 2024Allow1310NoNo
18365232PACKAGE COMPONENT, ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOFAugust 2023May 2025Allow2210NoNo
18359684Semiconductor Device and Method of ManufactureJuly 2023March 2024Allow800NoNo
18355824Architecture for Computing System PackageJuly 2023March 2024Allow800NoNo
18355004SEMICONDUCTOR CHIP STACK STRUCTURE, SEMICONDUCTOR PACKAGE, AND METHODS OF MANUFACTURING THEMJuly 2023February 2026Allow3100NoNo
18346319Integrated Circuit Package and Method Forming SameJuly 2023June 2024Allow1200NoNo
18339132DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURESJune 2023November 2025Allow2930YesNo
18338273ELECTRONIC PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2023September 2025Allow2700NoNo
18336561Methods Of Forming Air Spacers In Semicondutor DevicesJune 2023October 2024Allow1600NoNo
18329871Semiconductor Device and Method of Making an EMI Shield Using Intensive Pulsed Light IrradiationJune 2023February 2026Allow3210NoNo
18328322SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEJune 2023January 2024Allow800NoNo
18318864SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEMay 2023June 2024Allow1310NoNo
18138180SEMICONDUCTOR PACKAGEApril 2023March 2026Allow3410NoNo
18305516SEMICONDUCTOR DEVICEApril 2023October 2025Allow3000NoNo
18302589INTEGRATED CIRCUIT PACKAGE AND METHODApril 2023January 2024Allow900NoNo
18134767DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOFApril 2023July 2024Allow1510NoNo
18134333TUNNEL JUNCTION ULTRAVIOLET LIGHT EMITTING DIODES WITH ENHANCED LIGHT EXTRACTION EFFICIENCYApril 2023April 2025Allow2420NoNo
18122285SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEMarch 2023February 2026Allow3520YesNo
18184222HETEROGENEOUS INTEGRATION FOR MEMRISTOR-BASED HARDWARE ACCELERATORSMarch 2023August 2025Allow2900NoNo
18182728PACKAGE STRUCTURE WITH REINFORCED ELEMENTMarch 2023September 2024Allow1820NoNo
18120555ELECTRONIC DEVICEMarch 2023February 2026Abandon3510NoNo
18174129SEMICONDUCTOR PACKAGEFebruary 2023October 2024Allow2000NoNo
18112430SEMICONDUCTOR PACKAGES WITH CHIPLETS COUPLED TO A MEMORY DEVICEFebruary 2023September 2024Allow1900NoNo
18169713SEMICONDUCTOR PACKAGEFebruary 2023May 2025Allow2740YesNo
18041694LIGHT EMITTING MODULE, METHOD OF MANUFACTURING LIGHT EMITTING MODULE, AND DISPLAY DEVICEFebruary 2023February 2026Allow3610NoNo
18098987SEMICONDUCTOR DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2023December 2025Allow3510NoNo
18153380Zero Mask High Density CapacitorJanuary 2023April 2024Allow1510NoNo
18153458RF BRIDGEJanuary 2023July 2025Allow3000NoNo
18015576CHIP FINE LINE FAN-OUT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREFORJanuary 2023December 2025Allow3500NoNo
18091048DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGEDecember 2022February 2024Allow1420NoNo
18091197SELECTIVE GATE OXIDE FORMATION ON 2D MATERIAL BASED TRANSISTOR DEVICESDecember 2022February 2026Allow3800NoNo
18063377ELECTRONIC PACKAGE AND SUBSTRATE STRUCTURE THEREOFDecember 2022October 2025Allow3410NoNo
17979761LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE HAVING THE SAMENovember 2022February 2024Allow1500NoNo
17979480SEMICONDUCTOR PACKAGE HAVING TWO-DIMENSIONAL INPUT AND OUTPUT DEVICENovember 2022June 2025Allow3100NoNo
17973318SEMICONDUCTOR PACKAGE WITH DUMMY MIM CAPACITOR DIEOctober 2022March 2024Allow1720YesNo
17957012CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAMESeptember 2022December 2025Allow3810NoNo
17954745DISPLAY MODULE AND ELECTRONIC DEVICE INCLUDING THE SAMESeptember 2022September 2025Allow3510NoNo
17902902ELECTRONIC PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFSeptember 2022November 2025Allow3810YesNo
17902912PACKAGE-LEVEL ESD PROTECTIONSeptember 2022June 2025Allow3310NoNo
17888177DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGEAugust 2022March 2024Allow1920NoNo
17815634SEMICONDUCTOR PACKAGEJuly 2022October 2025Allow3920YesNo
17874402Semiconductor Device Package and Method of ManufactureJuly 2022August 2024Allow2520NoNo
17814716Controlling Threshold Voltages Through Blocking LayersJuly 2022December 2023Allow1710NoNo
17814730Packages with Thick RDLs and Thin RDLs Stacked AlternatinglyJuly 2022March 2024Allow2010NoNo
17870099GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATEJuly 2022December 2023Allow1720NoNo
17869080Connector Formation Methods and Packaged Semiconductor DevicesJuly 2022January 2026Allow4250YesNo
17862482FAN-OUT SEMICONDUCTOR PACKAGEJuly 2022January 2025Allow3000NoNo
17858905ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFJuly 2022April 2025Allow3300NoNo
17809921Silicon Oxide Layer for Oxidation Resistance and Method Forming SameJune 2022July 2024Allow2420NoNo
17790247DISPLAY PANELJune 2022February 2025Allow3100NoNo
17853204LOW INSERTION LOSS COAXIAL THROUGH-HOLE FOR HIGHSPEED INPUT-OUPUTJune 2022March 2026Allow4510NoNo
17847407PACKAGING ARCHITECTURE WITH CAVITIES FOR EMBEDDED INTERCONNECT BRIDGESJune 2022September 2025Allow3900NoNo
17807475ELECTRONIC ASSEMBLY HAVING MULTIPLE SUBSTRATE SEGMENTSJune 2022November 2024Allow2930NoNo
17824194SEMICONDUCTOR PACKAGEMay 2022January 2025Allow3210NoNo
17776685SUBSTRATE BONDINGMay 2022April 2025Allow3500NoNo
17733170METHODS AND APPARATUS TO IMPROVE SIGNAL INTEGRITY PERFORMANCE IN INTEGRATED CIRCUIT PACKAGESApril 2022December 2025Allow4410YesNo
17728761HOMOGENEOUS CHIPLETS CONFIGURABLE AS A TWO-DIMENSIONAL SYSTEM OR A THREE-DIMENSIONAL SYSTEMApril 2022July 2024Allow2700NoNo
17717250SIGNAL LINES IN MEMORY DEVICES AND METHODS FOR FORMING THE SAMEApril 2022January 2025Allow3410NoNo
17656729MULTI-LAYERED STRUCTURE INTERFACE BETWEEN A BALL GRID ARRAY DEVICE AND A PRINTED CIRCUIT BOARDMarch 2022May 2024Allow2600NoNo
17695859DISPLAY DEVICE AND SPLICING DISPLAY DEVICEMarch 2022May 2025Allow3810NoNo
17683774SEMICONDUCTOR PACKAGEMarch 2022January 2025Allow3520YesNo
17682238DIELECTRIC ANCHORS FOR ANCHORING A CONDUCTIVE PILLARFebruary 2022August 2024Allow3001NoNo
17638681DISPLAY DEVICE AND DISPLAY UNITFebruary 2022December 2024Allow3320YesNo
17679861SEMICONDUCTOR PACKAGEFebruary 2022February 2024Allow2420YesNo
17676862PACKAGE SUBSTRATE AND PACKAGE STRUCTUREFebruary 2022August 2024Allow3000NoNo
17677702SEMICONDUCTOR DIE DIPPING STRUCTUREFebruary 2022March 2025Allow3700NoNo
17676233STACKED DIE STRUCTURE AND METHOD OF FABRICATING THE SAMEFebruary 2022May 2024Allow2720NoNo
17670391MONOLITHIC CONDUCTIVE COLUMN IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODSFebruary 2022March 2025Allow3721NoNo
17670393MONOLITHIC CONDUCTIVE CYLINDER IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODSFebruary 2022April 2025Allow3811NoNo
17591084INTEGRATED CIRCUIT PACKAGE WITH DECOUPLING CAPACITORSFebruary 2022March 2025Allow3830YesNo
17631254MOLDED SILICON INTERCONNECTS IN BRIDGES FOR INTEGRATED-CIRCUIT PACKAGESJanuary 2022October 2024Allow3220NoNo
17648425SEMICONDUCTOR PACKAGEJanuary 2022September 2024Allow3220NoNo
17580368SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPSJanuary 2022July 2024Allow3010NoNo
17578965SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEJanuary 2022May 2024Abandon2820YesNo
17562477SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAMEDecember 2021March 2024Allow2610NoNo
17561722ULTRA LOW LOSS ROUTING BETWEEN GLASS CORESDecember 2021July 2025Allow4310NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TYNES JR., LAWRENCE C.

Strategic Value of Filing an Appeal

Total Appeal Filings
3
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
3
(100.0%)
Filing Benefit Percentile
7.8%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner TYNES JR., LAWRENCE C - Prosecution Strategy Guide

Executive Summary

Examiner TYNES JR., LAWRENCE C works in Art Unit 2899 and has examined 75 patent applications in our dataset. With an allowance rate of 94.7%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.

Allowance Patterns

Examiner TYNES JR., LAWRENCE C's allowance rate of 94.7% places them in the 83% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by TYNES JR., LAWRENCE C receive 1.88 office actions before reaching final disposition. This places the examiner in the 45% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TYNES JR., LAWRENCE C is 35 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +7.3% benefit to allowance rate for applications examined by TYNES JR., LAWRENCE C. This interview benefit is in the 36% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 38.1% of applications are subsequently allowed. This success rate is in the 87% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 45.5% of cases where such amendments are filed. This entry rate is in the 69% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 96% percentile among all examiners. Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 5% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 34% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.