USPTO Examiner PAYEN MARVIN - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18680896USING SPECTROSCOPIC MEASUREMENTS FOR SUBSTRATE TEMPERATURE MONITORINGMay 2024January 2025Allow700NoNo
18505083RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND FORMING METHOD THEREOFNovember 2023March 2025Allow1600NoNo
18496889OLED DISPLAY PANEL AND PREPARATION METHOD THEREOFOctober 2023March 2026Allow2800NoNo
18379423INTEGRATED CIRCUIT, METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT, WAFER AND METHOD FOR MANUFACTURING A WAFEROctober 2023December 2024Allow1400NoNo
18239104MEMORY DEVICEAugust 2023December 2024Allow1500NoNo
18239108MANUFACTURING METHOD OF MEMORY DEVICEAugust 2023October 2024Allow1300NoNo
18361373INTEGRATED CIRCUITJuly 2023January 2025Allow1820NoNo
18224054RRAM AND FABRICATING METHOD OF THE SAMEJuly 2023October 2025Allow2700NoNo
18353498Semiconductor Device and Method of Forming the SameJuly 2023October 2024Allow1511NoNo
18348146WAFER PROCESSING TOOLS AND METHODS THEREOFJuly 2023June 2024Allow1101NoNo
18338707VARIABLE RESISTANCE MEMORY DEVICEJune 2023May 2025Allow2300NoNo
18335940STRAINED TRANSISTORS AND PHASE CHANGE MEMORYJune 2023July 2024Allow1300NoNo
18332261METHOD OF SUPPLYING CHEMICAL LIQUIDJune 2023June 2025Allow2412NoNo
18205208ANTENNA ASSISTED RERAM FORMATIONJune 2023March 2025Allow2100NoNo
18254981RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF PREPARING THE SAMEMay 2023February 2026Allow3210NoNo
18253422SEMICONDUCTOR DEVICEMay 2023February 2026Allow3310NoNo
18196891REPLACEMENT GATE FORMATION IN MEMORYMay 2023July 2024Allow1500NoNo
18196044Resistive Change Elements Using Nanotube Fabrics Employing Break-Type Switching SitesMay 2023October 2025Allow2900NoNo
18310361RRAM DEVICE STRUCTURE AND MANUFACTURING METHODMay 2023June 2025Allow2600NoNo
18309564Semiconductor Device and Method of ManufactureApril 2023July 2024Allow1500NoNo
18140677RESISTIVE RANDOM-ACCESS MEMORY ELEMENTS WITH LATERAL SIDEWALL SWITCHINGApril 2023September 2025Allow2800NoNo
18305537NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAMEApril 2023June 2024Allow1400NoNo
18134048RESISTIVE RANDOM ACCESS MEMORY STRUCTURE AND FABRICATING METHOD OF THE SAMEApril 2023July 2025Allow2700NoNo
18298132HIGH-FREQUENCY, LOW-VOLTAGE SWITCH DEVICES AND METHODS OF MANUFACTURING THEREOFApril 2023October 2025Allow3000NoNo
18191885MEMORY ARRAY, SEMICONDUCTOR CHIP AND MANUFACTURING METHOD OF MEMORY ARRAYMarch 2023July 2024Allow1600NoNo
18186229STACKED RESISTIVE RANDOM-ACCESS MEMORY CROSS-POINT CELLMarch 2023February 2026Allow3500NoNo
18168038SEMICONDUCTOR DEVICEFebruary 2023May 2025Allow2700NoNo
18166479SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEFebruary 2023February 2026Allow3600NoNo
18158958DISPLAY DEVICE AND TILED DISPLAY DEVICEJanuary 2023March 2026Allow3700NoNo
18068155STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH ANCHORSDecember 2022October 2025Allow3400NoNo
18082155METHOD OF DETECTING A POSSIBLE THINNING OF A SUBSTRATE OF AN INTEGRATED CIRCUIT VIA THE REAR FACE THEREOF, AND ASSOCIATED DEVICEDecember 2022July 2024Allow1900NoNo
18076726BUFFER LAYER IN MEMORY CELL TO PREVENT METAL REDEPOSITIONDecember 2022January 2025Allow2511NoNo
17989085VARIABLE RESISTANCE MEMORY DEVICENovember 2022April 2025Allow2900NoNo
17977164SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFOctober 2022March 2024Allow1700NoNo
17937094DEVICES INCLUDING A PASSIVE MATERIAL BETWEEN MEMORY CELLS AND CONDUCTIVE ACCESS LINES, AND RELATED ELECTRONIC DEVICESSeptember 2022February 2025Allow2810NoNo
17952838Impedance Controlled Electrical Interconnection Employing Meta-MaterialsSeptember 2022February 2024Allow1700NoNo
17874861SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFORJuly 2022June 2025Allow3500NoNo
17874448MEMORY ARRAY WITH ASYMMETRIC BIT-LINE ARCHITECTUREJuly 2022December 2023Allow1700NoNo
17865994Fine Pitch BVA Using Reconstituted Wafer With Area Array Accessible For TestingJuly 2022December 2023Allow1700NoNo
17810590SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAMEJuly 2022February 2026Allow4310NoNo
17807645FINFET CHANNEL ON OXIDE STRUCTURES AND RELATED METHODSJune 2022December 2023Allow1800NoNo
17776259TUNABLE INDUCTOR DEVICEMay 2022August 2025Allow3900NoNo
17738366THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MEMORYMay 2022April 2025Allow3500NoNo
17738007MEMORY DEVICE AND METHOD OF FORMING THE SAME AND INTEGRATED CIRCUITMay 2022February 2026Allow4610NoNo
17735529TECHNOLOGIES FOR SEMICONDUCTOR DEVICES INCLUDING AMORPHOUS SILICONMay 2022February 2026Allow4611NoNo
17729258PAD STRUCTURE FOR FRONT SIDE ILLUMINATED IMAGE SENSORApril 2022January 2024Allow2100NoNo
17705537Field Effect Transistor Contact with Reduced Contact ResistanceMarch 2022July 2024Allow2701NoNo
17701144VERTICAL 1T1R STRUCTURE FOR EMBEDDED MEMORYMarch 2022August 2025Allow4101NoNo
17697974PROGRAMMABLE INTERPOSER USING RRAM PLATFORMMarch 2022January 2025Allow3400NoNo
17654911RESISTIVE SWITCHING MEMORY CELLMarch 2022June 2025Allow3900NoNo
17693340SOLID-STATE SWITCHMarch 2022October 2025Allow4301NoNo
17689604SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICEMarch 2022October 2024Allow3100NoNo
17687968MEMRISTOR DEVICES EMBEDDED IN DIELECTRICSMarch 2022September 2024Allow3000NoNo
17683318REPAIR TECHNIQUES FOR MICRO-LED DEVICES AND ARRAYSFebruary 2022March 2024Allow2500NoNo
17636833A Resistive Memory Device Structure Based on Stacked Layers Of Nanocrystalline TMDCsFebruary 2022October 2024Allow3210NoNo
17671731SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTUREFebruary 2022July 2024Allow2900NoNo
17647006SEMICONDUCTOR MEMORY DEVICES HAVING AN ELECTRODE WITH AN EXTENSIONJanuary 2022June 2024Allow2900NoNo
17546772SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEDecember 2021February 2024Allow2600NoNo
17545635STACKED CROSS-POINT PHASE CHANGE MEMORYDecember 2021April 2025Allow4000NoNo
17457930CROSSBAR MEMORY ARRAY IN BACK END OF LINE WITH CRYSTALLIZATION FRONTDecember 2021March 2025Allow3900NoNo
17457928CROSSBAR MEMORY ARRAY IN BACK END OF LINEDecember 2021March 2025Allow4001NoNo
17543957PHASE CHANGE MEMORY PROGRAMMING CURRENT LEAKAGE REDUCTIONDecember 2021March 2025Allow4000NoNo
17536927FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICENovember 2021September 2024Allow3401NoNo
17537071NEUROMORPHIC MEMRISTOR DEVICE BASED ON VERTICALLY-ORIENTED HALIDE PEROVSKITE NANOSTRUCTURE AND METHOD OF MANUFACTURING THE SAMENovember 2021February 2025Allow3920NoNo
17527648RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING SAMENovember 2021September 2024Allow3410NoNo
17453346MEMORY CELL WITH COMB-SHAPED ELECTRODESNovember 2021March 2025Allow4101NoNo
17511706ELECTROLUMINESCENT DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE COMPRISING THE SAMEOctober 2021June 2024Allow3220NoNo
17499709TECHNIQUES FOR MANUFACTURING A DOUBLE ELECTRODE MEMORY ARRAYOctober 2021July 2023Allow2100NoNo
17483868RESISTIVE SWITCHING DEVICE HAVING A PROTECTIVE ELECTRODE RINGSeptember 2021October 2024Allow3610NoNo
17477119MEMRISTOR AND PREPARATION METHOD THEREOFSeptember 2021July 2024Allow3410NoNo
17474103TRANSFORMER DESIGN WITH BALANCED INTERWINDING CAPACITANCE FOR IMPROVED EMI PERFORMANCESeptember 2021March 2024Allow3000NoNo
17399194VARIABLE RESISTANCE MEMORY DEVICEAugust 2021April 2024Allow3200YesNo
17444840BACK END OF LINE EMBEDDED RRAM STRUCTURE WITH GRAIN GROWTH ENHANCEMENTAugust 2021September 2024Allow3720NoNo
17444841BACK END OF LINE EMBEDDED RRAM STRUCTURE WITH LOW FORMING VOLTAGEAugust 2021September 2024Allow3721NoNo
17362075CHALCOGEN COMPOUND AND SEMICONDUCTOR DEVICE INCLUDING THE SAMEJune 2021March 2024Allow3311NoNo
17358293PHASE CHANGE MEMORY WITH GRADED HEATERJune 2021March 2025Allow4430YesNo
17350152DIE COUPLING USING A SUBSTRATE WITH A GLASS COREJune 2021February 2025Allow4401NoNo
17349777DIE TO DIE HIGH-SPEED COMMUNICATION WITHOUT DISCRETE AMPLIFIERS BETWEEN A MIXER AND TRANSMISSION LINEJune 2021September 2024Allow3900NoNo
17203172NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD OF THE NONVOLATILE SEMICONDUCTOR MEMORY DEVICEMarch 2021December 2023Allow3310NoNo
17178086REACTOR TO FORM FILMS ON SIDEWALLS OF MEMORY CELLSFebruary 2021May 2025Allow5151NoNo
17000457Deposition Of Metal-Organic Oxide FilmsAugust 2020July 2024Abandon4731NoNo
16128711FLEXIBLE DISPLAY DEVICE MANUFACTURING METHOD AND MANUFACTURING APPARATUSSeptember 2018October 2019Allow1300NoNo
15825231REDUCING TIP-TO-TIP DISTANCE BETWEEN END PORTIONS OF METAL LINES FORMED IN AN INTERCONNECT LAYER OF AN INTEGRATED CIRCUIT (IC)November 2017December 2018Allow1301YesNo
15824559SYSTEMS AND METHODS FOR TEMPERATURE SENSOR ACCESS IN DIE STACKSNovember 2017July 2024Abandon6071NoYes
15689473STACKED COMPLEMENTARY JUNCTION FETS FOR ANALOG ELECTRONIC CIRCUITSAugust 2017March 2019Allow1902YesNo
15471733SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATIONMarch 2017May 2017Allow200NoNo
15339402GATE HEIGHT AND SPACER UNIFORMITYOctober 2016March 2017Allow401NoNo
15279840SEMICONDUCTOR DEVICESeptember 2016January 2018Allow1610NoNo
15236603PLASMA CURING OF PECVD HMDSO FILM FOR OLED APPLICATIONSAugust 2016October 2016Allow200NoNo
15219738SEMICONDUCTOR MEMORY DEVICEJuly 2016January 2018Allow1810NoNo
15175595Semiconductor DeviceJune 2016October 2016Allow500NoNo
14974589SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATIONDecember 2015December 2016Allow1201NoNo
14876023FORMING INTERCONNECT FEATURES WITH REDUCED SIDEWALL TAPERINGOctober 2015February 2016Allow400NoNo
14874623AMORPHIZATION INDUCED METAL-SILICON CONTACT FORMATIONOctober 2015June 2018Allow3311NoNo
14617499Resistive Memory Cell Array With Top Electrode Bit LineFebruary 2015July 2015Allow500NoNo
14607955ONE TRANSISTOR AND ONE RESISTIVE (1T1R) RANDOM ACCESS MEMORY (RAM) STRUCTURE WITH DUAL SPACERSJanuary 2015March 2015Allow100NoNo
14312628Method for Reducing Forming Voltage in Resistive Random Access MemoryJune 2014July 2017Allow3720NoNo
14190604Lighting Device, Backlight Module And Illumination ModuleFebruary 2014February 2018Allow4720YesNo
14190874SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEFebruary 2014August 2017Allow4211NoNo
14180098INTEGRATED CLUSTER TO ENABLE NEXT GENERATION INTERCONNECTFebruary 2014July 2015Allow1711NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PAYEN, MARVIN.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
1
(50.0%)
Examiner Reversed
1
(50.0%)
Reversal Percentile
76.0%
Higher than average

What This Means

With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
3
Allowed After Appeal Filing
1
(33.3%)
Not Allowed After Appeal Filing
2
(66.7%)
Filing Benefit Percentile
53.9%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner PAYEN, MARVIN - Prosecution Strategy Guide

Executive Summary

Examiner PAYEN, MARVIN works in Art Unit 2899 and has examined 74 patent applications in our dataset. With an allowance rate of 97.3%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 32 months.

Allowance Patterns

Examiner PAYEN, MARVIN's allowance rate of 97.3% places them in the 88% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by PAYEN, MARVIN receive 1.07 office actions before reaching final disposition. This places the examiner in the 11% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PAYEN, MARVIN is 32 months. This places the examiner in the 52% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +3.0% benefit to allowance rate for applications examined by PAYEN, MARVIN. This interview benefit is in the 24% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 35.1% of applications are subsequently allowed. This success rate is in the 79% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 31.2% of cases where such amendments are filed. This entry rate is in the 45% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 100.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 75% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 60.0% of appeals filed. This is in the 36% percentile among all examiners. Of these withdrawals, 33.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 33.3% are granted (fully or in part). This grant rate is in the 21% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 4.1% of allowed cases (in the 83% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 34% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.