USPTO Examiner JEFFERSON QUOVAUNDA - Art Unit 2899

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18739344TRANSISTOR STRUCTURE WITH AIR GAP AND METHOD OF FABRICATING THE SAMEJune 2024July 2025Allow1320NoNo
18735584Light-Emitting Element, Light-Emitting Device, Display Device, Lighting Device, and Electronic DeviceJune 2024September 2025Allow1610NoNo
18732009METHOD FOR FABRICATING ELECTRONIC PACKAGEJune 2024June 2025Allow1210NoNo
18404665SEMICONDUCTOR SUBSTRATEJanuary 2024February 2025Allow1410NoNo
18396575INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOFDecember 2023May 2025Allow1610NoNo
18526429METHOD FOR FORMING SEMICONDUCTOR DEVICEDecember 2023June 2025Allow1810NoNo
18515961SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMENovember 2023December 2024Allow1300NoNo
18508595SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAMENovember 2023May 2025Allow1820NoNo
18388883SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMENovember 2023July 2025Allow2020NoNo
18500291TRENCH CAPACITORNovember 2023May 2025Allow1810NoNo
18497172METHODS OF CUTTING A FINE PATTERN, METHODS OF FORMING ACTIVE PATTERNS USING THE SAME, AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAMEOctober 2023January 2025Allow1410NoNo
18383385METHODS AND COMPOSITIONS FOR SURFACE FUNCTIONALIZATION OF OPTICAL SEMICONDUCTOR-INTEGRATED BIOCHIPSOctober 2023March 2025Allow1710NoNo
18486399METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIOOctober 2023March 2025Allow1710NoNo
18479871NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMEOctober 2023July 2024Allow900NoNo
18231912SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAMEAugust 2023March 2025Allow1900NoNo
18446583METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEAugust 2023February 2026Allow3010NoNo
18359735DEPOSITION WINDOW ENLARGEMENTJuly 2023January 2025Allow1820NoNo
18224904TECHNIQUES FOR VOID-FREE MATERIAL DEPOSITIONSJuly 2023July 2024Allow1210NoNo
18356694CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORSJuly 2023December 2024Allow1710NoNo
18354887Method of Forming Backside Power RailsJuly 2023September 2024Allow1410NoNo
18223521DISPLAY DEVICEJuly 2023June 2024Allow1110NoNo
18343544ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAMEJune 2023April 2024Allow1010NoNo
18342192SEMICONDUCTOR STRUCTURE INCLUDING DEVICES WITH DIFFERENT CHANNEL LENGTHS, AND METHOD FOR MANUFACTURING THE SAMEJune 2023January 2026Allow3101NoNo
18209217HALOGEN-FREE MOLYBDENUM-CONTAINING PRECURSORS FOR DEPOSITION OF MOLYBDENUMJune 2023December 2025Allow3100NoNo
18209035SELECTIVE SELF-ASSEMBLED MONOLAYER (SAM) REMOVALJune 2023February 2026Allow3210NoNo
18209257OXIDATION BARRIERS WITH CVD SOAK PROCESSESJune 2023August 2025Allow2700NoNo
18206427SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICESJune 2023March 2026Allow3310NoNo
18318917BARRIER FREE INTERFACE BETWEEN BEOL INTERCONNECTSMay 2023March 2025Allow2230NoNo
18317227SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTORMay 2023January 2025Allow2020NoNo
18305536Method for Reducing Line-End Space in Integrated Circuit PatterningApril 2023August 2024Allow1610NoNo
18194098VAPOR DEPOSITION OF TELLURIUM NANOMESH ELECTRONICS ON ARBITRARY SURFACES AT LOW TEMPERATUREMarch 2023December 2025Allow3310NoNo
18193041SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFMarch 2023February 2026Allow3510YesNo
18191707TEMPERATURE CHANGE RATE CONTROL DEVICE, METHOD, AND SEMICONDUCTOR PROCESS APPARATUSMarch 2023September 2024Allow1800NoNo
18190868SEMICONDUCTOR DEVICE WITH LOW-GALVANIC CORROSION STRUCTURES, AND METHOD OF MAKING SAMEMarch 2023June 2025Allow2620NoNo
18112159Methods for Transferring Graphene to Substrates and Related Lithographic Stacks and LaminatesFebruary 2023November 2025Allow3300NoNo
18112463SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAMEFebruary 2023December 2024Allow2220NoNo
18112431ELECTRONIC PACKAGE ASSEMBLY WITH STIFFENERFebruary 2023November 2025Allow3350YesNo
18171839SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR MANUFACTURING THE SAMEFebruary 2023November 2025Allow3301NoNo
18169799THIN FILM DEPOSITION METHOD AND MANUFACTURING METHOD OF ELECTRONIC DEVICE APPLYING THE SAMEFebruary 2023December 2025Allow3410NoNo
18162951METHODS OF MANUFACTURING SEMICONDUCTOR-ON-INSULATOR WAFERS HAVING CHARGE TRAPPING LAYERS WITH CONTROLLED STRESSFebruary 2023March 2026Allow3720NoNo
18018913SEMICONDUCTOR LAMINATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEJanuary 2023November 2025Allow3410NoNo
18152134SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJanuary 2023September 2025Allow3220NoNo
18013370METHOD FOR PRODUCING A GALLIUM OXIDE SEMICONDUCTOR FILM AND A FILM FORMING APPARATUSDecember 2022December 2025Allow3610NoNo
17992905MEMS SENSOR AND METHOD OF MANUFACTURING MEMS SENSORNovember 2022August 2025Allow3300NoNo
17991090SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMENovember 2022August 2025Allow3220YesNo
17922846METHOD FOR MANUFACTURING SOI WAFERNovember 2022December 2025Allow3820NoNo
18051182Light Emitting Diode and Fabrication Method ThereofOctober 2022May 2024Allow1910NoNo
17920227METHOD FOR FORMING THERMAL OXIDE FILM ON SEMICONDUCTOR SUBSTRATEOctober 2022February 2025Allow2800NoNo
17959557Methods for Forming Self-Aligned Contacts Using Spin-on Silicon CarbideOctober 2022May 2024Allow1910NoNo
17907224SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUSSeptember 2022August 2025Allow3510YesNo
17951756Method for Making Silicon Epitaxy of a FDSOI DeviceSeptember 2022June 2025Allow3310NoNo
17950481METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUMSeptember 2022October 2025Allow3710NoNo
17940949TRANSISTOR INCLUDING WRAP AROUND SOURCE AND DRAIN CONTACTSSeptember 2022July 2024Allow2220YesNo
17929311STRUCTURE MANUFACTURING METHODSeptember 2022March 2025Allow3000YesNo
17822008METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICESAugust 2022January 2026Allow4111NoNo
17880885HIGH CONDUCTANCE DIVERT LINE ARCHITECTUREAugust 2022June 2025Allow3400NoNo
17873313FULLY SELF-ALIGNED VIAJuly 2022April 2024Abandon2010NoNo
17873442Integrated Circuit Package and MethodJuly 2022December 2024Allow2900NoNo
17795154METHOD FOR FABRICATING ELECTRODE BASED ON LIQUID METALJuly 2022October 2025Allow3920NoNo
17868927CONTACT PLUGJuly 2022June 2024Allow2320NoNo
17856173METHOD OF MANUFACTURING DIAMOND SUBSTRATEJuly 2022January 2026Allow4210NoNo
17825664DEEP TRENCH VIA FOR THREE-DIMENSIONAL INTEGRATED CIRCUITMay 2022May 2024Allow2410NoNo
17756431METHOD FOR BONDING TWO SUBSTRATESMay 2022July 2024Allow2610NoNo
17779474SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOFMay 2022October 2024Allow2810NoNo
17737011TRANSISTOR STRUCTURE WITH AIR GAP AND METHOD OF FABRICATING THE SAMEMay 2022April 2024Allow2420NoNo
17736188METHODS FOR NEAR SURFACE WORK FUNCTION ENGINEERINGMay 2022September 2023Allow1700NoNo
17722611THIN FILM TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAMEApril 2022February 2025Allow3440NoNo
17720789AIR GAP FORMATION METHODApril 2022May 2024Allow2510NoNo
17714660Semiconductor Transistor Device and Method of Manufacturing the SameApril 2022June 2024Allow2620NoNo
17655510SEMICONDUCTOR DEVICES AND METHODS OF FORMATIONMarch 2022February 2025Allow3521YesNo
17642533SYSTEM AND METHOD FOR CONNECTING ELECTRONIC ASSEMBLIESMarch 2022February 2023Allow1100NoNo
17688343METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH A LOW-RESISTIVITY METALMarch 2022December 2024Allow3320NoNo
17678093METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING ACTIVE PATTERNS ON A BONDING LAYER AND SEMICONDUCTOR DEVICES FORMED BY THE SAMEFebruary 2022June 2024Allow2720YesNo
17299051METHOD FOR MANUFACTURING GALLIUM OXIDE FILMFebruary 2022February 2025Allow4520NoNo
17588920Methods of Packaging Semiconductor Devices and Packaged Semiconductor DevicesJanuary 2022March 2025Allow3730YesNo
17588708SEMICONDUCTOR FILMJanuary 2022July 2024Allow3010YesNo
17582782DEVICES WITH ADJUSTED FIN PROFILE AND METHODS FOR MANUFACTURING DEVICES WITH ADJUSTED FIN PROFILEJanuary 2022March 2024Allow2610NoNo
17577656FILM FORMING METHOD AND FILM FORMING APPARATUSJanuary 2022April 2024Allow2700NoNo
175694193D FLASH MEMORY MODULE CHIP AND METHOD OF FABRICATING THE SAMEJanuary 2022April 2025Allow3910NoNo
17567613SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEJanuary 2022August 2023Allow1900NoNo
17562238OPTICAL INSPECTION APPARATUS IN SEMICONDUCTOR PROCESS SYSTEMDecember 2021May 2025Allow4010NoNo
17548689DEPOSITION OF BORON FILMSDecember 2021June 2025Allow4230NoNo
17547669DOPANT-FREE INHIBITOR FOR AREA SELECTIVE DEPOSITIONSDecember 2021October 2025Abandon4601NoNo
17546303METHOD OF PATTERNING TWO-DIMENSIONAL MATERIAL LAYER ON SUBSTRATE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICEDecember 2021December 2023Allow2410YesNo
17545667THERMAL TRANSFER STRUCTURES FOR SEMICONDUCTOR DIE ASSEMBLIESDecember 2021August 2023Allow2110NoNo
17545209FIN FIELD-EFFECT TRANSISTOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEDecember 2021May 2025Allow4220NoNo
17544776METHODS AND COMPOSITIONS FOR SURFACE FUNCTIONALIZATION OF OPTICAL SEMICONDUCTOR-INTEGRATED BIOCHIPSDecember 2021July 2023Allow1931YesNo
17540552METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEDecember 2021March 2024Allow2720NoNo
17538760THERMAL ATOMIC LAYER DEPOSITION OF TERNARY GALLIUM OXIDE THIN FILMSNovember 2021June 2025Allow4330NoNo
17613324SOLUTION-BASED DEPOSITION METHOD FOR PREPARING SEMICONDUCTING THIN FILMS VIA DISPERSED PARTICLE SELF-ASSEMBLY AT A LIQUID-LIQUID INTERFACENovember 2021April 2024Allow2910NoNo
17609629METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICENovember 2021October 2025Allow4740NoNo
17511042METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH FINE PATTERNS AT DIFFERENT LEVELSOctober 2021July 2023Allow2110NoNo
17508419CARBON GAP FILL PROCESSESOctober 2021October 2024Allow3610YesNo
17474973SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICESeptember 2021July 2024Allow3410NoNo
17474067METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURESeptember 2021May 2024Allow3210NoNo
17472825METHOD FOR MANUFACTURING SEMICONDUCTOR AND MULTI-PIECE DEPOSITION DEVICESeptember 2021December 2024Abandon3920NoNo
17473302COMPOSITION FOR FORMING UNDERLAYER FILM FOR IMPRINTING, METHOD FOR PRODUCING COMPOSITION FOR FORMING UNDERLAYER FILM, KIT, PATTERN PRODUCING METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENTSeptember 2021June 2025Allow4520NoNo
17471703STACKED CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOFSeptember 2021October 2024Allow3701NoNo
17469992METHOD FOR DETERMINING CONTOUR OF SEMICONDUCTOR STRUCTURESeptember 2021June 2024Allow3300NoNo
17468909METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURESeptember 2021May 2024Allow3210NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner JEFFERSON, QUOVAUNDA.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
3
Examiner Affirmed
1
(33.3%)
Examiner Reversed
2
(66.7%)
Reversal Percentile
87.1%
Higher than average

What This Means

With a 66.7% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
19
Allowed After Appeal Filing
7
(36.8%)
Not Allowed After Appeal Filing
12
(63.2%)
Filing Benefit Percentile
60.6%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 36.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner JEFFERSON, QUOVAUNDA - Prosecution Strategy Guide

Executive Summary

Examiner JEFFERSON, QUOVAUNDA works in Art Unit 2899 and has examined 601 patent applications in our dataset. With an allowance rate of 84.0%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 29 months.

Allowance Patterns

Examiner JEFFERSON, QUOVAUNDA's allowance rate of 84.0% places them in the 59% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by JEFFERSON, QUOVAUNDA receive 2.53 office actions before reaching final disposition. This places the examiner in the 74% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by JEFFERSON, QUOVAUNDA is 29 months. This places the examiner in the 66% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +5.2% benefit to allowance rate for applications examined by JEFFERSON, QUOVAUNDA. This interview benefit is in the 30% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 27.3% of applications are subsequently allowed. This success rate is in the 47% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 38.3% of cases where such amendments are filed. This entry rate is in the 58% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 66.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 56% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 85.0% of appeals filed. This is in the 78% percentile among all examiners. Of these withdrawals, 47.1% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 52.9% are granted (fully or in part). This grant rate is in the 53% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.2% of allowed cases (in the 51% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 5.1% of allowed cases (in the 81% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.