USPTO Art Unit 2824 Prosecution Statistics

Art Unit Information

Art Unit: 2824
Group: 2820
Tech Center: 2800
Total Cases: 25,102
Last Active: June 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
192453493D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATHJune 2025March 2026Allow900NoNo
189916313D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYDecember 2024June 2025Allow500NoNo
17766568NON-VOLATILE STORAGE CIRCUITOctober 2024July 2024Allow2820NoNo
18820305DATA BUFFER CIRCUIT STRUCTURE, LAYOUT STRUCTURE OF MULTIPLE DATA BUFFER CIRCUITS, AND MEMORYAugust 2024February 2026Allow1700NoNo
18818260SCHEDULING SCAN OPERATIONS IN MEMORY SUB-SYSTEMSAugust 2024March 2026Allow1900NoNo
18810552SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAMPLING CIRCUITAugust 2024February 2026Allow1800NoNo
18837881CMOS SRAM CELL HAVING TRENCH STRUCTUREAugust 2024January 2025Allow500NoNo
18797883INTEGRATED CIRCUIT DEVICEAugust 2024February 2026Allow1800NoNo
18797072PRE-CHARGE AT READ RECOVERY CLOCK FROM BIT LINE SIDE FOR SUB-BLOCK ONE PERFORMANCE IMPROVEMENTAugust 2024March 2026Allow1900NoNo
18795750MEMORY DEVICES AND METHODS OF PERFORMING ROW ACCESS COUNTING OPERATIONSAugust 2024March 2026Allow1900NoNo
18789866SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAMEJuly 2024March 2026Allow1910NoNo
18789717Pulse Signal Generator System for a Magnetoresistive Random Access Memory ArrayJuly 2024January 2026Allow1700NoNo
18788725WORD LINE BOOSTER CIRCUIT AND METHODJuly 2024February 2026Allow1800NoNo
18788496PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING A PAGE BUFFER CIRCUITJuly 2024February 2026Allow1900NoNo
18789412WRITE LATENCY TESTING SYSTEMS AND METHODSJuly 2024March 2026Allow1900NoNo
18786588CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF MEMORYJuly 2024February 2026Allow1910NoNo
18785463WORDLINE GROUP DEPENDENT CORRECTIVE PROGRAM VERIFY OPERATION IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18785362ALL LEVELS PROGRAM OPERATION INTEGRATED WITH CORRECTIVE PROGRAM VERIFY OPERATION IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18784049MEMORY DEVICES AND OPERATION METHODS THEREOF, AND MEMORY SYSTEMSJuly 2024February 2026Allow1900NoNo
187789783D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATHJuly 2024June 2025Allow1100NoNo
18772714CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICEJuly 2024May 2025Allow1010NoNo
18771817NON-VOLATILE MEMORY STORED WITH ENCODED DATAJuly 2024February 2025Allow700NoNo
18767988SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATINGJuly 2024January 2026Allow1800NoNo
18768033SEMICONDUCTOR MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18764906MEMORY SYSTEMJuly 2024June 2025Allow1110NoNo
18764399SENSING CIRCUIT OF MEMORY DEVICE AND CONTROL METHOD OF SENSING CIRCUITJuly 2024February 2026Allow2000NoNo
18763964SELF-TIMING READ TERMINATIONJuly 2024December 2025Allow1800NoNo
18763067SEMICONDUCTOR MEMORY DEVICES WITH DIFFERENT WORD LINESJuly 2024February 2025Allow700NoNo
18761619MEMORY DEVICE WITH REDUNDANCY FOR PAGE-BASED REPAIRJuly 2024January 2025Allow700NoNo
18761321MEMORY DEVICE AND READ VOLTAGE SETTING METHOD THEREOFJuly 2024March 2026Allow2010NoNo
18759357Adjustable Clock and Power Gating ControlJune 2024December 2025Allow1800NoNo
18759032DRIFT COMPENSATION FOR CODEWORDS IN MEMORYJune 2024February 2026Allow2000NoNo
18758496ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICEJune 2024December 2025Allow1700NoNo
18758643REDUCTION IN CHIP AREA THROUGH DESIGN-TECHNOLOGY CO-OPTIMIZATIONJune 2024November 2025Allow1700NoNo
18757685THRESHOLD VOLTAGE-MODULATED MEMORY DEVICE USING VARIABLE-CAPACITANCE AND METHODS OF FORMING THE SAMEJune 2024January 2025Allow700NoNo
18757102SELECTOR ONLY MEMORY WRITE OPERATIONJune 2024January 2026Allow1900NoNo
18754433MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOFJune 2024January 2026Allow1900NoNo
18754884MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMSJune 2024February 2026Allow2000NoNo
18752638Scannable Memory SubsystemJune 2024March 2026Allow2110NoNo
18752008APPARATUS FOR TSV DATA OUTPUT CONTROL IN MULTIPLE CORE DIESJune 2024January 2026Allow1800NoNo
18752493SOLID STATE DRIVE (SSD) WITH IN-FLIGHT ERASURE ITERATION SUSPENSIONJune 2024December 2025Allow1800NoNo
18752079MEMORY CIRCUIT AND METHOD OF OPERATING THE SAMEJune 2024January 2026Allow1900NoNo
18750979HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCYJune 2024May 2025Allow1110NoNo
18751099MANAGING PROGRAM OPERATIONS IN MEMORY SYSTEMSJune 2024December 2025Allow1800NoNo
18749098METHOD AND SYSTEM FOR REPLACEMENT OF MEMORY CELLSJune 2024April 2025Allow910NoNo
18748196METHOD FOR PROGRAMMING MEMORYJune 2024May 2025Allow1110NoNo
18747626CIRCUIT SNAPBACK AND CHARGE DIVERSION FOR CROSS-POINT ARRAYSJune 2024March 2026Allow2110YesNo
18746964SEMICONDUCTOR MEMORY AND NONVOLATILE MEMORYJune 2024December 2025Allow1700NoNo
18744776MEMORY DEVICE WITH HIGH CONTENT DENSITY AND ENCODING METHOD THEREOFJune 2024January 2026Allow1900NoNo
18743818MEMORY SYSTEMS, OPERATING METHODS, AND READABLE STORAGE MEDIUMSJune 2024December 2025Allow1800NoNo
18743852PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAMEJune 2024February 2025Allow800NoNo
18741805PROGRAMMING VOLTAGE SUPPLY AND PROGRAMMING VOLTAGE GENERATING METHODJune 2024December 2025Allow1800NoNo
18742749TECHNIQUES FOR DETECTING A STATE OF A BUSJune 2024April 2025Allow1010NoNo
18741051SRAM STRUCTURESJune 2024August 2025Allow1410NoNo
18740981CURRENT AND VOLTAGE LIMIT CIRCUITRY FOR RESISTIVE RANDOM ACCESS MEMORY PROGRAMMINGJune 2024March 2025Allow910NoNo
18741201MEMORY INCLUDING METAL RAILS WITH BALANCED LOADINGJune 2024March 2025Allow910NoNo
18740400MEMORY DEVICE HAVING NON-UNIFORM REFRESHJune 2024December 2025Allow1820NoNo
187387213D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYJune 2024December 2024Allow610NoNo
18738172MEMORY DEVICE INCLUDING INTERFACE CIRCUIT AND METHOD OF OPERATING THE SAMEJune 2024December 2025Allow1820YesNo
187389673D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLSJune 2024December 2024Allow610NoNo
18736779BUILT-IN MEMORY REPAIR WITH REPAIR CODE COMPRESSIONJune 2024June 2025Allow1310NoNo
18735715RESISTIVE MEMORY DEVICE WITH PROTRUSION COVERED WITH RESISTANCE CHANGING ELEMENT AND METHOD FOR MANUFACTURING THE SAMEJune 2024July 2025Allow1310NoNo
18735967BIT-ERASABLE EMBEDDED SELECT IN TRENCH MEMORY (ESTM)June 2024March 2026Allow2110NoNo
18735812QUICK PASS WRITE WITH QUASI-LOW VERIFY HIGH LEVELJune 2024December 2025Allow1800NoNo
18733377RESAMPLE START VOLTAGE FOR CALIBRATION IN A PROGRAM OPERATION IMPROVEMENTJune 2024March 2026Allow2110NoNo
18733241DEVICE HAVING ROWS OF MRAM CELLS CONFIGURED FOR CONCURRENT WRITING AND READINGJune 2024November 2025Allow1700NoNo
18733187DETERMINING OFFSETS FOR MEMORY READ OPERATIONSJune 2024May 2025Allow1110NoNo
18733153INDUCTIVE ENERGY HARVESTING AND SIGNAL DEVELOPMENT FOR A MEMORY DEVICEJune 2024November 2025Allow1700NoNo
18732377MEMORY DEVICE WITH IMPROVED PROGRAM PERFORMANCE AND METHOD OF OPERATING THE SAMEJune 2024April 2025Allow1000NoNo
18731253APPARATUS AND METHODS FOR NEGATIVE THRESHOLD VOLTAGES FOR NONVOLATILE MEMORY DEVICESJune 2024January 2026Allow1900NoNo
18679956READ OPERATIONS WITH OFFSET FOR SLOW CHARGE LOSSMay 2024November 2025Allow1800NoNo
18680066FAKE FAST PLANE DETECTION IN EARLY PROGRAM TERMINATIONMay 2024January 2026Allow2000NoNo
18677654MAGNETIC DEVICE AND MAGNETIC RANDOM ACCESS MEMORYMay 2024April 2025Allow1010NoNo
18676719SENSE AMPLIFIER CIRCUIT, CORRESPONDING MEMORY DEVICE AND METHOD OF OPERATIONMay 2024November 2025Allow1700NoNo
18676385Se-BASED SELECTOR MATERIAL, SELECTOR UNIT AND METHOD FOR PREPARING THE SAMEMay 2024August 2024Allow200NoNo
18676267REDUCING PARTIAL BLOCK PROGRAMMING USING DYNAMIC TRIM SETTINGSMay 2024January 2026Allow2010NoNo
18672389APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLEMay 2024December 2025Allow1900NoNo
18671964MEMORY DEVICEMay 2024March 2026Allow2110NoNo
18670883MEMORY SYSTEMS AND DEVICES HAVING ENHANCED COLUMN REPAIR CAPABILITY AND METHODS OF OPERATING SAMEMay 2024February 2026Allow2110YesNo
18671835TRACKING RC TIME CONSTANT BY WORDLINE IN MEMORY DEVICESMay 2024April 2025Allow1100NoNo
18670778MEMORY MODULES INCLUDING A MIRRORING CIRCUIT AND METHODS OF OPERATING THE SAMEMay 2024April 2025Allow1110NoNo
18669795DEVICE AND METHOD FOR PERFORMING MATRIX OPERATIONMay 2024November 2025Allow1820NoNo
18669694STORAGE DEVICE PERFORMING DUMMY READ OPERATION, AND METHOD OF OPERATING THE SAMEMay 2024February 2026Allow2110NoNo
18669140MULTI-STATE PROGRAMMING OF MEMORY CELLSMay 2024April 2025Allow1110NoNo
18668540GRAY ENCODING FOR ANALOG CONTENT ADDRESSABLE MEMORY IN GENERAL COMPUTINGMay 2024November 2025Allow1800NoNo
18667358APPARATUSES AND METHODS FOR FORCING MEMORY CELL FAILURES IN A MEMORY DEVICEMay 2024November 2025Allow1810NoNo
18667153COMMON MODE SHIFTING OF SINGLE-ENDED SIGNALS BASED ON LINEARITY ANALYSISMay 2024November 2025Allow1800NoNo
18666819NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND READ METHOD OF MEMORY SYSTEMMay 2024January 2025Allow800NoNo
18667099SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED METHODS AND SYSTEMSMay 2024October 2025Allow1720NoNo
18665740ONE-TIME-PROGRAMMABLE MEMORY DEVICEMay 2024February 2026Allow2110NoNo
18709583SEMICONDUCTOR CIRCUITMay 2024December 2025Allow1900NoNo
18662945LEVEL-BASED DATA REFRESH IN A MEMORY SUB-SYSTEMMay 2024November 2025Allow1800NoNo
18662013MEMORY CELL ARRANGEMENTS AND METHOD OF OPERATING A MEMORY CELLMay 2024January 2026Allow2010NoNo
18662743DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPINGMay 2024May 2025Allow1210NoNo
18660338Far End Driver for Memory ClockMay 2024March 2025Allow1010NoNo
18656630SENSING APPARATUS FOR NON-VOLATILE MEMORYMay 2024November 2025Allow1800NoNo
18654012NONVOLATILE MEMORY READ WITH ASYMMETRIC READ-PASS VOLTAGESMay 2024February 2026Allow2110YesNo
18653688STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICEMay 2024January 2026Allow2110YesNo
18653418Multi-Bit Storage Device Using Phase Change MaterialMay 2024December 2024Allow700NoNo
18651357SEQUENTIAL ACCESS TO LINKED MEMORY DICE FOR BUS TRAININGApril 2024January 2026Allow2010YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2824.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
102
Examiner Affirmed
83
(81.4%)
Examiner Reversed
19
(18.6%)
Reversal Percentile
2.7%
Lower than average

What This Means

With a 18.6% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
309
Allowed After Appeal Filing
67
(21.7%)
Not Allowed After Appeal Filing
242
(78.3%)
Filing Benefit Percentile
9.2%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 21.7% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Art Unit 2824 - Prosecution Statistics Summary

Executive Summary

Art Unit 2824 is part of Group 2820 in Technology Center 2800. This art unit has examined 25,102 patent applications in our dataset, with an overall allowance rate of 93.1%. Applications typically reach final disposition in approximately 19 months.

Comparative Analysis

Art Unit 2824's allowance rate of 93.1% places it in the 92% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2824 receive an average of 0.94 office actions before reaching final disposition (in the 6% percentile). The median prosecution time is 19 months (in the 96% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.