USPTO Examiner DINH SON T - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18733187DETERMINING OFFSETS FOR MEMORY READ OPERATIONSJune 2024May 2025Allow1110NoNo
18670778MEMORY MODULES INCLUDING A MIRRORING CIRCUIT AND METHODS OF OPERATING THE SAMEMay 2024April 2025Allow1110NoNo
18662743DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPINGMay 2024May 2025Allow1210NoNo
18636901Selective and Dynamic Deployment of Error Correction Code Techniques in Integrated Circuit Memory DevicesApril 2024December 2024Allow800NoNo
18596753NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING A READ OPERATIONMarch 2024June 2025Allow1610NoNo
18418779STATIC RANDOM ACCESS MEMORY LAYOUTJanuary 2024March 2025Allow1410NoNo
18412635Flash memory controllerJanuary 2024November 2024Allow1010NoNo
18394660PERFORMING SELECTIVE COPYBACK IN MEMORY DEVICESDecember 2023December 2024Allow1110NoNo
18538722SEMICONDUCTOR STORAGE DEVICEDecember 2023January 2025Allow1310NoNo
18528935ACCELERATION OF MODEL/WEIGHT PROGRAMMING IN MEMRISTOR CROSSBAR ARRAYSDecember 2023January 2025Allow1310NoNo
18524477SEMICONDUCTOR MEMORY DEVICENovember 2023October 2024Allow1000NoNo
18518476Layout pattern for static random access memoryNovember 2023June 2025Allow1900NoNo
18510656DATA STORAGE DEVICE AND OPERATING METHOD THEREOFNovember 2023May 2025Allow1810NoNo
18509848DELAYED SELECT GATE RAMP-UP FOR PEAK READ CURRENT CONSUMPTION REDUCTION FOR NON-VOLATILE MEMORY APPARATUSNovember 2023June 2025Allow1900NoNo
18508311DETERMINING THE EFFECTS OF DIFFERENT ELECTRICAL CHARACTERISTICS OF A DRIVE-SENSE CIRCUIT ON A LOADNovember 2023January 2025Allow1410NoNo
18387780OPEN BLOCK-BASED READ OFFSET COMPENSATION IN READ OPERATION OF MEMORY DEVICENovember 2023November 2024Allow1210NoNo
18503644METHOD FOR CONTROLLING A MEMORY SYSTEM, A MEMORY SYSTEM, AND AN ELECTRONIC DEVICENovember 2023May 2025Allow1900NoNo
18386919MEMORY SUB-SYSTEM SANITIZATIONNovember 2023October 2024Allow1210NoNo
18380828MEMORY LOCATION MAPPING AND UNMAPPINGOctober 2023May 2025Allow1900NoNo
18486433SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIMEOctober 2023January 2025Allow1510NoNo
18482103SEMICONDUCTOR MEMORY DEVICEOctober 2023April 2025Allow1810NoNo
18374717OPERATING METHOD OF A NONVOLATILE MEMORY DEVICE FOR PROGRAMMING MULTI-PAGE DATASeptember 2023August 2024Allow1100NoNo
18478453EXTENDED MEMORY COMMUNICATIONSeptember 2023January 2025Allow1510NoNo
18375173SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAMESeptember 2023May 2025Allow1900NoNo
18476477SEMICONDUCTOR MEMORY DEVICESeptember 2023November 2024Allow1310NoNo
18474470BONDING QUALITY TEST METHOD, BONDING QUALITY TEST CIRCUIT, AND MEMORY DEVICE INCLUDING BONDING QUALITY TEST CIRCUITSeptember 2023May 2025Allow2000NoNo
18467005DATA PATH OSCILLATOR MISMATCH ERROR REDUCTION FOR NON-VOLATILE MEMORYSeptember 2023May 2025Allow2000NoNo
18241700MEMORY WITH PER DIE TEMPERATURE-COMPENSATED REFRESH CONTROLSeptember 2023February 2025Allow1710NoNo
18458891SEMICONDUCTOR MEMORY DEVICEAugust 2023June 2025Allow2200NoNo
18458071SEMICONDUCTOR STORAGE DEVICEAugust 2023April 2025Allow2000NoNo
18238908MEMORY SENSING WITH GLOBAL NON-REGULAR COUNTER AND/OR GLOBAL MULTIPLE REFERENCE VOLTAGESAugust 2023April 2025Allow1900NoNo
18238850ELIMINATING WRITE DISTURB FOR SYSTEM METADATA IN A MEMORY SUB-SYSTEMAugust 2023August 2024Allow1210NoNo
18238181METHOD OF CONTROLLING MEMORY, MEMORY AND MEMORY SYSTEMAugust 2023April 2025Allow1900NoNo
18454449PRE-CHARGE CONTROL CIRCUIT AND VOLTAGE GENERATION CIRCUIT INCLUDING THE SAMEAugust 2023June 2025Allow2100NoNo
18454144SETTING OPTIMAL THRESHOLD VOLTAGES FOR READING DATA FROM A MEMORY DEVICE BASED ON A CHANNEL DISTRIBUTIONAugust 2023April 2025Allow2000NoNo
18229748OPTIMIZED READ CURRENT CONSUMPTION BASED ON LOWER PAGE READ INFORMATION FOR NON-VOLATILE MEMORY APPARATUSAugust 2023April 2025Allow2100NoNo
18227581BINARY READ-BASED FAST ALGORITHM FOR OPTIMAL READ LEVEL ACQUISITIONJuly 2023March 2025Allow2000NoNo
18227505METHOD OF PROGRAMMING MULTI-PLANE MEMORY DEVICEJuly 2023March 2025Allow1910NoNo
18225574APPARATUSES AND METHODS FOR ORGANIZING DATA IN A MEMORY DEVICEJuly 2023November 2024Allow1510NoNo
18223994THREE-DIMENSIONAL VERTICAL NOR FLASH THIN-FILM TRANSISTOR STRINGSJuly 2023October 2024Allow1510NoNo
18352537NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEMJuly 2023November 2024Allow1710NoNo
18351179NON-VOLATILE MEMORY WITH OVERDRIVE VOLTAGE ZONING TO COMPENSATE FOR REDUCED MARGINSJuly 2023March 2025Allow2000NoNo
18219864ONE TIME PROGRAMMING MEMORY CELL WITH FIN FIELD-EFFECT TRANSISTOR USING PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGYJuly 2023March 2025Allow2000NoNo
18348570SEMICONDUCTOR MEMORY DEVICEJuly 2023July 2024Allow1200NoNo
18347517SEMICONDUCTOR DEVICEJuly 2023July 2024Allow1300NoNo
18217987MEMORY DEVICE AND ASYNCHRONOUS MULTI-PLANE INDEPENDENT READ OPERATION THEREOFJuly 2023May 2024Allow1110NoNo
18346335STAGE BASED FREQUENCY OPTIMIZATION FOR AREA REDUCTION OF CHARGE PUMPSJuly 2023March 2025Allow2000NoNo
18214080ESTABLISHING BITLINE, WORDLINE AND BOOST VOLTAGES TO MANAGE A MAXIMUM PROGRAM VOLTAGE LEVEL DURING ALL LEVELS PROGRAMMING OF A MEMORY DEVICEJune 2023February 2025Allow2000NoNo
18211476DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPINGJune 2023January 2024Allow700NoNo
18211495MEMORY DEVICE AND MULTI-PASS PROGRAM OPERATION THEREOFJune 2023May 2024Allow1110NoNo
18203693SEMICONDUCTOR MEMORY SYSTEMMay 2023May 2024Allow1110NoNo
18323838MULTI-LEVEL MEMRISTOR ELEMENTSMay 2023November 2024Allow1810NoNo
18201685MEMORY PROGRAMMING METHOD, MEMORY DEVICE, AND MEMORY SYSTEMMay 2023June 2025Allow2510NoNo
18197526CLOCK SIGNAL RETURN SCHEME FOR DATA READ IN PAGE BUFFER OF MEMORY DEVICEMay 2023August 2024Allow1510NoNo
18307603MEMORY DEVICE RELATED TO A VERIFY OPERATION AND METHOD OF OPERATING THE MEMORY DEVICEApril 2023May 2025Allow2510NoNo
18306552Real-Time Clock Module And Electronic DeviceApril 2023February 2025Allow2200NoNo
18138489PARTIAL BLOCK READ LEVEL VOLTAGE COMPENSATION TO DECREASE READ TRIGGER RATESApril 2023December 2024Allow1900NoNo
18304238SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME CAPABLE OF PREVENTING MALFUNCTION DURING READ OPERATIONApril 2023March 2025Allow2300NoNo
18304189MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICEApril 2023June 2025Allow2510NoNo
18135915CONDITIONAL VALLEY TRACKING DURING CORRECTIVE READSApril 2023November 2024Allow1900NoNo
18301275VOLTAGE CALIBRATION METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNITApril 2023February 2025Allow2200NoNo
18132489BOOST VOLTAGE MODULATED CORRECTIVE READApril 2023February 2025Allow2200NoNo
18296430NON-VOLATILE SEMICONDUCTOR STORAGE DEVICEApril 2023June 2024Allow1410NoNo
18130589AUTO-CALIBRATED CORRECTIVE READApril 2023January 2025Allow2200NoNo
18127980MEMORY DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF ELECTRONIC DEVICEMarch 2023May 2025Allow2510NoNo
18189580SEMICONDUCTOR DEVICEMarch 2023December 2024Allow2100NoNo
18189824IDENTIFY THE PROGRAMMING MODE OF MEMORY CELLS DURING READING OF THE MEMORY CELLSMarch 2023April 2024Allow1320NoNo
18188678SEMICONDUCTOR DEVICEMarch 2023May 2025Allow2600NoNo
18188332METHOD OF OPERATING SELECTOR DEVICE, METHOD OF OPERATING NONVOLATILE MEMORY APPARATUS USING THE SAME, ELECTRONIC CIRCUIT DEVICE INCLUDING SELECTOR DEVICE, AND NONVOLATILE MEMORY APPARATUSMarch 2023November 2024Allow2000NoNo
18186408MULTI-TIME PROGRAMMABLE NON-VOLATILE MEMORY CELL AND MEMORY WITH LOW POWER-COSTMarch 2023September 2024Allow1800NoNo
18186708IMPEDANCE CALIBRATION CIRCUIT, MEMORY CONTROLLER INCLUDING THE IMPEDANCE CALIBRATION CIRCUIT AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLERMarch 2023October 2024Allow1900NoNo
18177877MEMORY SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORYMarch 2023January 2025Allow2200NoNo
18177955BRIDGE CHIP, SEMICONDUCTOR STORAGE DEVICE, AND MEMORY SYSTEMMarch 2023October 2024Allow1900NoNo
18021442DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVERFebruary 2023September 2024Allow1900NoNo
18168847MEMORY WRITE ASSISTFebruary 2023November 2024Allow2100NoNo
18109338MEMORY MODULES INCLUDING A MIRRORING CIRCUIT AND METHODS OF OPERATING THE SAMEFebruary 2023February 2024Allow1210NoNo
18166484HYPERDIMENSIONAL COMPUTING DEVICEFebruary 2023February 2025Allow2410NoNo
18104228MEMORY CELL ARRAY WITH ROW DIRECTION GAP BETWEEN ERASE GATE LINES AND DUMMY FLOATING GATESJanuary 2023September 2024Allow1900NoNo
18095787TEMPERATURE-BASED MEMORY MANAGEMENTJanuary 2023August 2023Allow700NoNo
18151062MEMORY CONTROLLER AND METHOD FOR ADAPTIVELY PROGRAMMING FLASH MEMORYJanuary 2023June 2025Allow2910NoNo
18149505MEMORY DEVICEJanuary 2023December 2024Allow2310NoNo
18091303SEMICONDUCTOR MEMORY DEVICEDecember 2022August 2023Allow810NoNo
18090320SUPERCONDUCTING QUANTUM CIRCUITDecember 2022October 2024Allow2200NoNo
18146255MAGNETIC RANDOM ACCESS MEMORY STRUCTUREDecember 2022January 2025Allow2500NoNo
18069255MEMORY DEVICE AND METHOD FOR OPERATING THE SAMEDecember 2022March 2025Allow2710NoNo
18067224NON-VOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING THE SAME, AND READ METHOD THEREOFDecember 2022February 2025Allow2610NoNo
17985304BANK TO BANK DATA TRANSFERNovember 2022August 2024Allow2110NoNo
17968912OPERATING METHOD OF A NONVOLATILE MEMORY DEVICE FOR PROGRAMMING MULTI-PAGE DATAOctober 2022June 2023Allow810NoNo
17953219PREDICTING AND COMPENSATING FOR DEGRADATION OF MEMORY CELLSSeptember 2022July 2023Allow1010NoNo
17952828DATA STORAGE DEVICE AND OPERATING METHOD THEREOFSeptember 2022August 2023Allow1010NoNo
17895988TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRIOR READ OPERATIONSAugust 2022July 2024Allow2200NoNo
17895886READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANSAugust 2022June 2024Allow2200NoNo
17895803ADVANCED WINDOW PROGRAM-VERIFYAugust 2022April 2024Allow2000NoNo
17819826DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATIONAugust 2022May 2024Allow2100NoNo
17887348INDEPENDENT SENSING TIMESAugust 2022September 2024Allow2510NoNo
17818956COMPARISON CIRCUIT AND MEMORY CHIPAugust 2022June 2024Allow2200NoNo
17884107MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES USING SEGMENTATIONAugust 2022April 2024Allow2000NoNo
17882459SEMICONDUCTOR MEMORY DEVICEAugust 2022June 2024Allow2300NoNo
17816612APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAMEAugust 2022June 2023Allow1010NoNo
17878489SENSITIVE AMPLIFIER AND STORAGE DEVICEAugust 2022October 2022Allow200NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner DINH, SON T.

Strategic Value of Filing an Appeal

Total Appeal Filings
5
Allowed After Appeal Filing
3
(60.0%)
Not Allowed After Appeal Filing
2
(40.0%)
Filing Benefit Percentile
88.1%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 60.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner DINH, SON T - Prosecution Strategy Guide

Executive Summary

Examiner DINH, SON T works in Art Unit 2824 and has examined 1,790 patent applications in our dataset. With an allowance rate of 98.3%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 18 months.

Allowance Patterns

Examiner DINH, SON T's allowance rate of 98.3% places them in the 95% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by DINH, SON T receive 0.59 office actions before reaching final disposition. This places the examiner in the 5% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by DINH, SON T is 18 months. This places the examiner in the 94% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.7% benefit to allowance rate for applications examined by DINH, SON T. This interview benefit is in the 17% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 39.2% of applications are subsequently allowed. This success rate is in the 88% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 91.2% of cases where such amendments are filed. This entry rate is in the 98% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 12% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 91% percentile among all examiners. Of these withdrawals, 20.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 46.4% are granted (fully or in part). This grant rate is in the 53% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 3.6% of allowed cases (in the 85% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.3% of allowed cases (in the 47% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.