USPTO Examiner YANG HAN - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18743852PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAMEJune 2024February 2025Allow800NoNo
187389673D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLSJune 2024December 2024Allow610NoNo
18645018NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLSApril 2024April 2025Allow1210NoNo
18645184NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLSApril 2024December 2024Allow800NoNo
18644840NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLSApril 2024February 2025Allow1010NoNo
186054013D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLSMarch 2024May 2024Allow200NoNo
18581260SENSING SCHEME FOR A MEMORY WITH SHARED SENSE COMPONENTSFebruary 2024May 2025Allow1400NoNo
18443979Sub-Word Line Driver Placement For Memory DeviceFebruary 2024November 2024Allow900YesNo
18418880FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINSJanuary 2024February 2025Allow1310NoNo
184070963D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY-LINE PILLARSJanuary 2024March 2024Allow200NoNo
18541218MEMORY DEVICE, ELECTRONIC DEVICE, AND OPERATION METHOD OF MEMORY DEVICEDecember 2023June 2025Allow1800NoNo
18527978NAND DATA PLACEMENT SCHEMADecember 2023December 2024Allow1200NoNo
18518849MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOFNovember 2023February 2025Allow1500NoNo
18508903STORAGE DEVICES HAVING ENHANCED ERROR DETECTION AND MEMORY CELL REPAIRNovember 2023June 2025Allow1900NoNo
183843043D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARSOctober 2023December 2023Allow200NoNo
18489567SEMICONDUCTOR DEVICES FOR DETECTING DEFECTS IN ERROR CORRECTION CIRCUITS, AND METHODS OF PERFORMING TEST MODE OPERATIONSOctober 2023June 2025Allow2000NoNo
18482016MEMORY, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEMOctober 2023November 2024Allow1300NoNo
18376198APPARATUS FOR DETERMINING MEMORY CELL DATA STATESOctober 2023June 2024Allow800NoNo
18459930SEMICONDUCTOR MODULE FOR PERFORMING ERROR CORRECTION OPERATIONSeptember 2023April 2025Allow1900NoNo
18455904MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAMEAugust 2023August 2024Allow1200NoNo
18237816CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEMAugust 2023April 2025Allow2000NoNo
18453223INTEGRATED CIRCUIT DEVICEAugust 2023February 2025Allow1810YesNo
18233562MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE AND DIGITAL IN-MEMORY COMPUTATION PROCESSING MODEAugust 2023March 2025Allow1900NoNo
18447997FERROELECTRIC FIELD-EFFECT TRANSISTOR (FeFET) MEMORYAugust 2023May 2025Allow2120NoNo
18446513METHOD AND DEVICE FOR OBTAINING ROW HAMMER REFRESH ADDRESS, AND STORAGE MEDIUMAugust 2023April 2025Allow2000NoNo
18366191MEMORY DEVICE WITH CONTENT ADDRESSABLE MEMORY UNITSAugust 2023June 2024Allow1100NoNo
182312353D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARSAugust 2023October 2023Allow200NoNo
18264414DYNAMIC RANDOM ACCESS MEMORY REFRESH CIRCUIT AND REFRESH METHOD, AND PROOF-OF-WORK CHIPAugust 2023June 2025Allow2310NoNo
18362525MAGNETIC MEMORY DEVICEJuly 2023February 2024Allow700NoNo
18358463TEMPERATURE DEPENDENT REFRESH READ RATEJuly 2023March 2025Allow2000NoNo
18357412NON-VOLATILE MEMORY WITH ERASE DEPTH DETECTION AND ADAPTIVE ADJUSTMENT TO PROGRAMMINGJuly 2023May 2025Allow2100NoNo
18219418FERROELECTRIC MEMORY LOCAL SENSE AMPLIFICATIONJuly 2023April 2025Allow2100NoNo
18219401FERROELECTRIC MEMORY REFERENCE GENERATIONJuly 2023March 2025Allow2000NoNo
18340906Identifying unusable memory blocks based on zeros-ones imbalance in memory readoutsJune 2023March 2025Allow2100NoNo
18336428MEMORY DEVICEJune 2023August 2024Allow1400NoNo
18209051SYSTEM AND METHOD FOR TESTING MEMORY DEVICEJune 2023December 2024Allow1800NoNo
18331923REFRESH CIRCUIT AND MEMORYJune 2023February 2025Allow2000NoNo
18322894SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONSMay 2023February 2025Allow2000NoNo
18321576PAGE BUFFER, MEMORY DEVICE INCLUDING PAGE BUFFER AND MEMORY SYSTEMMay 2023February 2025Allow2100NoNo
18320667TEST CIRCUIT AND RECEIVING CIRCUIT HAVING TEST FUNCTIONMay 2023January 2025Allow2000NoNo
18317382SEMICONDUCTOR DEVICEMay 2023May 2025Allow2401NoNo
18313041MEMORY DEVICE AND MANUFACTURING METHODMay 2023August 2024Allow1610NoNo
18251699SPINTRONIC DEVICE, MEMORY CELL, MEMORY ARRAY AND READ AND WRITE CIRCUITMay 2023April 2025Allow2410NoNo
18310738APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLEMay 2023February 2024Allow1000NoNo
18310302APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLEMay 2023June 2024Allow1410NoNo
18306531MEMORY DEVICES INCLUDING PROCESSING-IN-MEMORY ARCHITECTURE CONFIGURED TO PROVIDE ACCUMULATION DISPATCHING AND HYBRID PARTITIONINGApril 2023February 2025Allow2200NoNo
18306762Sub-Word Line Driver Placement For Memory DeviceApril 2023November 2023Allow600NoNo
18133867NON-VOLATILE ANALOG RESISTIVE MEMORY CELLS IMPLEMENTING FERROELECTRIC SELECT TRANSISTORSApril 2023December 2023Allow800NoNo
18295148EFUSE STRUCTURE AND METHODApril 2023November 2023Allow700NoNo
18193645TEST METHOD FOR TESTING DECISION FEEDBACK EQUALIZATION OF MEMORY DEVICEMarch 2023October 2024Allow1800NoNo
18191039MEMORY DEVICE AND DEFENSE METHOD THEREOFMarch 2023October 2024Allow1900NoNo
18124334NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLSMarch 2023March 2024Allow1201NoNo
18245784DRIVING METHOD OF SEMICONDUCTOR DEVICEMarch 2023June 2025Allow2710NoNo
18121846CONCURRENT SLOW-FAST MEMORY CELL PROGRAMMINGMarch 2023September 2024Allow1800NoNo
18119997PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMORY DEVICEMarch 2023September 2024Allow1900NoNo
18180944MEMORY SYSTEMMarch 2023October 2023Allow800NoNo
18176507SEMICONDUCTOR MEMORY DEVICEMarch 2023September 2024Allow1900NoNo
18175511REDUCING PRECHARGE POWER CONSUMPTION IN A MEMORY ARRAYFebruary 2023January 2025Allow2310NoNo
18170548MEMORY DEVICE FOR PERFORMING READ OPERATION AND PROGRAM VERIFICATION OPERATIONFebruary 2023December 2024Allow2101NoNo
18111035LOCAL REFERENCE VOLTAGE GENERATOR FOR NON-VOLATILE MEMORYFebruary 2023January 2024Allow1100NoNo
18166476SENSE AMPLIFIER, METHOD FOR DRIVING SENSE AMPLIFIER, AND MEMORYFebruary 2023September 2024Allow1900NoNo
18163323ADDRESS SIGNAL TRANSMISSION CIRCUIT, ADDRESS SIGNAL TRANSMISSION METHOD AND STORAGE SYSTEMFebruary 2023October 2024Allow2110NoNo
18103500OXIDE SEMICONDUCTOR-BASED FRAMJanuary 2023June 2023Allow400NoNo
18103383NEURAL MEMORY ARRAY STORING SYNAPSIS WEIGHTS IN DIFFERENTIAL CELL PAIRSJanuary 2023October 2023Allow800NoNo
18158316APPARATUSES, SYSTEMS, AND METHODS FOR RESETTING ROW HAMMER DETECTOR CIRCUIT BASED ON SELF-REFRESH COMMANDJanuary 2023September 2023Allow800NoNo
18156654SEMICONDUCTOR MEMORY DEVICEJanuary 2023September 2023Allow810NoNo
18155676MEMORY CHIP TEST METHOD AND APPARATUS, MEDIUM, AND DEVICEJanuary 2023September 2024Allow2000NoNo
18097226SEMICONDUCTOR DEVICEJanuary 2023August 2024Allow1900NoNo
18095880MANAGING MEMORY LEAKAGES OF A SYSTEM FOR EVALUATING MANUFACTURED ITEMSJanuary 2023September 2024Allow2000NoNo
18151515SEMICONDUCTOR STRUCTURE AND CHIPJanuary 2023August 2024Allow1900NoNo
18094288MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOFJanuary 2023September 2023Allow800NoNo
18149729MEMORY DEVICE HAVING INTERFACE CHARGE TRAPSJanuary 2023April 2025Allow2711NoNo
18090409MEMORY DEVICE, METHOD FOR OPERATING MEMORY DEVICE, MEMORY SYSTEMDecember 2022October 2024Allow2210NoNo
18147537A MEMORY DEVICE, PROGRAMMING METHOD AND MEMORY SYSTEMDecember 2022August 2024Allow2000NoNo
18069685MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAMEDecember 2022May 2023Allow500NoNo
18068337STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICESDecember 2022April 2023Allow400NoNo
18076225QUICK RELIABILITY SCAN FOR MEMORY DEVICEDecember 2022October 2023Allow1010NoNo
18075027NAND DATA PLACEMENT SCHEMADecember 2022August 2023Allow910NoNo
18074101DEVICES, METHODS, AND SYSTEMS FOR A MULTILEVEL MEMORY CELLDecember 2022December 2024Allow2510NoNo
18061270MANGANESE OR SCANDIUM DOPED MULTI-ELEMENT NON-LINEAR POLAR MATERIAL GAIN MEMORY BIT-CELLDecember 2022June 2023Allow710NoNo
18072014NON-VOLATILE MEMORY AND VOLTAGE DETECTING CIRCUIT THEREOFNovember 2022July 2024Allow2000NoNo
18071054APPARATUS, MEMORY DEVICE, AND METHOD FOR STORING MULTIPLE PARAMETER CODES FOR OPERATION PARAMETERSNovember 2022February 2023Allow300NoNo
17988760MEMORY DEVICENovember 2022July 2024Allow2000NoNo
17988090ERASING MEMORYNovember 2022September 2024Allow2200NoNo
18053305CHARGE LEAKAGE DETECTION FOR MEMORY SYSTEM RELIABILITYNovember 2022April 2023Allow500NoNo
17980546SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICENovember 2022March 2025Allow2811NoNo
17977099SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICEOctober 2022August 2023Allow901NoNo
17974940METHODS OF OPERATING A NEAR MEMORY PROCESSING-DUAL IN-LINE MEMORY MODULE (NMP-DIMM) FOR PERFORMING A READ OPERATION AND AN ADAPTIVE LATENCY MODULE AND A SYSTEM THEREOFOctober 2022December 2024Allow2620YesNo
18048738SENSING SCHEME FOR A MEMORY WITH SHARED SENSE COMPONENTSOctober 2022October 2023Allow1210NoNo
18045520PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR MEMORY ELEMENTS FOR IN-MEMORY SERIAL PROCESSINGOctober 2022October 2024Allow2410NoNo
18045529CALIBRATION METHODS AND STRUCTURES FOR PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESISTOR MEMORY ELEMENTSOctober 2022July 2024Allow2200NoNo
17957532MEMORY DEVICE AND OPERATION METHOD THEREOFSeptember 2022May 2024Allow2000NoNo
17937120REFRESH CIRCUIT, MEMORY, AND REFRESH METHODSeptember 2022June 2024Allow2100NoNo
17955978MEMORY DEVICESeptember 2022June 2024Allow2100NoNo
17955439DATA CORRECTION OF REDUNDANT DATA STORAGESeptember 2022June 2024Allow2100NoNo
179482253D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH BIT-LINE PILLARSSeptember 2022July 2023Allow1011NoNo
17930625SEMICONDUCTOR MEMORY DEVICESeptember 2022April 2024Allow1900NoNo
17939756Detection of an Incorrectly Located Read VoltageSeptember 2022February 2024Allow1720NoNo
17903371Bipolar Read RetrySeptember 2022March 2023Allow700NoNo
17900352CONTROLLER AND SEMICONDUCTOR SYSTEM INCLUDING A CONTROLLERAugust 2022April 2023Allow700NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner YANG, HAN.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
1
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
10.2%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
5
Allowed After Appeal Filing
3
(60.0%)
Not Allowed After Appeal Filing
2
(40.0%)
Filing Benefit Percentile
88.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 60.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner YANG, HAN - Prosecution Strategy Guide

Executive Summary

Examiner YANG, HAN works in Art Unit 2824 and has examined 1,092 patent applications in our dataset. With an allowance rate of 96.7%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.

Allowance Patterns

Examiner YANG, HAN's allowance rate of 96.7% places them in the 90% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by YANG, HAN receive 0.77 office actions before reaching final disposition. This places the examiner in the 7% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by YANG, HAN is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +1.5% benefit to allowance rate for applications examined by YANG, HAN. This interview benefit is in the 17% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 43.2% of applications are subsequently allowed. This success rate is in the 94% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 51.9% of cases where such amendments are filed. This entry rate is in the 73% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 133.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 85% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 83.3% of appeals filed. This is in the 74% percentile among all examiners. Of these withdrawals, 40.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 48.7% are granted (fully or in part). This grant rate is in the 58% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 2.6% of allowed cases (in the 80% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.2% of allowed cases (in the 45% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.