USPTO Examiner LUU PHO M - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18797883INTEGRATED CIRCUIT DEVICEAugust 2024February 2026Allow1800NoNo
18789717Pulse Signal Generator System for a Magnetoresistive Random Access Memory ArrayJuly 2024January 2026Allow1700NoNo
18788496PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING A PAGE BUFFER CIRCUITJuly 2024February 2026Allow1900NoNo
18772714CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICEJuly 2024May 2025Allow1010NoNo
18767988SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATINGJuly 2024January 2026Allow1800NoNo
18758496ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICEJune 2024December 2025Allow1700NoNo
18758643REDUCTION IN CHIP AREA THROUGH DESIGN-TECHNOLOGY CO-OPTIMIZATIONJune 2024November 2025Allow1700NoNo
18754433MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOFJune 2024January 2026Allow1900NoNo
18754884MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMSJune 2024February 2026Allow2000NoNo
18750979HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCYJune 2024May 2025Allow1110NoNo
18746964SEMICONDUCTOR MEMORY AND NONVOLATILE MEMORYJune 2024December 2025Allow1700NoNo
18740981CURRENT AND VOLTAGE LIMIT CIRCUITRY FOR RESISTIVE RANDOM ACCESS MEMORY PROGRAMMINGJune 2024March 2025Allow910NoNo
18648219COARSE AND FINE PROGRAMMING OF NON-VOLATILE MEMORY CELLSApril 2024November 2025Allow1800NoNo
18646587TEMPERATURE EXCEPTION TRACKING IN A TEMPERATURE LOG FOR A MEMORY SYSTEMApril 2024March 2025Allow1110NoNo
18635631Bank-Shared Usage-Based Disturbance CircuitryApril 2024January 2026Allow2110YesNo
18633153AP-pinned Data Storage Layer and Laminated Topological Heusler Alloy SOT-MRAM Unit Cell for In-Memory Computing Artificial Intelligence Inference ChipApril 2024March 2026Allow2310NoNo
18625956NON-VOLATILE MEMORY AND OPERATING METHOD THEREOFApril 2024December 2024Allow810NoNo
18624399SELECT GATE BIAS GRADATION STRUCTURE IN NAND MEMORYApril 2024October 2025Allow1800NoNo
18615497SENSE AMPLIFIER CIRCUIT AND METHODMarch 2024March 2025Allow1210NoNo
18601832MEMORY DEVICEMarch 2024December 2025Allow2100NoNo
18594666MEMORY WITH ARTIFICIAL INTELLIGENCE MODEMarch 2024February 2025Allow1210NoNo
18585184Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAMFebruary 2024January 2025Allow1110NoNo
18583294MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAMEFebruary 2024January 2026Allow2310NoNo
18581131FPGA MEMORY WITH AUTO ADDRESS MODEFebruary 2024March 2026Allow2510NoNo
18443955POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTSFebruary 2024March 2026Allow2510NoNo
18441264SEMICONDUCTOR SYSTEM RELATED TO PERFORMING AN ERROR CHECK SCRUB OPERATIONFebruary 2024August 2025Allow1800NoNo
18436025MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEMFebruary 2024May 2025Allow1610NoNo
18423181MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT THRESHOLDS BASED ON BIT SIGNIFICANCEJanuary 2024December 2025Allow2310NoNo
18404710DUTY CYCLE CORRECTION CIRCUIT AND DUTY CYCLE CORRECTING METHODJanuary 2024November 2025Allow2310NoNo
18399867NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING A NONVOLATILE MEMORYDecember 2023September 2025Allow2000NoNo
18394849MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM)December 2023February 2026Allow2610NoNo
18573206METHOD FOR SWITCHING MAGNETIC MOMENTS IN MAGNETIC MATERIAL USING SEEDED SPIN-ORBIT TORQUEDecember 2023September 2025Allow2000NoNo
18389987APPARATUS AND METHODS FOR MANAGING SELECTOR DEVICE THRESHOLD VOLTAGE DRIFTDecember 2023February 2026Allow2610NoNo
18537357MEMORY DEVICE INTERFACE AND METHODDecember 2023November 2024Allow1110NoNo
18534818NON-VOLATILE MEMORY (NVM) CELL STRUCTURE TO INCREASE RELIABILITYDecember 2023March 2025Allow1510NoNo
18533165DELAY CONTROL CIRCUIT, DELAY CONTROL METHOD AND MEMORYDecember 2023October 2025Allow2310NoNo
18524668INTEGRATED CIRCUIT DIE WITH MEMORY MACRO INCLUDING THROUGH-SILICON VIA AND METHOD OF FORMING THE SAMENovember 2023January 2025Allow1410NoNo
18524526Systems and Methods to Perform Automatic Test Pattern Generation on Multiple Memory Units in ParallelNovember 2023October 2025Allow2310NoNo
18521891COUNTER-BASED SENSE AMPLIFIER METHOD FOR MEMORY CELLSNovember 2023May 2025Allow1810NoNo
18519248DYNAMIC READ CALIBRATIONNovember 2023June 2025Allow1800NoNo
18518426SYSTEM AND METHOD OF PERFORMING A READ OPERATIONNovember 2023November 2025Allow2410YesNo
18517970MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAMENovember 2023January 2026Allow2610NoNo
18515692MATCHING PATTERNS IN MEMORY ARRAYSNovember 2023December 2024Allow1310NoNo
18515273MAGNETORESISTIVE RANDOM ACCESS MEMORYNovember 2023October 2024Allow1110NoNo
18510857SENSE TIME SEPARATION IN FOGGY-FINE PROGRAM TO IMPROVE OPTIMAL VT WIDTHNovember 2023June 2025Allow1800NoNo
18561023TDC APPARATUS, DISTANCE MEASURING APPARATUS, AND DISTANCE MEASURING METHODNovember 2023October 2025Allow2300NoNo
18509188BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIPNovember 2023June 2025Allow1900NoNo
18560681METHOD FOR OPERATING THREE-DIMENSIONAL FLASH MEMORYNovember 2023September 2025Allow2210NoNo
18388680MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUTNovember 2023December 2024Allow1310NoNo
18504362APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATIONNovember 2023March 2026Allow2810NoNo
18386783READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRINGNovember 2023October 2025Allow2310NoNo
18386760READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRINGNovember 2023September 2025Allow2310NoNo
18492511MEMORY CELLS BASED ON SUPERCONDUCTING AND MAGNETIC MATERIALS AND METHODS OF THEIR CONTROL IN ARRAYSOctober 2023October 2024Allow1210NoNo
18481224SIGNAL RECEIVER, DATA RECEIVER AND DATA LATCH THEREOFOctober 2023January 2026Allow2710NoNo
18480762TRACKING SCHEME CIRCUIT OF MEMORY DEVICE AND METHODS FOR OPERATING THE SAMEOctober 2023February 2026Allow2810NoNo
18473086METHOD AND SYSTEM FOR REFRESH OF MEMORY DEVICESSeptember 2023February 2025Allow1610NoNo
18367677NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF TESTING NONVOLATILE MEMORY DEVICESeptember 2023December 2025Allow2710YesNo
18464350MAGNETIC MEMORYSeptember 2023May 2025Allow2000NoNo
18463525BLOCK DATA ENCRYPTION OF NON-VOLATILE MEMORY THROUGH SELECTIVE SELECT GATE ERASE THROUGH CHARGE COUPLED SCHEMESeptember 2023October 2025Allow2610NoNo
18238706TEMPERATURE SENSOR CIRCUITS FOR INTEGRATED CIRCUIT DEVICESAugust 2023August 2024Allow1210NoNo
18455575MEMORY SYSTEM HAVING A NON-VOLATILE MEMORY AND A CONTROLLER CONFIGURED TO SWITCH A MODE FOR CONTROLLING AN ACCESS OPERATION TO THE NON-VOLATILE MEMORYAugust 2023September 2025Allow2410NoNo
18235727TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORYAugust 2023May 2024Allow910NoNo
18448164STORAGE DEVICE AND METHOD OF OPERATING THE SAMEAugust 2023January 2026Allow2910NoNo
18232538SINGLE BLOCK MODE BLOCK HANDLING FOR SINGLE-SIDE GIDL ERASEAugust 2023April 2025Allow2000NoNo
18231338MULTIPLE CURRENT QUANTIZATION VALUES FOR PEAK POWER MANAGEMENTAugust 2023June 2025Allow2300NoNo
18230145SOLID-STATE DRIVE SECURE DATA WIPING FOR REUSE AND RECYCLINGAugust 2023August 2025Allow2510YesNo
18229182MEMORY CIRCUITAugust 2023June 2025Allow2310NoNo
18363251INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAMEAugust 2023December 2025Allow2810NoNo
18354211LOW POWER AND AREA OPTIMIZED TM4 AND TM5 COMPLIANT COMBINATION TMIO TRANSMITTER ARCHITECTUREJuly 2023December 2025Allow2910YesNo
18353607APPARATUSES AND METHODS FOR GENERATING CLOCK SIGNALSJuly 2023September 2025Allow2610NoNo
18352289METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICEJuly 2023August 2024Allow1310NoNo
18221330Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of OperatingJuly 2023July 2024Allow1310NoNo
18350145PHYSICALLY-DRIVEN GENERATION OF MANY-PORTED STORAGE ARRAYSJuly 2023September 2025Allow2610NoNo
18333661SEMICONDUCTOR DEVICEJune 2023May 2024Allow1110NoNo
18332753SEMICONDUCTOR MEMORY DEVICEJune 2023October 2025Allow2810NoNo
18256074A FIBRE OPTIC INTEGRATED QUANTUM MEMORY FOR LIGHTJune 2023February 2025Allow2000NoNo
18327343POWER AMPLIFIER CIRCUITJune 2023August 2025Allow2610YesNo
18321552METHOD AND SYSTEM TO BALANCE GROUND BOUNCEMay 2023May 2024Allow1210NoNo
18321511SEMICONDUCTOR MEMORY DEVICEMay 2023October 2025Allow2900NoNo
18319513MEMORY STRUCTURE AND METHOD FOR OPERATING THE SAMEMay 2023March 2025Allow2200NoNo
18315619TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE VOLTAGEMay 2023November 2025Allow3010YesNo
18312459MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICEMay 2023July 2025Allow2710YesNo
18141229BOOSTED DRIVER CIRCUITRY OF A LOW VOLTAGE SUPPLY MEMORY CONTROLLERApril 2023August 2025Allow2810NoNo
18306987SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR COMPENSATING SLEW RATE USING IMPEDANCE CALIBRATIONApril 2023March 2025Allow2310NoNo
18306073HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCYApril 2023March 2024Allow1110NoNo
18137388APPARATUS WITH ADJUSTABLE DIAGNOSTIC MECHANISM AND METHODS FOR OPERATING THE SAMEApril 2023April 2025Allow2410NoNo
18301440CONTENT ADDRESSABLE MEMORY ARRAY DEVICE STRUCTUREApril 2023February 2025Allow2200NoNo
18298779Stacked 3D Memory Architecture for Power OptimizationApril 2023May 2025Allow2500NoNo
18295855APPARATUS AND METHOD FOR PROGRAMMING AND VERIFYING DATA IN NON-VOLATILE MEMORY DEVICEApril 2023September 2025Allow3010NoNo
18030380NON-VOLATILE ELECTRO-OPTICAL HIGH-BANDWIDTH ULTRA-FAST LARGE-SCALE MEMORY ARCHITECTUREApril 2023October 2024Allow1900NoNo
18295276CANTILEVER NANOELECTROMECHANICAL DECODER CIRCUIT AND METHODS FOR FORMING THE SAMEApril 2023January 2025Allow2200NoNo
18247446SELF-REFERENCE STORAGE STRUCTURE AND IN-MEMORY COMPUTING CIRCUITMarch 2023August 2025Allow2910NoNo
18191858NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOFMarch 2023October 2025Allow3010NoNo
18188523Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAMMarch 2023November 2023Allow810NoNo
18184792SEMICONDUCTOR MEMORY DEVICEMarch 2023March 2025Allow2400NoNo
18119559MEMORY WITH ARTIFICIAL INTELLIGENCE MODEMarch 2023October 2023Allow810NoNo
18177026SEMICONDUCTOR MEMORYMarch 2023March 2025Allow2400NoNo
18169560SEMICONDUCTOR DEVICE INCLUDING REFERENCE CELLS AND A METHOD OF OPERATING THEREOFFebruary 2023August 2025Allow3010NoNo
18169151MEMORY DEVICE, OPERATION METHOD OF A MEMORY DEVICE, AND OPERATION METHOD OF A MEMORY CONTROLLERFebruary 2023June 2025Allow2810YesNo
18109744PROTECTING MEMORY CONTROLS AND ADDRESSFebruary 2023April 2025Allow2610YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LUU, PHO M.

Strategic Value of Filing an Appeal

Total Appeal Filings
2
Allowed After Appeal Filing
1
(50.0%)
Not Allowed After Appeal Filing
1
(50.0%)
Filing Benefit Percentile
80.3%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 50.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner LUU, PHO M - Prosecution Strategy Guide

Executive Summary

Examiner LUU, PHO M works in Art Unit 2824 and has examined 2,052 patent applications in our dataset. With an allowance rate of 97.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner LUU, PHO M's allowance rate of 97.5% places them in the 89% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by LUU, PHO M receive 0.85 office actions before reaching final disposition. This places the examiner in the 6% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by LUU, PHO M is 19 months. This places the examiner in the 95% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.7% benefit to allowance rate for applications examined by LUU, PHO M. This interview benefit is in the 18% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 43.1% of applications are subsequently allowed. This success rate is in the 94% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 87.9% of cases where such amendments are filed. This entry rate is in the 98% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 93% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 36.7% are granted (fully or in part). This grant rate is in the 25% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 7.8% of allowed cases (in the 91% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.2% of allowed cases (in the 52% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.