USPTO Examiner LUU PHO M - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18772714CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICEJuly 2024May 2025Allow1010NoNo
18750979HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCYJune 2024May 2025Allow1110NoNo
18740981CURRENT AND VOLTAGE LIMIT CIRCUITRY FOR RESISTIVE RANDOM ACCESS MEMORY PROGRAMMINGJune 2024March 2025Allow910NoNo
18646587TEMPERATURE EXCEPTION TRACKING IN A TEMPERATURE LOG FOR A MEMORY SYSTEMApril 2024March 2025Allow1110NoNo
18625956NON-VOLATILE MEMORY AND OPERATING METHOD THEREOFApril 2024December 2024Allow810NoNo
18615497SENSE AMPLIFIER CIRCUIT AND METHODMarch 2024March 2025Allow1210NoNo
18594666MEMORY WITH ARTIFICIAL INTELLIGENCE MODEMarch 2024February 2025Allow1210NoNo
18585184Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAMFebruary 2024January 2025Allow1110NoNo
18436025MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEMFebruary 2024May 2025Allow1610NoNo
18537357MEMORY DEVICE INTERFACE AND METHODDecember 2023November 2024Allow1110NoNo
18534818NON-VOLATILE MEMORY (NVM) CELL STRUCTURE TO INCREASE RELIABILITYDecember 2023March 2025Allow1510NoNo
18524668INTEGRATED CIRCUIT DIE WITH MEMORY MACRO INCLUDING THROUGH-SILICON VIA AND METHOD OF FORMING THE SAMENovember 2023January 2025Allow1410NoNo
18521891COUNTER-BASED SENSE AMPLIFIER METHOD FOR MEMORY CELLSNovember 2023May 2025Allow1810NoNo
18519248DYNAMIC READ CALIBRATIONNovember 2023June 2025Allow1800NoNo
18515692MATCHING PATTERNS IN MEMORY ARRAYSNovember 2023December 2024Allow1310NoNo
18515273MAGNETORESISTIVE RANDOM ACCESS MEMORYNovember 2023October 2024Allow1110NoNo
18510857SENSE TIME SEPARATION IN FOGGY-FINE PROGRAM TO IMPROVE OPTIMAL VT WIDTHNovember 2023June 2025Allow1800NoNo
18509188BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIPNovember 2023June 2025Allow1900NoNo
18388680MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUTNovember 2023December 2024Allow1310NoNo
18492511MEMORY CELLS BASED ON SUPERCONDUCTING AND MAGNETIC MATERIALS AND METHODS OF THEIR CONTROL IN ARRAYSOctober 2023October 2024Allow1210NoNo
18473086METHOD AND SYSTEM FOR REFRESH OF MEMORY DEVICESSeptember 2023February 2025Allow1610NoNo
18464350MAGNETIC MEMORYSeptember 2023May 2025Allow2000NoNo
18238706TEMPERATURE SENSOR CIRCUITS FOR INTEGRATED CIRCUIT DEVICESAugust 2023August 2024Allow1210NoNo
18235727TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORYAugust 2023May 2024Allow910NoNo
18232538SINGLE BLOCK MODE BLOCK HANDLING FOR SINGLE-SIDE GIDL ERASEAugust 2023April 2025Allow2000NoNo
18231338MULTIPLE CURRENT QUANTIZATION VALUES FOR PEAK POWER MANAGEMENTAugust 2023June 2025Allow2300NoNo
18229182MEMORY CIRCUITAugust 2023June 2025Allow2310NoNo
18352289METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICEJuly 2023August 2024Allow1310NoNo
18221330Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of OperatingJuly 2023July 2024Allow1310NoNo
18333661SEMICONDUCTOR DEVICEJune 2023May 2024Allow1110NoNo
18256074A FIBRE OPTIC INTEGRATED QUANTUM MEMORY FOR LIGHTJune 2023February 2025Allow2000NoNo
18321552METHOD AND SYSTEM TO BALANCE GROUND BOUNCEMay 2023May 2024Allow1210NoNo
18319513MEMORY STRUCTURE AND METHOD FOR OPERATING THE SAMEMay 2023March 2025Allow2200NoNo
18306987SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR COMPENSATING SLEW RATE USING IMPEDANCE CALIBRATIONApril 2023March 2025Allow2310NoNo
18306073HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCYApril 2023March 2024Allow1110NoNo
18137388APPARATUS WITH ADJUSTABLE DIAGNOSTIC MECHANISM AND METHODS FOR OPERATING THE SAMEApril 2023April 2025Allow2410NoNo
18301440CONTENT ADDRESSABLE MEMORY ARRAY DEVICE STRUCTUREApril 2023February 2025Allow2200NoNo
18030380NON-VOLATILE ELECTRO-OPTICAL HIGH-BANDWIDTH ULTRA-FAST LARGE-SCALE MEMORY ARCHITECTUREApril 2023October 2024Allow1900NoNo
18295276CANTILEVER NANOELECTROMECHANICAL DECODER CIRCUIT AND METHODS FOR FORMING THE SAMEApril 2023January 2025Allow2200NoNo
18188523Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAMMarch 2023November 2023Allow810NoNo
18184792SEMICONDUCTOR MEMORY DEVICEMarch 2023March 2025Allow2400NoNo
18119559MEMORY WITH ARTIFICIAL INTELLIGENCE MODEMarch 2023October 2023Allow810NoNo
18177026SEMICONDUCTOR MEMORYMarch 2023March 2025Allow2400NoNo
18109744PROTECTING MEMORY CONTROLS AND ADDRESSFebruary 2023April 2025Allow2610YesNo
18169151MEMORY DEVICE, OPERATION METHOD OF A MEMORY DEVICE, AND OPERATION METHOD OF A MEMORY CONTROLLERFebruary 2023June 2025Allow2810YesNo
18107914MEMORY SYSTEM RELATED TO CLOCK SYNCHRONIZATIONFebruary 2023February 2025Allow2510NoNo
18103876MANAGING WORKLOAD OF PROGRAMMING SETS OF PAGES TO MEMORY DEVICEJanuary 2023September 2023Allow710NoNo
18160597SEMICONDUCTOR DEVICES CAPABLE OF PERFORMING WRITE TRAINING WITHOUT READ TRAINING, AND MEMORY SYSTEM INCLUDING THE SAMEJanuary 2023June 2025Allow2910NoNo
18159882NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING IN A NONVOLATILE MEMORYJanuary 2023September 2023Allow810NoNo
18153475MEMORY MACRO INCLUDING THROUGH-SILICON VIAJanuary 2023August 2023Allow810NoNo
18152998INPUT SAMPLING SYSTEM AND METHOD, STORAGE MEDIUM, AND COMPUTER DEVICEJanuary 2023May 2025Allow2810NoNo
18150921RECEIVING CIRCUIT AND MEMORYJanuary 2023January 2025Allow2410NoNo
18091645DIGITAL VERIFY FAILBIT COUNT (VFC) CIRCUITDecember 2022February 2025Allow2610NoNo
18068637INFERENCE FOCUS FOR OFFLINE TRAINING OF SRAM INFERENCE ENGINE IN BINARY NEURAL NETWORKDecember 2022August 2023Allow810NoNo
18065098VOLTAGE CONTROLLED MAGNETIC ANISOTROPY (VCMA) MEMORY DEVICES INCLUDING PLATINUM CONTAINING LAYER IN CONTACT WITH FREE LAYERDecember 2022December 2024Allow2410NoNo
18064635NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING IN THE SAMEDecember 2022August 2023Allow910NoNo
18063516APPARATUS FOR EDGE TRIMMING OF SEMICONDUCTOR WAFERSDecember 2022July 2023Allow810NoNo
17994676LITHOGRAPHY FOR EDITABLE ATOMIC-SCALE DEVICES AND MEMORIESNovember 2022November 2023Allow1210NoNo
17990864Materials and Methods for Fabricating Superconducting Quantum Integrated CircuitsNovember 2022January 2024Allow1410NoNo
17984750COMPENSATION FOR CONDUCTANCE DRIFT IN ANALOG MEMORY IN CROSSBAR ARRAYNovember 2022December 2024Allow2520YesNo
18053271MEMORY SYSTEM AND MEMORY CONTROLLERNovember 2022August 2023Allow910NoNo
17973926TEMPERATURE SENSOR CIRCUITS FOR INTEGRATED CIRCUIT DEVICESOctober 2022August 2023Allow1010NoNo
17956492STORAGE RING QUANTUM COMPUTERSeptember 2022July 2023Allow1010NoNo
17952324SEMICONDUCTOR DEVICE AND STORAGE SYSTEMSeptember 2022June 2025Allow3310NoNo
17944135BUILT-IN SELF-TEST CIRCUITRYSeptember 2022January 2025Allow2810YesNo
17943706BUILT-IN SELF-TEST BURST PATTERNS BASED ON ARCHITECTURE OF MEMORYSeptember 2022January 2025Allow2810YesNo
17944162MEMORY CONTROL CIRCUIT AND REFRESH METHOD FOR DYNAMIC RANDOM ACCESS MEMORY ARRAYSeptember 2022September 2024Allow2410NoNo
17943763SWITCHING ELEMENT AND MEMORY DEVICESeptember 2022September 2024Allow2410NoNo
17940753METHOD FOR ACCESSING MEMORY CELLS, CORRESPONDING CIRCUIT AND DATA STORAGE DEVICESeptember 2022October 2024Allow2600NoNo
17940935Model Inversion in Integrated Circuit Devices having Analog Inference CapabilitySeptember 2022August 2024Allow2400NoNo
17939021STORAGE SYSTEM AND OPERATING METHOD OF STORAGE CONTROLLERSeptember 2022September 2024Allow2410YesNo
17930250NON VOLATILE STATIC RANDOM ACCESS MEMORY DEVICE AND CORRESPONDING CONTROL METHODSeptember 2022June 2023Allow910NoNo
17902130MANAGING DIGITALLY-CONTROLLED CHARGE PUMP OPERATION IN A MEMORY SUB-SYSTEMSeptember 2022November 2023Allow1510NoNo
17899293MEMORY SYSTEM AND READ METHODAugust 2022April 2024Allow1900NoNo
17897067VOLTAGE GENERATION CIRCUIT AND INTERFACE CIRCUITAugust 2022March 2025Allow3010NoNo
17885747Dynamic Way-Based Variable Pipeline Architecture for On-Chip MemoryAugust 2022November 2024Allow2710NoNo
17885709Burst Read with Flexible Burst Length for On-Chip MemoryAugust 2022May 2024Allow2110NoNo
17882156MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAMEAugust 2022August 2024Allow2410NoNo
17881187MEMORY DEVICEAugust 2022January 2025Allow2910YesNo
17881180MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEMAugust 2022December 2024Allow2810YesNo
17817348MEMORY SYSTEM, REFRESH CONTROL CIRCUIT, AND REFRESH CONTROL METHODAugust 2022August 2024Allow2410YesNo
17816809INTEGRATED CIRCUIT DEVICES INCLUDING A POWER DISTRIBUTION NETWORK AND METHODS OF FORMING THE SAMEAugust 2022September 2024Allow2510YesNo
17878034MEMORY CELLS BASED ON SUPERCONDUCTING AND MAGNETIC MATERIALS AND METHODS OF THEIR CONTROL IN ARRAYSJuly 2022November 2024Allow2710NoNo
17877452BISTABLE CIRCUIT AND ELECTRONIC CIRCUITJuly 2022August 2024Allow2410YesNo
17876346MEMORY CELL VOLTAGE LEVEL SELECTIONJuly 2022August 2024Allow2400NoNo
17873911COMMAND TRIGGERED POWER GATING FOR A MEMORY DEVICEJuly 2022November 2023Allow1610NoNo
17873730MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEMJuly 2022November 2023Allow1610NoNo
17868900SEMICONDUCTOR DEVICEJuly 2022October 2024Allow2710YesNo
17868241ONE TIME PROGRAMMABLE (OTP) MEMORY ARRAY AND READ AND WRITE METHOD THEREOFJuly 2022March 2024Allow2000NoNo
17812102APPARATUSES AND METHODS FOR ACCURATE BIAS TEMPERATURE INSTABILITY MITIGATIONJuly 2022June 2024Allow2310NoNo
17861627MEMORY DEVICE INTERFACE AND METHODJuly 2022August 2023Allow1410NoNo
17811037MEMORY DEVICES INCLUDING MULTIPLEXER DEVICES, AND RELATED ELECTRONIC SYSTEMSJuly 2022May 2023Allow1010NoNo
17858596FUNCTION SWITCHABLE MAGNETIC RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAMEJuly 2022February 2024Allow2000NoNo
17810018STRUCTURE INCLUDING A CROSS-BAR ROUTER AND METHODJune 2022March 2024Allow2110NoNo
17854068NON-VOLATILE MEMORY (NVM) CELL STRUCTURE TO INCREASE RELIABILITYJune 2022August 2023Allow1310NoNo
17850956MANAGING BIN PLACEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE BASED ON TRIGGER METRIC VALVESJune 2022July 2023Allow1310NoNo
17847528SEMICONDUCTOR STORAGE DEVICEJune 2022April 2023Allow1010NoNo
17846102SEMICONDUCTIVE MEMORY DEVICEJune 2022October 2024Abandon2810NoNo
17843241SRAM STRUCTURE AND METHODJune 2022April 2023Allow1010NoNo
17842989MEMORY DEVICE AND METHOD FOR OPERATING THE SAMEJune 2022October 2024Allow2810NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LUU, PHO M.

Strategic Value of Filing an Appeal

Total Appeal Filings
1
Allowed After Appeal Filing
1
(100.0%)
Not Allowed After Appeal Filing
0
(0.0%)
Filing Benefit Percentile
97.4%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 100.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner LUU, PHO M - Prosecution Strategy Guide

Executive Summary

Examiner LUU, PHO M works in Art Unit 2824 and has examined 2,080 patent applications in our dataset. With an allowance rate of 97.6%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner LUU, PHO M's allowance rate of 97.6% places them in the 93% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by LUU, PHO M receive 0.84 office actions before reaching final disposition. This places the examiner in the 8% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by LUU, PHO M is 19 months. This places the examiner in the 92% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.9% benefit to allowance rate for applications examined by LUU, PHO M. This interview benefit is in the 15% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 41.0% of applications are subsequently allowed. This success rate is in the 91% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 85.3% of cases where such amendments are filed. This entry rate is in the 97% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 91% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 34.5% are granted (fully or in part). This grant rate is in the 29% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 6.3% of allowed cases (in the 92% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.2% of allowed cases (in the 45% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.