USPTO Examiner LEBOEUF JEROME LARRY - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18669140MULTI-STATE PROGRAMMING OF MEMORY CELLSMay 2024April 2025Allow1110NoNo
18653418Multi-Bit Storage Device Using Phase Change MaterialMay 2024December 2024Allow700NoNo
18430136PROCESSING IN MEMORYFebruary 2024May 2025Allow1510NoNo
18420073MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETSJanuary 2024August 2024Allow700NoNo
18413107RESISTIVE MEMORY DEVICES USING A CARBON-BASED CONDUCTOR LINE AND METHODS FOR FORMING THE SAMEJanuary 2024May 2025Allow1610NoNo
18517320CROSSBAR CIRCUITS FOR PERFORMING CONVOLUTION OPERATIONSNovember 2023June 2025Allow1900NoNo
18515649Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth MemoriesNovember 2023August 2024Allow900NoNo
18479836MEMORY DEVICES WITH SELECTOR LAYER AND METHODS OF FORMING THE SAMEOctober 2023October 2024Allow1210NoNo
18375869MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATESOctober 2023January 2025Allow1620NoNo
18478776SEMICONDUCTOR DEVICE INCLUDING CHALCOGEN COMPOUND AND SEMICONDUCTOR APPARATUS INCLUDING THE SAMESeptember 2023May 2024Allow800NoNo
18373741DATA INTEGRITY CHECKS BASED ON VOLTAGE DISTRIBUTION METRICSSeptember 2023February 2025Allow1720YesNo
18467094MEMORY DEVICE DETERMINING TARGET RESISTANCE STATESSeptember 2023May 2025Allow2000NoNo
18447232SEMICONDUCTOR DEVICES WITH A DOUBLE SIDED WORD LINE STRUCTUREAugust 2023March 2025Allow1910NoNo
18230450CHARGE PUMP SYSTEM WITH LOW RIPPLE OUTPUT VOLTAGEAugust 2023September 2024Allow1410NoNo
18362289SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SENSE AMPLIFIERSJuly 2023July 2024Allow1110NoNo
18333392STATIC RANDOM ACCESS MEMORY WITH A SUPPLEMENTARY DRIVER CIRCUIT AND METHOD OF CONTROLLING THE SAMEJune 2023August 2024Allow1410YesNo
18331746APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONSJune 2023July 2024Allow1310NoNo
18205417METHOD OF RRAM WRITE RAMPING VOLTAGE IN INTERVALSJune 2023February 2025Allow2030YesNo
18321898PHASE CHANGE MATERIAL SWITCH CIRCUIT FOR ENHANCED SIGNAL ISOLATION AND METHODS OF FORMING THE SAMEMay 2023June 2025Allow2510NoNo
18317123PHASE CHANGE MEMORY CELL WITH AN AIRGAP TO ALLOW FOR THE EXPANSION AND RESTRICTION OF THE PCM MATERIALMay 2023February 2024Allow900NoNo
18317680ELECTRONIC DEVICE WITH VARIABLE RESISTANCE LAYERS AND INSULATING LAYERS ALTERNATELY STACKED AND METHOD OF MANUFACTURING THE SAMEMay 2023April 2024Allow1110NoNo
18247213MEMORY CIRCUIT STRUCTURE AND METHOD OF OPERATING MEMORY CIRCUIT STRUCTUREMarch 2023February 2025Allow2300NoNo
18188475MEMORY DEVICE AND MEMORY SYSTEM FOR USING READ COMPENSATION SCHEME AND OPERATING METHOD OF THE SAMEMarch 2023May 2025Allow2610NoNo
18188729PHASE CHANGE MATERIAL INCLUDING DEUTERIUMMarch 2023June 2025Allow2710YesNo
18124576SEMICONDUCTOR DIE HAVING ON-DIE POWER SWITCH FOR SELECTING TARGET OPERATION VOLTAGE FROM OPERATION VOLTAGES PROVIDED BY DIFFERENT POWER SOURCESMarch 2023May 2025Allow2610NoNo
18182382LOW POWER MEMORY DEVICE WITH COLUMN AND ROW LINE SWITCHES FOR SPECIFIC MEMORY CELLSMarch 2023September 2024Abandon1811NoNo
18181851CHIP BONDED SEMICONDUCTOR MEMORY DEVICE WITH DIFFERENT CHARGE STORAGE FILMSMarch 2023April 2025Allow2501NoNo
18025009SEMICONDUCTOR DEVICE WITH FIRST AND SECOND ELEMENTS AND ELECTRONIC DEVICEMarch 2023April 2025Allow2610NoNo
18117108FERROELECTRIC-BASED SYNAPTIC DEVICE AND METHOD OF OPERATING THE SYNAPTIC DEVICE, AND 3D SYNAPTIC DEVICE STACK USING THE SYNAPTIC DEVICESMarch 2023December 2024Allow2110NoNo
18167819SIGNAL CONTROL CIRCUIT, SIGNAL CONTROL METHOD FOR BLOCKING ACTIVATION OPERATIONS AND SEMICONDUCTOR MEMORYFebruary 2023February 2025Allow2410NoNo
18164657IN-DYNAMIC MEMORY SEARCH DEVICE AND OPERATION METHOD THEREOFFebruary 2023September 2024Allow1900NoNo
18105935PHASE-CHANGE MATERIAL-BASED XOR LOGIC GATESFebruary 2023May 2024Allow1510NoNo
18161915TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORSJanuary 2023October 2024Allow2120YesNo
18100615SEMICONDUCTOR MEMORY DEVICE WITH A PLURALITY OF SENSE AMPILIFERS OVERLAPPING A PLURALITY OF METAL JOINTSJanuary 2023September 2023Allow810NoNo
18092115METHOD FOR LOCATING BOUNDARY PAGE LINE IN MEMORY DEVICE, MEMORY DEVICE, AND MEMORY SYSTEM THEREOFDecember 2022January 2025Allow2410YesNo
18081265SEMICONDUCTOR STORAGE DEVICEDecember 2022July 2024Allow1900NoNo
18077572SEMICONDUCTOR MEMORY DEVICE WITH VOLTAGES APPLIED TO GLOBAL DRAIN SELECT LINES AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICEDecember 2022December 2024Allow2401NoNo
18076060VOLTAGE SUPPLY CIRCUIT WITH A VOLTAGE REGULATORDecember 2022November 2024Allow2401NoNo
18059124MEMORY DEVICE AND TEST METHOD OF MEMORY DEVICENovember 2022December 2024Allow2401NoNo
18055588APPARATUSES AND METHODS FOR INPUT BUFFER DATA FEEDBACK EQUALIZATION CIRCUITSNovember 2022January 2025Allow2610NoNo
17986628MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE FOR CONTROLLING A CHANNEL VOLTAGENovember 2022March 2025Allow2820NoNo
17978144MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETSOctober 2022October 2023Allow1210NoNo
17968082VERTICAL MEMORY DEVICE WITH A DOUBLE WORD LINE STRUCTUREOctober 2022June 2024Allow2020NoNo
18045881SRAM WITH RECONFIGURABLE SETTINGOctober 2022March 2025Allow2920NoNo
17955670SIGNAL DETECTION SYSTEM FOR DUTY CYCLE TESTING AND MEMORY DETECTION METHODSeptember 2022November 2024Allow2610NoNo
17934965MEMORY CIRCUIT, SYSTEM AND METHOD FOR RAPID RETRIEVAL OF DATA SETSSeptember 2022November 2023Allow1310NoNo
17899974SEMICONDUCTOR MEMORY DEVICEAugust 2022July 2024Allow2300YesNo
17900228SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD FOR THE SAMEAugust 2022May 2024Allow2000NoNo
17899898VARIABLE RESISTANCE NON-VOLATILE MEMORY WITH A GATE INSULATOR FILM AT A SAME HEIGHT AS A VOLTAGE APPLICATION ELECTRODEAugust 2022September 2024Allow2501NoNo
17899951SEMICONDUCTOR STORAGE DEVICE ACQUIRING VOLTAGE FROM DUMMY PILLARSAugust 2022September 2024Allow2501NoNo
17895433Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth MemoriesAugust 2022June 2023Allow1000NoNo
17888781TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICEAugust 2022October 2024Allow2610NoNo
17885431Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural NetworkAugust 2022June 2023Allow1010NoNo
17885437COMPENSATION FOR REFERENCE TRANSISTORS AND MEMORY CELLS IN ANALOG NEURO MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORKAugust 2022August 2023Allow1210NoNo
17881009MEMORY DEVICE AND METHOD FOR DETERMINING START POINT AND END POINT OF VERIFICATION OPERATION OF TARGET STATE DURING PROGRAMMINGAugust 2022September 2024Allow2510YesNo
17877714MEMORY DEVICE WITH MEMORY STRINGS USING VARIABLE RESISTANCE MEMORY REGIONSJuly 2022April 2025Allow3221NoNo
17875449METHOD AND CIRCUIT FOR ADAPTIVE COLUMN-SELECT LINE SIGNAL GENERATIONJuly 2022February 2024Allow1900NoNo
17874611Buried Metal TechniquesJuly 2022June 2025Allow3541YesNo
17813802Generating Self-Aligned Heater for PCRAM Using FilamentsJuly 2022October 2023Allow1510NoNo
17864970MULTI-LAYERED MAGNETIC RANDOM ACCESS MEMORY AND ELECTRONIC DEVICEJuly 2022September 2024Allow2620NoNo
17865381LOW_POWERED MEMORY DEVICE AND METHOD OF CONTROLLING POWER OF THE SAMEJuly 2022April 2025Abandon3320NoNo
17810688Multi-Bit Storage Device Using Phase Change MaterialJuly 2022January 2024Allow1901NoNo
17834074PROCESSING APPARATUSES INCLUDING MAGNETIC RESISTORSJune 2022January 2024Allow1900NoNo
17826733MEMORY DEVICE WITH DYNAMIC PROGRAM-VERIFY VOLTAGE CALIBRATIONMay 2022October 2023Allow1720YesNo
17750484RESISTIVE MEMORY DEVICES USING A CARBON-BASED CONDUCTOR LINE AND METHODS FOR FORMING THE SAMEMay 2022October 2023Allow1710NoNo
17751417ELECTRONIC DEVICE WITH VARIABLE RESISTANCE LAYERS AND INSULATING LAYERS ALTERNATELY STACKED AND METHOD OF MANUFACTURING THE SAMEMay 2022September 2023Abandon1610NoNo
17664550THREE DIMENSIONAL MEMORY DEVICE CONTAINING RESONANT TUNNELING BARRIER AND HIGH MOBILITY CHANNEL AND METHOD OF MAKING THEREOFMay 2022November 2024Allow3010NoNo
17749364SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEMMay 2022November 2024Allow3010NoNo
17747183FLASH MEMORY DEVICES INCLUDING DRAMMay 2022July 2024Allow2621YesNo
17747998NON-VOLATILE STATIC RANDOM ACCESS MEMORY INCORPORATING RESISTIVE RANDOM-ACCESS MEMORYMay 2022March 2024Allow2210NoNo
17747335SEMICONDUCTOR DEVICE DELAYING MODE CONTROL SIGNALSMay 2022January 2024Allow2000NoNo
17737032MEMORY DEVICES WITH SELECTOR LAYER AND METHODS OF FORMING THE SAMEMay 2022June 2023Allow1410YesNo
17737207CHARGE PUMP SYSTEM WITH LOW RIPPLE OUTPUT VOLTAGEMay 2022June 2023Allow1310NoNo
17733474WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGNApril 2022June 2024Allow2611NoNo
17660640STACKED FET SRAMApril 2022December 2023Allow2000NoNo
17657777METHOD OF FORMING PHASE-CHANGE MEMORY LAYERS ON RECESSED ELECTRODESApril 2022February 2023Allow1100NoNo
17694184PROCESSING IN MEMORY IMPLEMENTING VLIW CONTROLLERMarch 2022September 2023Allow1810YesNo
17690332LOW POWER MODE WITH READ SEQUENCE ADJUSTMENTMarch 2022April 2024Allow2610YesNo
17682297MEMORY DEVICE WITH INCREASED ELECTRODE RESISTANCE TO REDUCE TRANSIENT SELECTION CURRENTFebruary 2022April 2023Allow1410NoNo
17682968SEMICONDUCTOR STORAGE DEVICE AND DATA ERASING METHODFebruary 2022November 2023Allow2000NoNo
17673137THREE DIMENSIONAL MEMORY DEVICE CONTAINING RESONANT TUNNELING BARRIER AND HIGH MOBILITY CHANNEL AND METHOD OF MAKING THEREOFFebruary 2022January 2025Allow3511NoNo
17671288DUAL PORT MEMORY CELL WITH MULTIPLE METAL LAYERSFebruary 2022July 2024Allow2911NoNo
17579364MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATESJanuary 2022June 2023Allow1720NoNo
17627160CMOS-COMPATIBLE PROTONIC RESISTIVE DEVICESJanuary 2022June 2022Allow500NoNo
17575399SYSTEMS AND METHODS TO MANAGE MEMORY DURING POWER DOWN AND STORAGEJanuary 2022October 2024Allow3320NoNo
17561278ADJUSTING PROGRAM EFFECTIVE TIME USING PROGRAM STEP CHARACTERISTICSDecember 2021September 2023Allow2130YesNo
17552225SEMICONDUCTOR MEMORY DEVICEDecember 2021November 2023Allow2300NoNo
17549162MEMORY COMPRISING A MATRIX OF RESISTIVE MEMORY CELLS, AND ASSOCIATED METHOD OF INTERFACINGDecember 2021April 2024Allow2810NoNo
17541240STATIC RANDOM ACCESS MEMORY WITH A SUPPLEMENTARY DRIVER CIRCUIT AND METHOD OF CONTROLLING THE SAMEDecember 2021January 2023Allow1410NoNo
17537937MAGNETIC MEMORY DEVICE WITH A PLURALITY OF CAPPING LAYERSNovember 2021June 2024Allow3020YesNo
17536386METHOD OF RRAM WRITE RAMPING VOLTAGE IN INTERVALSNovember 2021January 2023Allow1410YesNo
17526121MULTI-STATE PROGRAMMING OF MEMORY CELLSNovember 2021January 2024Allow2610NoNo
17526646MRAM STRUCTURE WITH ENHANCED MAGNETICS USING SEED ENGINEERINGNovember 2021January 2024Allow2601NoNo
17450691TUNING PERPENDICULAR MAGNETIC ANISOTROPY OF HEUSLER COMPOUND IN MRAM DEVICESOctober 2021March 2025Allow4110YesNo
17441667TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICESSeptember 2021February 2024Allow2810NoNo
17470003WRAP-AROUND PROJECTION LINER FOR AI DEVICESeptember 2021April 2024Allow3120NoNo
17462302SEMICONDUCTOR STORAGE DEVICEAugust 2021February 2024Abandon2910NoNo
17460504CONDUCTIVE-BRIDGING SEMICONDUCTOR MEMORY DEVICE FORMED BY SELECTIVE DEPOSITIONAugust 2021November 2023Allow2610NoNo
17310859ANTI-FUSE UNIT STRUCTURE AND ANTI-FUSE ARRAYAugust 2021January 2025Allow4120NoNo
17412157PHASE CHANGE MEMORY WITH HEATERAugust 2021December 2023Allow2711NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LEBOEUF, JEROME LARRY.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
3
Examiner Affirmed
2
(66.7%)
Examiner Reversed
1
(33.3%)
Reversal Percentile
52.0%
Higher than average

What This Means

With a 33.3% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
12
Allowed After Appeal Filing
1
(8.3%)
Not Allowed After Appeal Filing
11
(91.7%)
Filing Benefit Percentile
10.3%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 8.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner LEBOEUF, JEROME LARRY - Prosecution Strategy Guide

Executive Summary

Examiner LEBOEUF, JEROME LARRY works in Art Unit 2824 and has examined 524 patent applications in our dataset. With an allowance rate of 86.1%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 22 months.

Allowance Patterns

Examiner LEBOEUF, JEROME LARRY's allowance rate of 86.1% places them in the 58% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by LEBOEUF, JEROME LARRY receive 1.69 office actions before reaching final disposition. This places the examiner in the 48% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by LEBOEUF, JEROME LARRY is 22 months. This places the examiner in the 81% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +6.8% benefit to allowance rate for applications examined by LEBOEUF, JEROME LARRY. This interview benefit is in the 35% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 31.2% of applications are subsequently allowed. This success rate is in the 55% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 39.8% of cases where such amendments are filed. This entry rate is in the 53% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 44.4% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 38% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 70.0% of appeals filed. This is in the 51% percentile among all examiners. Of these withdrawals, 42.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 37.0% are granted (fully or in part). This grant rate is in the 33% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.6% of allowed cases (in the 61% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.8% of allowed cases (in the 63% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.