USPTO Group 2820 Prosecution Statistics

Group Information

Group: 2820
Tech Center: 2800
Total Cases: 85,958
Last Active: July 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19261799SYSTEMS AND METHODS FOR IMPLEMENTING A FEEDBACK-INFORMED MEMORY PROGRAMMING OF AN INTEGRATED CIRCUITJuly 2025September 2025Allow200YesNo
192453493D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATHJune 2025March 2026Allow900NoNo
19239787CONTINUOUS-WAVE PEROVSKITE POLARITON LASER DEVICE AND A LASER CHIPJune 2025December 2025Allow610NoNo
19209685METHOD AND DEVICE FOR AUTOMATICALLY LOCKING REPETITION FREQUENCY AND CARRIER-ENVELOP OFFSET FREQUENCY OF OPTICAL FREQUENCY COMBMay 2025August 2025Allow300NoNo
19063845EXTERNAL CAVITY LASER WITH MULTIPLE MATERIALS MICRO-RING REFLECTORSFebruary 2025October 2025Allow711YesNo
19057911SEMICONDUCTOR WAVEGUIDE OPTICAL GAIN DEVICE WITH LATERAL CURRENT CONFINEMENT AND OPTICAL MODE SHAPINGFebruary 2025June 2025Allow400NoNo
19057892SEMICONDUCTOR WAVEGUIDE OPTICAL GAIN DEVICE WITH OPTICAL MODE SHAPINGFebruary 2025May 2025Allow300NoNo
19056941SEMICONDUCTOR WAVEGUIDE OPTICAL GAIN DEVICE WITH OPTICAL MODE SHAPINGFebruary 2025April 2025Allow200NoNo
19039289GASEOUS LASER SYSTEMS WITH EDGE-DEFINING ELEMENT AND RELATED TECHNIQUESJanuary 2025October 2025Allow920NoNo
19019732METHOD FOR OPERATING A DYNAMIC MEMORY STRUCTURE HAVING A WRITE GATING DEVICE, A READ GATING DEVICE, AND A CAPACITORJanuary 2025June 2025Allow510YesNo
19007848VERTICAL CAVITY SURFACE EMITTING LASER STRUCTURE AND MANUFACTURING METHOD THEREOFJanuary 2025March 2025Allow200NoNo
189916313D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYDecember 2024June 2025Allow500NoNo
18984180VERTICALLY INTEGRATED ELECTRO-ABSORPTION MODULATED LASERS AND METHODS OF FABRICATIONDecember 2024August 2025Allow810NoNo
18975798BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAMEDecember 2024November 2025Allow1100YesNo
18973149BROADBAND LASER SYSTEM ENHANCED IN LATER PART OF MID INFRARED SPECTRUMDecember 2024February 2025Allow200NoNo
18971777TWO-DIMENSIONAL PHOTONIC CRYSTAL SURFACE EMITTING LASERDecember 2024September 2025Allow910NoNo
18957531SEMICONDUCTOR WAVEGUIDE OPTICAL GAIN DEVICE WITH LATERAL CURRENT CONFINEMENTNovember 2024May 2025Allow511NoNo
18866832SELF-SEEDING A BIDIRECTIONAL MODE-LOCKED LASERNovember 2024March 2025Allow400NoNo
18941312SYSTEM AND TECHNIQUES FOR DIODE LASER WAVELENGTH SPECTRUM NARROWINGNovember 2024July 2025Allow811NoNo
18926560LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEMOctober 2024December 2024Allow110NoNo
18920010WAVE SHAPING CIRCUIT FOR LASER DRIVING CIRCUIT, LASER DRIVING CIRCUIT AND LASER DEVICEOctober 2024April 2025Allow600NoNo
17766568NON-VOLATILE STORAGE CIRCUITOctober 2024July 2024Allow2820NoNo
18911618DEVICE FOR RECEIVING SINGLE-ENDED SIGNAL OF LIGHT EMITTING DIODE CONTROL CARD AND FORWARDING AS DIFFERENTIAL SIGNALSOctober 2024December 2024Allow200NoNo
18888087NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH MULTI-WAY SHARING OF GAIN ELEMENT WITH SERIES TRANSISTORSeptember 2024March 2026Allow1800NoNo
18884137HIGH-POWER LARGE-APERTURE FUNDAMENTAL MODE VORTEX OPTICAL WAVEGUIDE COHERENT VCSEL ARRAYSeptember 2024February 2025Allow500NoNo
18829968MAGNETIC MEMORYSeptember 2024March 2026Allow1800NoNo
18845799METHODS AND APPARATUS FOR GENERATING COHERENT LIGHT AT NEW FREQUENCIES VIA TIME VARYING LASINGSeptember 2024April 2025Allow701NoNo
18826515MEMORY SYSTEMS, OPERATING METHODS FOR MEMORY SYSTEMS, CONTROLLER AND STORAGE MEDIUMSeptember 2024March 2026Allow1800NoNo
18825487ADDRESS PATH ROUTING REDUCTION STRATEGY FOR NONVOLATILE MEMORY DECODERSSeptember 2024March 2026Allow1800NoNo
18824515APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKINGSeptember 2024March 2026Allow1800NoNo
18823046ELECTRONIC DEVICE WITH BUFFERED OPERATION ENGINE AND METHOD FOR PERFORMING CALCULATION USING SAMESeptember 2024February 2025Allow510YesNo
18822985BITLINE SENSE AMPLIFIERS AND SEMICONDUCTOR DEVICES INCLUDING THE SAMESeptember 2024March 2026Allow1800NoNo
18820305DATA BUFFER CIRCUIT STRUCTURE, LAYOUT STRUCTURE OF MULTIPLE DATA BUFFER CIRCUITS, AND MEMORYAugust 2024February 2026Allow1700NoNo
18820449REFERENCE VOLTAGE CALIBRATION APPARATUS IN MEMORY INTERFACEAugust 2024March 2026Allow1800NoNo
18821402SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND CONTROL METHODAugust 2024March 2026Allow1800NoNo
18821016SEMICONDUCTOR DEVICEAugust 2024February 2026Allow1800NoNo
18818913MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAMEAugust 2024March 2026Allow1800NoNo
18819770MEMORY DEVICEAugust 2024February 2026Allow1800NoNo
18818260SCHEDULING SCAN OPERATIONS IN MEMORY SUB-SYSTEMSAugust 2024March 2026Allow1900NoNo
18818078HANDLING POWER-LOSS RESET EVENTS WITH BAD BLOCK RISK MITIGATIONAugust 2024March 2026Allow1800NoNo
18818256CONTROLLING SOLITON SELF-FREQUENCY SHIFTAugust 2024January 2025Allow501NoNo
18816949METHODS OF OPERATING MEMORIES, MEMORIES AND MEMORY SYSTEMSAugust 2024February 2026Allow1800NoNo
18816921MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMS, AND ELECTRONIC DEVICESAugust 2024March 2026Allow1800NoNo
18815547METHOD OF OPERATING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICEAugust 2024March 2026Allow1900NoNo
18814679SEMICONDUCTOR MEMORY DEVICEAugust 2024February 2026Allow1800NoNo
18815802MEMORY DEVICE AND INTERNAL VOLTAGE MEASURING METHOD THEREOFAugust 2024March 2026Allow1800NoNo
18810552SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAMPLING CIRCUITAugust 2024February 2026Allow1800NoNo
18809407Gain Optical Fiber with Double-clad Fluoride and Its Preparation MethodAugust 2024October 2024Allow200NoNo
18807590MEMORY DEVICE, MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD THEREOFAugust 2024February 2026Allow1800NoNo
18806082LOW DROPOUT REGULATORSAugust 2024February 2026Allow1800NoNo
18806359APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR CLOCK SWITCHING AND LOW POWER CONSUMPTIONAugust 2024February 2026Allow1800NoNo
18804524CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE, OPERATION METHOD OF CONTROLLER, AND STORAGE DEVICE INCLUDING MEMORY DEVICE AND CONTROLLERAugust 2024February 2026Allow1800NoNo
18803450SEMICONDUCTOR LASER COMPONENTSAugust 2024November 2025Allow1520NoNo
18837881CMOS SRAM CELL HAVING TRENCH STRUCTUREAugust 2024January 2025Allow500NoNo
18801328READING VOLTAGE MANAGEMENT METHOD AND STORAGE DEVICEAugust 2024February 2026Allow1800NoNo
18800495EFFICIENT LASER SYSTEMAugust 2024March 2025Allow710NoNo
18799934NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICEAugust 2024February 2026Allow1800NoNo
18799404METHOD FOR PRODUCING OPTOELECTRONIC DEVICESAugust 2024March 2026Allow1920YesNo
18797883INTEGRATED CIRCUIT DEVICEAugust 2024February 2026Allow1800NoNo
18798572OPERATION METHOD FOR THREE-DIMENSIONAL FLASH MEMORY INCLUDING FERROELECTRIC-BASED DATA STORAGE PATTERN AND BACK GATEAugust 2024February 2026Allow1800NoNo
18797072PRE-CHARGE AT READ RECOVERY CLOCK FROM BIT LINE SIDE FOR SUB-BLOCK ONE PERFORMANCE IMPROVEMENTAugust 2024March 2026Allow1900NoNo
18795750MEMORY DEVICES AND METHODS OF PERFORMING ROW ACCESS COUNTING OPERATIONSAugust 2024March 2026Allow1900NoNo
18796143MEMORY WITH DOUBLE REDUNDANCYAugust 2024March 2026Allow1900NoNo
18795818MEMORY SYSTEMAugust 2024March 2026Allow1900NoNo
18793984NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACEAugust 2024February 2026Allow1900NoNo
18793177VARIABLE RESISTANCE MEMORY DEVICEAugust 2024March 2026Allow1900NoNo
18791722MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SYSTEMAugust 2024February 2026Allow1900NoNo
18789866SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAMEJuly 2024March 2026Allow1910NoNo
18789717Pulse Signal Generator System for a Magnetoresistive Random Access Memory ArrayJuly 2024January 2026Allow1700NoNo
18789680SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CIRCUITRYJuly 2024February 2026Allow1800NoNo
18790480READ VOLTAGE LEVEL BIN SELECTIONJuly 2024February 2026Allow1800NoNo
18788725WORD LINE BOOSTER CIRCUIT AND METHODJuly 2024February 2026Allow1800NoNo
18788496PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING A PAGE BUFFER CIRCUITJuly 2024February 2026Allow1900NoNo
18789412WRITE LATENCY TESTING SYSTEMS AND METHODSJuly 2024March 2026Allow1900NoNo
18789364CONFIGURABLE PROGRAM VERIFY LEVELS ACCORDING TO PROGRAM-ERASE CYCLES AT A MEMORY SYSTEMJuly 2024January 2026Allow1800NoNo
18788480READ AND WRITE ENHANCEMENTS FOR ARRAYS OF SUPERCONDUCTING MEMORY CELLSJuly 2024March 2026Allow1910NoNo
18788926NON-VOLATILE MEMORY DEVICEJuly 2024January 2026Allow1700NoNo
18786588CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF MEMORYJuly 2024February 2026Allow1910NoNo
18788047SENSING CIRCUIT IN A VERTICAL MEMORY SYSTEMJuly 2024February 2026Allow1900NoNo
18787812CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALINGJuly 2024February 2026Allow1900NoNo
18787957USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCKS IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18788001CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICESJuly 2024February 2026Allow1800NoNo
18787977READ MARGIN HEALTH EVALUATIONS FOR MEMORY SYSTEMSJuly 2024February 2026Allow1800NoNo
18786480PROCESSING IN MEMORY REGISTERSJuly 2024March 2026Allow2000NoNo
18785463WORDLINE GROUP DEPENDENT CORRECTIVE PROGRAM VERIFY OPERATION IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18785362ALL LEVELS PROGRAM OPERATION INTEGRATED WITH CORRECTIVE PROGRAM VERIFY OPERATION IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18786291MEMORY DEVICE WITH A STORAGE COMPONENTJuly 2024January 2026Allow1800NoNo
18785902EFFICIENT EMPTY PAGE SCAN OPERATIONSJuly 2024January 2026Allow1800NoNo
18784049MEMORY DEVICES AND OPERATION METHODS THEREOF, AND MEMORY SYSTEMSJuly 2024February 2026Allow1900NoNo
18784505APPARATUS AND METHODS FOR DETECTING COUPLING FAULTS IN NON-VOLATILE MEMORY DEVICESJuly 2024February 2026Allow1900NoNo
18784152Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory CellsJuly 2024February 2026Allow1800NoNo
18784022ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINESJuly 2024March 2026Allow1900NoNo
18783345SEMICONDUCTOR MEMORY DEVICEJuly 2024March 2026Allow1910NoNo
18781317PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICESJuly 2024January 2026Allow1800NoNo
18781878NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT WITH SERIES TRANSISTOR AND INDIVIDUAL ACCESS TRANSISTORJuly 2024October 2025Allow1500NoNo
18781916NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT WITH SERIES TRANSISTORJuly 2024January 2026Allow1800NoNo
187789783D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATHJuly 2024June 2025Allow1100NoNo
18778321MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEURAL NETWORKJuly 2024January 2026Allow1800NoNo
18775312SYSTEM AND METHOD FOR PROVIDING COMPRESSION ATTACHED MEMORY MODULE COMPRESSION CONNECTORSJuly 2024December 2024Allow510NoNo
18773628MEMORY CIRCUIT AND WORD LINE DRIVERJuly 2024June 2025Allow1110NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for group 2820.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
384
Examiner Affirmed
250
(65.1%)
Examiner Reversed
134
(34.9%)
Reversal Percentile
63.6%
Higher than average

What This Means

With a 34.9% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
1878
Allowed After Appeal Filing
728
(38.8%)
Not Allowed After Appeal Filing
1150
(61.2%)
Filing Benefit Percentile
90.1%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 38.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Group 2820 - Prosecution Statistics Summary

Executive Summary

Group 2820 is part of Technology Center 2800. This group has examined 85,958 patent applications in our dataset, with an overall allowance rate of 89.9%. Applications typically reach final disposition in approximately 21 months.

Prosecution Patterns

Applications in Group 2820 receive an average of 1.19 office actions before reaching final disposition. The median prosecution time is 21 months.

Strategic Overview

This group-level data aggregates statistics across multiple art units. For more targeted prosecution strategies, review the individual art unit and examiner statistics within this group.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.