USPTO Examiner BERNSTEIN ALLISON - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
189916313D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYDecember 2024June 2025Allow500NoNo
18837881CMOS SRAM CELL HAVING TRENCH STRUCTUREAugust 2024January 2025Allow500NoNo
187789783D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATHJuly 2024June 2025Allow1100NoNo
187387213D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYJune 2024December 2024Allow610NoNo
18676385Se-BASED SELECTOR MATERIAL, SELECTOR UNIT AND METHOD FOR PREPARING THE SAMEMay 2024August 2024Allow200NoNo
18638140THREE-DIMENSIONAL STACKABLE FERROELECTRIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF FORMINGApril 2024April 2025Allow1210NoNo
18603373ONE-TIME PROGRAMMABLE MEMORY DEVICEMarch 2024April 2025Allow1320NoNo
18595464SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEMarch 2024January 2025Allow1110NoNo
18437961FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATESFebruary 2024April 2025Allow1410NoNo
18437549MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICESFebruary 2024April 2025Allow1410NoNo
184292023D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLSJanuary 2024June 2024Allow510NoNo
18410874SEMICONDUCTOR INTEGRATED CIRCUIT DEVICEJanuary 2024January 2025Allow1210NoNo
185273563D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYDecember 2023August 2024Allow810NoNo
185169583D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYNovember 2023April 2024Allow510NoNo
18518142SEMICONDUCTOR MEMORY DEVICES WITH DIFFERENT DOPING TYPESNovember 2023October 2024Allow1110NoNo
185152553D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORYNovember 2023March 2024Allow400NoNo
183888523D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLSNovember 2023January 2024Allow210NoNo
18377418SEMICONDUCTOR DEVICE WITH PROGRAMMABLE UNIT AND METHOD FOR FABRICATING THE SAMEOctober 2023August 2024Allow1010NoNo
18285857THREE-DIMENSIONAL 1S1C MEMORY BASED ON RING CAPACITOR AND PREPARATION METHODOctober 2023April 2025Allow1810NoNo
18233985Memory Device Comprising An Electrically Floating Body TransistorAugust 2023August 2024Allow1210NoNo
18357974INTEGRATION OF FERROELECTRIC MEMORY DEVICES HAVING STACKED ELECTRODES WITH TRANSISTORSAugust 2023July 2024Allow1210NoNo
18448607Stacked SRAM Cell ArchitectureAugust 2023April 2025Allow2000NoNo
18365850MEMORY DEVICES INCLUDING STRINGS OF MEMORY CELLS AND RELATED SYSTEMSAugust 2023March 2025Allow1900NoNo
18365726SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAugust 2023June 2025Allow2200NoNo
18363500SEMICONDUCTOR MEMORY DEVICES WITH ELECTRICALLY ISOLATED STACKED BIT LINES AND METHODS OF MANUFACTUREAugust 2023June 2025Allow2211NoNo
18228282Spacer Stack For Magnetic Tunnel JunctionsJuly 2023December 2024Allow1601NoNo
182271833D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLSJuly 2023October 2023Allow310NoNo
18360764EMBEDDED MEMORY ADJACENT TO NON-MEMORYJuly 2023October 2024Allow1510NoNo
18357838SEMICONDUCTOR MEMORY STRUCTUREJuly 2023March 2025Allow2000NoNo
18354667MEMORY DEVICE AND MANUFACTURING METHOD THEREOFJuly 2023December 2024Allow1701NoNo
18352182SEMICONDUCTOR DEVICEJuly 2023June 2024Allow1100NoNo
18349433SEMICONDUCTOR APPARATUSJuly 2023October 2024Allow1610YesNo
18348418SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAMEJuly 2023May 2024Allow1000NoNo
18348521SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGIONJuly 2023July 2024Allow1210NoNo
18342538SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOFJune 2023August 2024Allow1410NoNo
18339821MEMORY DEVICE AND METHOD FOR FABRICATING THE MEMORY DEVICEJune 2023June 2024Allow1210NoNo
18333145MEMORY DEVICE WITH BOTTOM ELECTRODEJune 2023February 2025Allow2020NoNo
18330258SEMICONDUCTOR STORAGE DEVICEJune 2023June 2024Allow1210NoNo
18321975DEVICE-REGION LAYOUT FOR EMBEDDED FLASHMay 2023April 2024Allow1010YesNo
18312389MEMORY CELL, 3D MEMORY AND PREPARATION METHOD THEREFOR, AND ELECTRONIC DEVICEMay 2023July 2023Allow200NoNo
18140516Integrated Assemblies, and Methods of Forming Integrated AssembliesApril 2023July 2024Allow1510YesNo
18138625MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOFApril 2023April 2024Allow1210NoNo
181250533D SEMICONDUCTOR DEVICE AND STRUCTURE WITH OXIDE BONDINGMarch 2023June 2023Allow310NoNo
18123992STATIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAMEMarch 2023July 2025Allow2700NoNo
18178103SPIN ORBIT TORQUE MAGNETIC MEMORY DEVICES, OPERATING METHODS THEREOF, AND ELECTRONIC APPARATUSES INCLUDING THE MAGNETIC MEMORY DEVICESMarch 2023April 2025Allow2511NoNo
18108117SELF-SELECTING MEMORY DEVICESFebruary 2023June 2025Allow2800NoNo
18097592SEMICONDUCTOR DEVICEJanuary 2023April 2024Allow1510NoNo
18151682THREE-DIMENSIONAL STACKABLE FERROELECTRIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF FORMINGJanuary 2023January 2024Allow1210NoNo
180927273D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORYJanuary 2023March 2023Allow200NoNo
18149442Three-Dimensional Memory Device and MethodJanuary 2023October 2024Allow2230NoNo
18091432SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAMEDecember 2022November 2024Abandon2210NoNo
18065195NEGATIVE CAPACITANCE FOR FERROELECTRIC CAPACITIVE MEMORY CELLDecember 2022February 2025Allow2610YesNo
18064261REACTIVE SERIAL RESISTANCE REDUCTION FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY DEVICESDecember 2022June 2025Allow3001YesNo
18078513THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOFDecember 2022April 2024Allow1610NoNo
18076182SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICEDecember 2022November 2023Allow1100NoNo
18073908SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICEDecember 2022April 2025Allow2900NoNo
18071658Layout pattern of static random access memory and the forming method thereofNovember 2022December 2024Allow2410NoNo
17993245NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICENovember 2022December 2023Allow1310NoNo
18054318NON-LOCAL ANTIFERROMAGNETIC MEMORY STORAGENovember 2022October 2024Allow2300NoNo
17981634SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICENovember 2022November 2024Allow2401NoNo
17979789MEMORY STRUCTURENovember 2022August 2023Allow910NoNo
18050438METHODS OF FORMING MICROELECTRONIC DEVICESOctober 2022October 2023Allow1200NoNo
17974028RESISTIVE MEMORY ELEMENTS ACCESSED BY BIPOLAR JUNCTION TRANSISTORSOctober 2022July 2025Allow3210NoNo
17968058SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAMEOctober 2022April 2025Allow3000NoNo
18047214METHODS OF FORMING ELECTRONIC DEVICES USING MATERIALS REMOVABLE AT DIFFERENT TEMPERATURESOctober 2022January 2024Allow1510NoNo
179615653D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORYOctober 2022November 2022Allow100NoNo
17938200SEMICONDUCTOR DEVICESOctober 2022April 2025Allow3000NoNo
17915285SHIELDED TERMINAL AND SHIELDED CONNECTORSeptember 2022February 2025Allow2910NoNo
17952322MEMORY DEVICESeptember 2022May 2025Allow3201NoNo
17934655SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFSeptember 2022June 2025Allow3210NoNo
17951213SEMICONDUCTOR STRUCTURE, MEMORY AND METHOD FOR OPERATING MEMORYSeptember 2022December 2024Allow2610NoNo
17951596Magnetoresistive Devices Comprising A Synthetic Antiferromagnetic Coupling Layer Of RuAl Having a (110) TextureSeptember 2022September 2024Allow2400NoNo
17944830SEMICONDUCTOR MEMORY DEVICESeptember 2022August 2024Allow2300NoNo
17942126SEMICONDUCTOR DEVICE INCLUDING SELECTOR LAYERSeptember 2022June 2025Allow3310YesNo
17930416SEMICONDUCTOR STRUCTURESeptember 2022March 2025Allow3000NoNo
17930279MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODSSeptember 2022May 2025Allow3201NoNo
17930300SEMICONDUCTOR MEMORY DEVICESeptember 2022March 2025Allow3000NoNo
17901744MEMORY DEVICESeptember 2022March 2025Allow3100NoNo
17823455THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS FORMED WITH AN OXIDE SEMICONDUCTOR CHANNELAugust 2022May 2025Allow3210NoNo
17897255SEMICONDUCTOR DEVICEAugust 2022March 2023Allow700NoNo
17898232MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORSAugust 2022May 2025Allow3201NoNo
17822712STAIRCASE FORMATION IN A MEMORY ARRAYAugust 2022October 2024Allow2611NoNo
17894167SPIN INJECTION SOURCE, MAGNETIC MEMORY, SPIN HALL OSCILLATOR, COMPUTER, AND MAGNETIC SENSORAugust 2022December 2024Allow2810NoNo
17887766SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAMEAugust 2022February 2025Allow3000NoNo
17818923ASYMMETRIC MEMORY CELL DESIGNAugust 2022January 2025Allow2921NoNo
17815285MEMORY STRUCTUREJuly 2022April 2025Allow3200NoNo
17813098ANTIFUSE ARRAY STRUCTURE AND MEMORYJuly 2022January 2023Allow600NoNo
17866756RESISTIVE MEMORY ELEMENT ARRAYS WITH SHARED ELECTRODE STRIPSJuly 2022March 2025Allow3210NoNo
17812866FORMING-FREE RANDOM-ACCESS MEMORY (RRAM) DEVICESJuly 2022May 2024Allow2201NoNo
17855045Highly Textured 001 BiSb And Materials for Making SameJune 2022September 2024Allow2611YesNo
17854803SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOFJune 2022March 2023Allow900NoNo
17853024MEMORY STRUCTUREJune 2022May 2025Allow3510NoNo
17849797SEMICONDUCTOR DEVICESJune 2022March 2025Allow3310YesNo
17845274VARIABLE RESISTANCE MEMORY DEVICEJune 2022March 2024Allow2100NoNo
17785916PREPARATION METHOD OF BIPOLAR GATING MEMRISTOR AND BIPOLAR GATING MEMRISTORJune 2022September 2023Allow1500NoNo
17834144PLASMA-BASED BARRIER LAYER REMOVAL METHOD FOR INCREASING PEAK TRANSCONDUCTANCE WHILE MAINTAINING ON-STATE RESISTANCE AND RELATED DEVICESJune 2022April 2025Allow3510NoNo
17833322Isolation for Multigate DevicesJune 2022May 2025Allow3521NoNo
17826812MEMORY DEVICE AND METHOD OF MANUFACTURING THE MEMORY DEVICEMay 2022January 2025Allow3110NoNo
17664542THREE DIMENSIONAL MEMORY DEVICE CONTAINING RESONANT TUNNELING BARRIER AND HIGH MOBILITY CHANNEL AND METHOD OF MAKING THE SAMEMay 2022March 2025Allow3410NoNo
17751002HORN SHAPED SPACER FOR MEMORY DEVICESMay 2022December 2024Allow3001NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BERNSTEIN, ALLISON.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
9
Examiner Affirmed
7
(77.8%)
Examiner Reversed
2
(22.2%)
Reversal Percentile
34.4%
Lower than average

What This Means

With a 22.2% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
29
Allowed After Appeal Filing
3
(10.3%)
Not Allowed After Appeal Filing
26
(89.7%)
Filing Benefit Percentile
11.3%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 10.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner BERNSTEIN, ALLISON - Prosecution Strategy Guide

Executive Summary

Examiner BERNSTEIN, ALLISON works in Art Unit 2824 and has examined 1,113 patent applications in our dataset. With an allowance rate of 85.4%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 22 months.

Allowance Patterns

Examiner BERNSTEIN, ALLISON's allowance rate of 85.4% places them in the 57% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by BERNSTEIN, ALLISON receive 1.46 office actions before reaching final disposition. This places the examiner in the 34% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by BERNSTEIN, ALLISON is 22 months. This places the examiner in the 81% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -1.9% benefit to allowance rate for applications examined by BERNSTEIN, ALLISON. This interview benefit is in the 6% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 23.6% of applications are subsequently allowed. This success rate is in the 23% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 49.5% of cases where such amendments are filed. This entry rate is in the 69% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 20.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 25% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 62.5% of appeals filed. This is in the 36% percentile among all examiners. Of these withdrawals, 53.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 32.1% are granted (fully or in part). This grant rate is in the 25% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 2.8% of allowed cases (in the 82% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 4.0% of allowed cases (in the 75% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.