USPTO Examiner CHEN XIAOCHUN L - Art Unit 2824

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18810552SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAMPLING CIRCUITAugust 2024February 2026Allow1800NoNo
18795750MEMORY DEVICES AND METHODS OF PERFORMING ROW ACCESS COUNTING OPERATIONSAugust 2024March 2026Allow1900NoNo
18785463WORDLINE GROUP DEPENDENT CORRECTIVE PROGRAM VERIFY OPERATION IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18785362ALL LEVELS PROGRAM OPERATION INTEGRATED WITH CORRECTIVE PROGRAM VERIFY OPERATION IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18759357Adjustable Clock and Power Gating ControlJune 2024December 2025Allow1800NoNo
18759032DRIFT COMPENSATION FOR CODEWORDS IN MEMORYJune 2024February 2026Allow2000NoNo
18752008APPARATUS FOR TSV DATA OUTPUT CONTROL IN MULTIPLE CORE DIESJune 2024January 2026Allow1800NoNo
18747626CIRCUIT SNAPBACK AND CHARGE DIVERSION FOR CROSS-POINT ARRAYSJune 2024March 2026Allow2110YesNo
18741051SRAM STRUCTURESJune 2024August 2025Allow1410NoNo
18735812QUICK PASS WRITE WITH QUASI-LOW VERIFY HIGH LEVELJune 2024December 2025Allow1800NoNo
18733377RESAMPLE START VOLTAGE FOR CALIBRATION IN A PROGRAM OPERATION IMPROVEMENTJune 2024March 2026Allow2110NoNo
18732377MEMORY DEVICE WITH IMPROVED PROGRAM PERFORMANCE AND METHOD OF OPERATING THE SAMEJune 2024April 2025Allow1000NoNo
18676267REDUCING PARTIAL BLOCK PROGRAMMING USING DYNAMIC TRIM SETTINGSMay 2024January 2026Allow2010NoNo
18671835TRACKING RC TIME CONSTANT BY WORDLINE IN MEMORY DEVICESMay 2024April 2025Allow1100NoNo
18667153COMMON MODE SHIFTING OF SINGLE-ENDED SIGNALS BASED ON LINEARITY ANALYSISMay 2024November 2025Allow1800NoNo
18666819NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND READ METHOD OF MEMORY SYSTEMMay 2024January 2025Allow800NoNo
18662013MEMORY CELL ARRANGEMENTS AND METHOD OF OPERATING A MEMORY CELLMay 2024January 2026Allow2010NoNo
18639995VOLTAGE GENERATING CIRCUITApril 2024October 2025Allow1800NoNo
18640912MEMORY CIRCUITApril 2024October 2025Allow1800NoNo
18638379SELF-CALIBRATION IN A MEMORY DEVICEApril 2024December 2025Allow2010NoNo
18622900MODE REGISTER UPDATE (MRUPD) MODEMarch 2024October 2025Allow1900NoNo
18620473READ FOR MEMORY CELL WITH THRESHOLD SWITCHING SELECTORMarch 2024January 2026Allow2210YesNo
18619094HALF GOOD BLOCK HANDLING WITH DEFECTIVE DECK PRE-PROGRAMING IN A MEMORY SUB-SYSTEMMarch 2024October 2025Allow1800NoNo
18605079ENCODED READ-ONLY MEMORY AND DECODERMarch 2024February 2026Allow2310NoNo
18605636TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMSMarch 2024July 2025Allow1610NoNo
18600230PHYSICALLY UNCLONABLE FUNCTION CELL AND OPERATION METHOD OF THE SAMEMarch 2024March 2025Allow1200NoNo
18600281METHOD FOR PROCESSING INPUT VARIABLES BY MEANS OF A PROCESSING DEVICE HAVING AT LEAST ONE TRANSISTOR, DEVICE FOR EXECUTING THE METHOD, COMPUTING DEVICE AND USEMarch 2024October 2025Allow2000NoNo
18583197SLOW-CHARGE-LOSS TRACKING USING FEEDBACK-CONTROL LOOPFebruary 2024September 2025Allow1900NoNo
18441517SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTSFebruary 2024November 2025Allow2100NoNo
18434404MEMORY WITH PARTIAL ARRAY REFRESHFebruary 2024January 2025Allow1200NoNo
18420978COMPACT K-SAT VERIFICATION WITH TCAMSJanuary 2024February 2025Allow1210NoNo
18397533Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored ThereinDecember 2023February 2026Allow2610NoNo
18393820MEMORY WITH ERROR CHECKING AND CORRECTING UNITDecember 2023February 2025Allow1410NoNo
18392199STORAGE DEVICE AND DATA TRAINING METHOD THEREOFDecember 2023January 2026Allow2510YesNo
18389982BITSCAN TECHNIQUES IN A MEMORY DEVICEDecember 2023February 2026Allow2610NoNo
18525216DUAL POWER SUPPLIED MEMORY CELLS AND DETERMINISTIC RESET THEREOF FOR PROGRAMMABLE LOGIC DEVICESNovember 2023September 2025Allow2100NoNo
18524458SEMICONDUCTOR MEMORY DEVICENovember 2023October 2024Allow1100NoNo
18520910MEMORY DEVICE TEST SYSTEMNovember 2023September 2025Allow2100NoNo
18515681METHODS OF TESTING REPAIR CIRCUITS OF MEMORY DEVICESNovember 2023December 2025Allow2510YesNo
18516448TEST CIRCUIT AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE TEST CIRCUITNovember 2023January 2026Allow2610NoNo
18507521SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAMENovember 2023December 2025Allow2510YesNo
18388769MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELLNovember 2023October 2024Allow1100NoNo
18505372PROGRAMMABLE SIGNAL PROCESSING APPARATUSNovember 2023August 2025Allow2100NoNo
18501463MACHINE LEARNING ASSISTED READ VERIFY IN A MEMORY SUB-SYSTEMNovember 2023March 2025Allow1600NoNo
18499234REFRESH CONTROL CIRCUITNovember 2023September 2025Allow2210NoNo
18498267NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAMEOctober 2023April 2025Allow1710YesNo
18384716SELECT GATE MAINTENANCE WITH ADAPTIVE SCAN FREQUENCY IN A MEMORY SUB-SYSTEMOctober 2023August 2025Allow2200NoNo
18492252POWER LOSS ERROR DETECTION USING PARTIAL BLOCK HANDLINGOctober 2023August 2025Allow2200NoNo
18487202CIRCUIT STRUCTURE AND RELATED METHOD FOR RADIATION RESISTANT MEMORY CELLOctober 2023September 2024Allow1100NoNo
18485900PARALLEL TIMING MARGIN TESTING OF MEMORY DEVICESOctober 2023October 2025Allow2410YesNo
18480130DEVICES AND METHODS FOR A FINFET SENSE AMPLIFIEROctober 2023September 2025Allow2410NoNo
18478207FAILURE ANALYSIS DEVICE AND FAILURE ANALYSIS METHODSeptember 2023May 2025Allow2000NoNo
18476411RESERVOIR DEVICE AND RESERVOIR ARRAYSeptember 2023August 2025Allow2310YesNo
18473667SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICESeptember 2023September 2025Allow2310NoNo
18369479RESUMPTION OF PROGRAM OR ERASE OPERATIONS IN MEMORYSeptember 2023January 2025Allow1610YesNo
18465416MEMORY SYSTEMS AND DEVICES THAT SUPPORT METHODS FOR CALIBRATING INPUT OFFSETS THEREINSeptember 2023February 2025Allow1800NoNo
18367075NON-VOLATILE 3D MEMORY SEARCH ARCHITECTURESeptember 2023May 2025Allow2000NoNo
18465541METHOD OF OPERATING MEMORY DEVICE AND MEMORY DEVICE PERFORMING THE SAMESeptember 2023May 2025Allow2000NoNo
18463720MEMORY AND OPERATION METHOD THEREOFSeptember 2023May 2025Allow2000NoNo
18459447PAGE BUFFER CIRCUIT AND READ OPERATION METHOD OF MEMORYSeptember 2023July 2025Allow2310NoNo
18237786ROW TRACKING FOR ROW HAMMER MITIGATIONAugust 2023May 2025Allow2000NoNo
18454293MEMORY DEVICE REDUCING I/O SIGNAL LINES THROUGH I/O MAPPING CONNECTION AND MEMORY SYSTEM INCLUDING THE SAMEAugust 2023August 2025Allow2410YesNo
18235189NON-VOLATILE MEMORY DEVICE, CONTROLLER AND MEMORY SYSTEMAugust 2023January 2025Allow1710NoNo
18234185ENERGY EFFICIENT FAST READ IN A MEMORY DEVICEAugust 2023September 2025Allow2510NoNo
18448274Capacitor Health Check For Data Storage DevicesAugust 2023October 2025Allow2610YesNo
18447776COMPACT K-XOR-SAT FILTERING WITH CAMSAugust 2023April 2025Allow2000NoNo
18447311CALIBRATION DEVICE AND MEMORY DEVICE INCLUDING THE CALIBRATION DEVICE FOR A HIGH-SPEED DATA I/O OPERATION UNDER A LOW POWER CONDITIONAugust 2023December 2024Allow1600NoNo
18446508DELAY CONTROL CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORYAugust 2023July 2025Allow2410NoNo
18365894SIMULTANEOUS LOWER TAIL VERIFY WITH UPPER TAIL VERIFYAugust 2023March 2025Allow1910YesNo
18361841NON-VOLATILE MEMORY WITH DECLINE STATE OPERATIONJuly 2023July 2025Allow2410YesNo
18361842NON-VOLATILE MEMORY WITH SUB-BLOCK PROGRAMMINGJuly 2023July 2025Allow2410YesNo
18227409PROGRAMMING METHOD OF NON-VOLATILE MEMORY CELLJuly 2023January 2025Allow1800NoNo
18227264ZQ CALIBRATION CIRCUIT, OPERATION METHOD, MEMORY AND MEMORY SYSTEMJuly 2023March 2025Allow1910YesNo
18358177MEMORY CIRCUIT AND METHOD OF OPERATING THE SAMEJuly 2023August 2024Allow1300NoNo
18223358GENERATION OF QUICK PASS WRITE BIASES IN A MEMORY DEVICEJuly 2023August 2025Allow2510NoNo
18222640MEMORY SYSTEMJuly 2023July 2025Allow2410NoNo
18353709DYNAMIC CLOCK MASK BASED ON READ DATA FOR POWER SAVINGJuly 2023December 2024Allow1700NoNo
18219289Masking Techniques for Memory ApplicationsJuly 2023May 2025Allow2210NoNo
18219426FERROELECTRIC MEMORY WRITING METHOD AND ASSOCIATED DEVICESJuly 2023May 2025Allow2310NoNo
18347852SRAM INCLUDING REFERENCE VOLTAGE GENERATOR AND READ METHOD THEREOFJuly 2023June 2025Allow2310YesNo
18348009DELAY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND DELAY CONTROL METHODJuly 2023March 2025Allow2100NoNo
18346329FOLDING ORDERING SCHEME FOR IMPROVED THROUGHPUT IN NON-VOLATILE MEMORYJuly 2023January 2025Allow1900NoNo
18330404MEMORY DEVICE AND OPERATION METHOD THEREOFJune 2023December 2024Allow1800NoNo
18326303APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITECTURESMay 2023August 2024Allow1400NoNo
18324797Power Loss Reduction in Data Storage ArraysMay 2023February 2025Allow2100NoNo
18322170META MODEL EXTENSION FOR A MACHINE LEARNING EQUALIZERMay 2023March 2025Allow2200NoNo
18317665ONE TIME PROGRAMMABLE MEMORYMay 2023November 2024Allow1810NoNo
18195860MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIEMay 2023July 2024Allow1400NoNo
18314568PV Distribution Variation Detection and Data Reclaim PolicyMay 2023May 2025Allow2410NoNo
18138820SEMICONDUCTOR MEMORY DEVICEApril 2023May 2024Allow1300NoNo
18302510REPAIRABLE LATCH ARRAYApril 2023May 2024Allow1300NoNo
18298915MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICEApril 2023April 2025Allow2410NoNo
18133103TRACKING AND REFRESHING STATE METRICS IN MEMORY SUB-SYSTEMSApril 2023December 2023Allow800NoNo
18297908SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SYNCHRONIZING CLOCK SIGNALS IN CS GEARDOWN MODEApril 2023February 2025Allow2210YesNo
18297605Memory Device Having Variable Impedance Memory Cells and Time-to-Transition Sensing of Data Stored ThereinApril 2023June 2024Allow1410YesNo
18295013DETERMINATION CIRCUIT AND MEMORY DEVICE AND PERIPHERAL CIRCUIT THEREOFApril 2023October 2024Allow1900NoNo
18119458MEMORY DEVICE AND OPERATION METHOD THEREOFMarch 2023July 2025Allow2930YesNo
18177320MEMORY DEVICE AND OPERATING METHOD THEREOFMarch 2023April 2024Allow1400NoNo
18175375CIRCUIT FOR GENERATING AND TRIMMING PHASES FOR MEMORY CELL READ OPERATIONSFebruary 2023June 2023Allow400NoNo
18173730MEMORY DEVICE WITH IMPROVED PROGRAM PERFORMANCE AND METHOD OF OPERATING THE SAMEFebruary 2023February 2024Allow1200NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner CHEN, XIAOCHUN L.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
1
(50.0%)
Examiner Reversed
1
(50.0%)
Reversal Percentile
74.5%
Higher than average

What This Means

With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
3
Allowed After Appeal Filing
1
(33.3%)
Not Allowed After Appeal Filing
2
(66.7%)
Filing Benefit Percentile
53.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner CHEN, XIAOCHUN L - Prosecution Strategy Guide

Executive Summary

Examiner CHEN, XIAOCHUN L works in Art Unit 2824 and has examined 527 patent applications in our dataset. With an allowance rate of 93.4%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 15 months.

Allowance Patterns

Examiner CHEN, XIAOCHUN L's allowance rate of 93.4% places them in the 81% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by CHEN, XIAOCHUN L receive 1.06 office actions before reaching final disposition. This places the examiner in the 11% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by CHEN, XIAOCHUN L is 15 months. This places the examiner in the 99% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -4.6% benefit to allowance rate for applications examined by CHEN, XIAOCHUN L. This interview benefit is in the 6% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 26.3% of applications are subsequently allowed. This success rate is in the 43% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 45.0% of cases where such amendments are filed. This entry rate is in the 68% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 50.0% of appeals filed. This is in the 18% percentile among all examiners. Of these withdrawals, 50.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.

Petition Practice

When applicants file petitions regarding this examiner's actions, 45.5% are granted (fully or in part). This grant rate is in the 39% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.2% of allowed cases (in the 52% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.4% of allowed cases (in the 54% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.