USPTO Art Unit 2812 Prosecution Statistics

Art Unit Information

Art Unit: 2812
Group: 2810
Tech Center: 2800
Total Cases: 24,498
Last Active: December 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19004132SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTUREDecember 2024May 2025Allow510NoNo
18879209METHOD FOR CONTROLLING SURFACE CHARACTERISTICS AND THICKNESS OF MULTILAYER TRANSITION METAL DICHALCOGENIDE THIN FILMDecember 2024March 2025Allow300NoNo
18980888SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTUREDecember 2024April 2025Allow410NoNo
18981113SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTUREDecember 2024April 2025Allow410NoNo
18979543Semiconductor Structure and Manufacturing Method ThereofDecember 2024February 2025Allow200NoNo
18872218VERTICAL IGBT WITH COMPLEMENTARY CHANNEL FOR HOLE EXTRACTIONDecember 2024April 2025Allow400NoNo
18865498METHOD FOR TRANSFERRING A LAYER FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATENovember 2024May 2025Allow610NoNo
18937369TRENCH GATE SILICON CARBIDE MOSFET DEVICE AND FABRICATION METHOD THEREOFNovember 2024December 2024Allow200NoNo
18911535INTEGRATED POLYPHASE HYDROGEL AND PREPARATION METHOD AND APPLICATION THEREOF IN FLEXIBLE AND STRETCHABLE SUPERCAPACITOROctober 2024April 2025Allow601NoNo
18907921Advanced Low Electrostatic Field TransistorOctober 2024February 2025Allow500YesNo
18816975STACKABLE AND EMBEDDABLE VERTICAL CAPACITORS IN SEMICONDUCTOR DEVICES AND METHOD OF FABRICATIONAugust 2024May 2025Allow902NoNo
18792267THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICONAugust 2024May 2025Allow920YesNo
18785583SILICON CARBIDE SPLIT-GATE MOSFETS INTEGRATING HIGH-SPEED FREEWHEELING DIODES AND PREPARATION METHODS THEREOFJuly 2024February 2025Allow720NoNo
18777737SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESJuly 2024February 2025Allow700NoNo
18774563TRENCH MOS RECTIFIER WITH TERMINATION STRUCTUREJuly 2024December 2024Allow501YesNo
18769958Conductive Feature FormationJuly 2024March 2025Allow800NoNo
18769902HIGH-ELECTRON-MOBILITY TRANSISTORS WITH INACTIVE GATE BLOCKSJuly 2024September 2024Allow310NoNo
18770547NOVEL PHASE CHANGE RANDOM ACCESS MEMORY DEVICEJuly 2024April 2025Allow910NoNo
18768561METHOD FOR FORMING SEMICONDUCTOR STRUCTUREJuly 2024May 2025Allow1000NoNo
18766944DISPLAY DEVICEJuly 2024April 2025Allow910NoNo
18766867Semiconductor Transistor Devices Having Double-sided Interconnect StructuresJuly 2024June 2025Allow1110NoNo
18764641LIGHT EMITTING ELEMENTJuly 2024June 2025Allow1110YesNo
18764971SEMICONDUCTOR DEVICE HAVING METALLIZATION LAYER WITH LOW CAPACITANCE AND METHOD FOR MANUFACTURING THE SAMEJuly 2024June 2025Allow1110NoNo
18762560Manufacturing Method for a Power MOSFET with Gate-Source ESD Diode StructureJuly 2024October 2024Allow310NoNo
18760829INCREASING SOURCE/DRAIN DOPANT CONCENTRATION TO REDUCED RESISTANCEJuly 2024March 2025Allow900YesNo
18761200SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAMEJuly 2024June 2025Allow1110NoNo
18759611FORMING SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALSJune 2024May 2025Allow1010NoNo
18756008METHOD AND STRUCTURE FOR BARRIER-LESS PLUGJune 2024February 2025Allow801NoNo
18754754DISPLAY DEVICE WITH TOUCH SENSING LAYERJune 2024April 2025Allow1010NoNo
18754448IMAGE SENSOR AND MANUFACTURING PROCESS THEREOFJune 2024March 2025Allow900NoNo
18755342MULTI-GATE DEVICE AND RELATED METHODSJune 2024March 2025Allow801NoNo
18753892PACKAGING OF A SEMICONDUCTOR DEVICE WITH A PLURALITY OF LEADSJune 2024May 2025Allow1010NoNo
18751724CHIP PACKAGE STRUCTURE WITH LIDJune 2024May 2025Allow1010NoNo
18750063BIPOLAR JUNCTION TRANSISTOR WITH GATE OVER TERMINALSJune 2024January 2025Allow700NoNo
18749899SEMICONDUCTOR STRUCTURE WITH AIR GAP IN PATTERN-DENSE REGION AND METHOD OF MANUFACTURING THE SAMEJune 2024January 2025Allow710NoNo
18750751NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHTJune 2024April 2025Allow1010NoNo
18748489METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON 28 EPITAXIAL LAYERJune 2024February 2025Allow710NoNo
18747615Semiconductor Device with Uneven Electrode Surface and Method for Fabricating the SameJune 2024January 2025Allow700NoNo
18746928AN INTEGRATED CIRCUIT DEVICE INCLUDING AN N-CHANNEL METAL-OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR REIGION AND A P-CHANNEL MOS (PMOS) TRANSISTOR REGIONJune 2024June 2025Allow1110NoNo
18743453SEMICONDUCTOR DEVICE WITH PROGRAMMABLE STRUCTURE AND METHOD FOR FABRICATING THE SAMEJune 2024January 2025Allow700NoNo
18741998METHOD OF FORMING A GATE STRUCTURE INCLUDING SEMICONDUCTOR MATERIAL IMPLANTATION INTO DUMMY GATE STACKJune 2024February 2025Allow800NoNo
18739078REINFORCED THIN-FILM DEVICEJune 2024April 2025Allow1000NoNo
18738742SEMICONDUCTOR DEVICES DEVICES INCLUDING CRYSTALLIZED LAYER HAVING MULTIPLE CRYSTALLINE ORIENTATIONS AND METHODS OF MANUFACTUREJune 2024February 2025Allow800NoNo
18739140SILVER PATTERNING AND INTERCONNECT PROCESSESJune 2024December 2024Allow600NoNo
18737166Nanosheet Devices With Hybrid Structures And Methods Of Fabricating The SameJune 2024April 2025Allow1010NoNo
18737600IMAGE SENSOR DEVICE AND METHODS OF FORMING THE SAMEJune 2024March 2025Allow1010NoNo
18735999SEMICONDUCTOR NANOPARTICLES, METHOD OF PRODUCING THE SEMICONDUCTOR NANOPARTICLES, AND LIGHT-EMITTING DEVICEJune 2024January 2025Allow810NoNo
18733451LASER DRILLING OF METAL FOILS FOR ASSEMBLY IN AN ELECTROLYTIC CAPACITORJune 2024February 2025Allow810NoNo
18733213Light-Emitting Diode Chip, Display Substrate And Manufacturing Method ThereofJune 2024April 2025Allow1010YesNo
18678215SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFMay 2024May 2025Allow1110NoNo
18676380FOLDABLE, FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMEMay 2024March 2025Allow1001NoNo
18676451IMAGE SENSORMay 2024January 2025Allow800NoNo
18675560SEMICONDUCTOR DIE PACKAGE WITH RING STRUCTUREMay 2024March 2025Allow1000NoNo
18676465SEMICONDUCTOR STRUCTURES OF ANTI-FUSE DEVICES AND CORE DEVICES WITH DIFFERENT DIELECTRIC LAYERSMay 2024April 2025Allow1120NoNo
18674930MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGEMay 2024April 2025Allow1110YesNo
18674136DISPLAY DEVICE AND ELECTRONIC APPARATUSMay 2024March 2025Allow1010NoNo
18674649SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTUREMay 2024December 2024Allow611NoNo
18674589INTRODUCING FLUORINE TO GATE AFTER WORK FUNCTION METAL DEPOSITIONMay 2024May 2025Allow1210NoNo
18674249REDUCING PARASITIC CAPACITANCE IN FIELD-EFFECT TRANSISTORSMay 2024May 2025Allow1210NoNo
18673632MULTIPLE BACK SIDE/BURIED POWER RAIL (BPR) CELL INCLUDING FIELD-EFFECT TRANSISTORS WITH AIR VOID BETWEEN TWO ADJACENT BPR CELLSMay 2024April 2025Allow1110NoNo
18673998GATES STRUCTURES OF NANOSTRUCTURE FIELD-EFFECT TRANSISTORS (NANO-FETs) INCLUDING A PLURALITY OF SEMICONDUCTOR BASED CAPPING MATERIALS AND METHODS OF FORMING THE SAMEMay 2024May 2025Allow1210NoNo
18673099METHOD OF FORMING A REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICEMay 2024April 2025Allow1101NoNo
18670594PHOTOELECTRIC CONVERSION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, AND MOVING OBJECTMay 2024June 2025Allow1210NoNo
18669624FinFET Structures and Methods of Forming the SameMay 2024March 2025Allow1010NoNo
18670132BACKSIDE GATE CONTACTMay 2024January 2025Allow800NoNo
18669514DISPLAY DEVICE WITH LIGHT EMITTING ELEMENTS ON PARALLEL ELECTRODE BRANCHES EXTENDING FROM SEPARATE PARALLEL ELECTRODESMay 2024April 2025Allow1110NoNo
18668777SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTINGMay 2024April 2025Allow1101NoNo
186682183D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERSMay 2024November 2024Allow620NoNo
18665858LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING UNITS INCLUDING EPITAXIAL STRUCTURE AND CONDUCTIVE STRUCTUREMay 2024January 2025Allow800NoNo
18666465NANOSTRUCTURE FIELD-EFFECT TRANSISTORS INCLUDING SOURCE/DRAIN FEATURES WITH ASYMMETRICAL DEPTHMay 2024May 2025Allow1210NoNo
18663563LATERALLY-DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES WITH AN AIR GAPMay 2024September 2024Allow411NoNo
18663523HETEROJUNCTION BIPOLAR TRANSISTORS WITH TERMINALS HAVING A NON-PLANAR ARRANGEMENTMay 2024October 2024Allow511NoNo
18662267CUPROUS OXIDE DEVICES AND FORMATION METHODSMay 2024April 2025Allow1110NoNo
18660461NANOSHEET FIELD-EFFECT TRANSISTOR DEVICE INCLUDING MULTI-LAYER SPACER FILM AND METHOD OF FORMINGMay 2024March 2025Allow1010NoNo
18661171SEMICONDUCTOR DEVICE HAVING MULTI-BRIDGE CHANNEL FIELD-EFFECT TRANSISTOR INCLUDING SOURCE/DRAIN PATTERN WITH A PLURALITY OF SEMICONDUCTOR PATTERNSMay 2024March 2025Allow1010NoNo
18659863IMAGING DEVICE AND CAMERA SYSTEM INCLUDING PHOTOELECTRIC CONVERSION LAYER BETWEEN TWO ELECTRODES, AND DRIVING METHOD OF IMAGING DEVICEMay 2024April 2025Allow1110NoNo
18659343IN-CHAMBER LOW-PROFILE SENSOR ASSEMBLYMay 2024April 2025Allow1110YesNo
18659692ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOFMay 2024March 2025Allow1010NoNo
18658521AIR SPACERS AROUND CONTACT PLUGS AND METHOD FORMING SAMEMay 2024May 2025Allow1210NoNo
18658333FALSE COLLECTORS AND GUARD RINGS FOR SEMICONDUCTOR DEVICESMay 2024November 2024Allow700NoNo
18656610BACKSIDE ILLUMINATED IMAGE SENSOR AND MANUFACTURING METHOD THEREOFMay 2024March 2025Allow1010NoNo
18655822ELECTRONIC PACKAGE COMPRISING CONDUCTIVE LAYER CONNECTED ELECTRODE PAD THROUGH ELECTRONIC COMPONENTMay 2024June 2025Allow1310NoNo
18656277INTEGRATED CIRCUIT PACKAGES HAVING ADHESION LAYERS FOR THROUGH VIASMay 2024April 2025Allow1110NoNo
18653955METHODS OF SELECTIVE OXIDATION ON RAPID THERMAL PROCESSING (RTP) CHAMBER WITH ACTIVE STEAM GENERATIONMay 2024March 2025Allow1110NoNo
18651840IMAGE SENSOR PACKAGEMay 2024May 2025Allow1310NoNo
18650218SEMICONDUCTOR DEVICE INCLUDING WALL FIN WITH DIELECTRIC LAYERS DISPOSED BETWEEN GATE-ALL-AROUND TRANSISTORSApril 2024March 2025Allow1010NoNo
18706187COMPUTATIONAL GRAPH COMPILING AND SCHEDULING METHODS AND RELATED PRODUCTSApril 2024May 2025Allow1300NoNo
18648979PHASE CONTROL IN CONTACT FORMATIONApril 2024December 2024Allow800NoNo
18646520DISPLAY PANEL HAVING AN ARRANGEMENT BY UNIT PIXEL PAIRSApril 2024June 2025Allow1310NoNo
18645551METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS INCLUDING A PLURALITY OF NANOSHEETSApril 2024April 2025Allow1100YesNo
18644136METHOD FOR FORMING SEMICONDUCTOR MEMORY DEVICEApril 2024January 2025Allow900NoNo
18645181REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGESApril 2024November 2024Allow700NoNo
18643632FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROMApril 2024November 2024Allow600NoNo
18643035SEMICONDUCTOR DEVICE STRUCTURE INCLUDING DIELECTRIC REGION WITH PLURALITY OF DIFFERENT OXIDATION REGIONSApril 2024March 2025Allow1110NoNo
18642509SEMICONDUCTOR DEVICEApril 2024November 2024Allow700NoNo
18637723METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE STRUCTUREApril 2024April 2025Allow1220NoNo
18638396METHOD OF MAKING INTEGRATED CIRCUIT MEDICAL DEVICESApril 2024March 2025Allow1110NoNo
18636545METHOD FOR PREPARING RECESSED GATE STRUCTURE WITH PROTECTION LAYERApril 2024January 2025Allow910NoNo
18636248LIGHT EMITTING ELEMENT, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE INCLUDING THE LIGHT EMITTING ELEMENTApril 2024November 2024Allow700NoNo
18636253DISPLAY DEVICEApril 2024March 2025Allow1110NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2812.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
107
Examiner Affirmed
72
(67.3%)
Examiner Reversed
35
(32.7%)
Reversal Percentile
51.6%
Higher than average

What This Means

With a 32.7% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
724
Allowed After Appeal Filing
300
(41.4%)
Not Allowed After Appeal Filing
424
(58.6%)
Filing Benefit Percentile
87.9%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 41.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2812 - Prosecution Statistics Summary

Executive Summary

Art Unit 2812 is part of Group 2810 in Technology Center 2800. This art unit has examined 24,498 patent applications in our dataset, with an overall allowance rate of 87.3%. Applications typically reach final disposition in approximately 22 months.

Comparative Analysis

Art Unit 2812's allowance rate of 87.3% places it in the 84% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2812 receive an average of 1.35 office actions before reaching final disposition (in the 16% percentile). The median prosecution time is 22 months (in the 88% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.