USPTO Examiner YI CHANGHYUN - Art Unit 2812

Examiner Information

Name: YI, CHANGHYUN
Art Unit: 2812
Total Cases: 205
Last Active: July 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18766867Semiconductor Transistor Devices Having Double-sided Interconnect StructuresJuly 2024June 2025Allow1110NoNo
18759611FORMING SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALSJune 2024May 2025Allow1010NoNo
18746928AN INTEGRATED CIRCUIT DEVICE INCLUDING AN N-CHANNEL METAL-OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR REIGION AND A P-CHANNEL MOS (PMOS) TRANSISTOR REGIONJune 2024June 2025Allow1110NoNo
18674589INTRODUCING FLUORINE TO GATE AFTER WORK FUNCTION METAL DEPOSITIONMay 2024May 2025Allow1210NoNo
18674249REDUCING PARASITIC CAPACITANCE IN FIELD-EFFECT TRANSISTORSMay 2024May 2025Allow1210NoNo
18673632MULTIPLE BACK SIDE/BURIED POWER RAIL (BPR) CELL INCLUDING FIELD-EFFECT TRANSISTORS WITH AIR VOID BETWEEN TWO ADJACENT BPR CELLSMay 2024April 2025Allow1110NoNo
18673998GATES STRUCTURES OF NANOSTRUCTURE FIELD-EFFECT TRANSISTORS (NANO-FETs) INCLUDING A PLURALITY OF SEMICONDUCTOR BASED CAPPING MATERIALS AND METHODS OF FORMING THE SAMEMay 2024May 2025Allow1210NoNo
18670132BACKSIDE GATE CONTACTMay 2024January 2025Allow800NoNo
18666465NANOSTRUCTURE FIELD-EFFECT TRANSISTORS INCLUDING SOURCE/DRAIN FEATURES WITH ASYMMETRICAL DEPTHMay 2024May 2025Allow1210NoNo
18661171SEMICONDUCTOR DEVICE HAVING MULTI-BRIDGE CHANNEL FIELD-EFFECT TRANSISTOR INCLUDING SOURCE/DRAIN PATTERN WITH A PLURALITY OF SEMICONDUCTOR PATTERNSMay 2024March 2025Allow1010NoNo
18645551METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS INCLUDING A PLURALITY OF NANOSHEETSApril 2024April 2025Allow1100YesNo
18630814INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE INTERCONNECTION STRUCTURE HAVING AIR GAPApril 2024May 2025Allow1310YesNo
18627635SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOFApril 2024April 2025Allow1310NoNo
18622659SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICESMarch 2024March 2025Allow1210YesNo
18618329SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR WITH NANOSTRUCTURE BASED LAMINATED CHANNEL STRUCTURE AND A FIELD EFFECT TRANSISTOR WITH A SINGLE CHANNEL STRUCTUREMarch 2024April 2025Allow1210NoNo
18610318SEMICONDUCTOR DEVICE WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOFMarch 2024March 2025Allow1210NoNo
18604670SEMICONDUCTOR TRANSISTOR STRUCTURE WITH NANOSTRUCTURES AND CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEMarch 2024April 2025Allow1310NoNo
18602684METHOD AND SYSTEM FOR FABRICATING FIDUCIALS USING SELECTIVE AREA GROWTHMarch 2024February 2025Allow1210NoNo
18599779SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE HAVING GRADED GERMANIUMMarch 2024June 2025Allow1520YesNo
18591771DISPLAY SUBSTRATE HAVING PHOTO SPACER AND PIXEL DEFINING LAYER INCLUDING A PLURALITY OF OPENINGS AND DISPLAY DEVICEFebruary 2024March 2025Allow1310NoNo
18588727SEMICONDUCTOR DEVICE WITH BACKSIDE SELF-ALIGNED POWER RAIL AND METHODS OF FORMING THE SAMEFebruary 2024February 2025Allow1110NoNo
18584028TRANSISTOR DEVICE FOR SOURCE/DRAIN BACKSIDE CONTACT AND METHOD OF FORMING CAVITYFebruary 2024December 2024Allow1010NoNo
18440499SEMICONDUCTOR DEVICE INCLUDING STANDARD CELLSFebruary 2024September 2024Allow700YesNo
18438653INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE DIELECTRIC LAYER HAVING AIR GAPFebruary 2024January 2025Allow1110NoNo
18436052SEMICONDUCTOR DEVICE TRANSISTOR HAVING MULTIPLE CHANNELS WITH DIFFERNT WIDTHS AND MATERIALSFebruary 2024March 2025Allow1310NoNo
18427581DIELECTRIC LINER FOR FIELD EFFECT TRANSISTORSJanuary 2024June 2025Allow1720YesNo
18425895Gate structure of transistor including a plurality of work function layers and oxygen device and methodJanuary 2024December 2024Allow1010NoNo
18421121Source/Drain Structure with Enhanced Dopant Diffusion for Semiconductor DeviceJanuary 2024December 2024Allow1110YesNo
18414753Nanostructure Field-effect Transistor (nano-FET) with Gates including a seam in p-type work function metal between nanostructures and Methods of FormingJanuary 2024February 2025Allow1310YesNo
18410681Cavity Spacer for Nanowire TransistorsJanuary 2024February 2025Allow1310NoNo
18410409FIN FIELD EFFECT TRANSISTORS (FINFET) DEVICE INCLUDING A PLURALITY OF RECESSED REGIONS ALTERNATING WITH UNRECESSED REGIONS IN CHANNEL STACKJanuary 2024February 2025Allow1310NoNo
18408223GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEVICES WITH SOURCE/DRAIN-TO-SUBSTRATE ELECTRICAL CONTACTJanuary 2024January 2025Allow1210YesNo
18406827HIGH VOLTAGE ISOLATION DEVICES FOR SEMICONDUCTOR DEVICESJanuary 2024December 2024Allow1110NoNo
18406025INTEGRATED CIRCUIT INCLUDING DIPOLE INCORPORATION FOR THRESHOLD VOLTAGE TUNING IN TRANSISTORSJanuary 2024February 2025Allow1310NoNo
18401764STACKED MULTI-GATE STRUCTURE AND METHODS OF FABRICATING THE SAMEJanuary 2024January 2025Allow1310NoNo
18540544TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAINDecember 2023January 2025Allow1310NoNo
18523153GATE ALL AROUND (GAA) TRANSISTOR STRUCTURES HAVING A PLURALITY OF SEMICONDUCTOR NANOSTRUCTURESNovember 2023December 2024Allow1210NoNo
18523214EPITAXIAL SOURCE/DRAIN STRUCTURES FOR MULTIGATE DEVICES AND METHODS OF FABRICATING THEREOFNovember 2023December 2024Allow1310NoNo
18521711METHOD OF MANUFACTURE OVERLAY MARK USING LASER MARKING PROCESS FOR SEMICONDUCTOR DEVICENovember 2023November 2024Allow1110NoNo
18521556SOURCE/DRAIN FORMATION WITH REDUCED SELECTIVE LOSS DEFECTSNovember 2023July 2024Allow800NoNo
18518004SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR PATTERNSNovember 2023August 2024Allow910NoNo
18479323METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A MASKOctober 2023November 2024Allow1310YesNo
18374959SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICESSeptember 2023October 2024Allow1310YesNo
18478373SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME WHERE SEMICONDUCTOR DEVICE INCLUDES HIGH-K DIELECTRIC LAYER THAT DOES NOT EXTEND BETWEEN INHIBITION LAYER AND SIDE OF GATE ELECTRODESeptember 2023August 2024Allow1110YesNo
18369582GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURESSeptember 2023October 2024Allow1310YesNo
18469295STACKED SEMICONDUCTOR TRANSISTOR DEVICE WITH DIFFERENT CONDUCTIVITIES HAVING NANOWIRE CHANNELSSeptember 2023January 2025Allow1610NoNo
18469336Multi-Gate Transistor StructureSeptember 2023November 2024Allow1410NoNo
18239660SEMICONDUCTOR DEVICE-INCLUDING SOURCE AND DRAIN REGIONS AND SUPERLATTICE PATTERN HAVING A PILLAR SHAPEAugust 2023July 2024Allow1110YesNo
18447664CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICESAugust 2023September 2024Allow1310YesNo
18231847SEMICONDUCTOR ARRANGEMENT COMPRISING A SOURCE PAD, GATE PAD, DRAIN PAD, BACKSIDE INTERCONNECT LINE, AND BACKSIDE CONTACT, AND BACKSIDE CONDUCTIVE LINE AND METHOD OF MAKINGAugust 2023August 2024Allow1310NoNo
18366733Semiconductor Device Including a Dielectric Layer Between a Source/Drain Region and a SubstrateAugust 2023October 2024Allow1410NoNo
18231029EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAMEAugust 2023April 2024Allow900NoNo
18364995GATE OXIDE OF NANOSTRUCTURE TRANSISTOR WITH INCREASED CORNER THICKNESSAugust 2023September 2024Allow1410NoNo
18362778GATE-ALL-AROUND TRANSISTOR WITH STRAINED CHANNELSJuly 2023September 2024Allow1410NoNo
18360889INTEGRATION OF SILICON CHANNEL NANOSTRUCTURES AND SILICON-GERMANIUM CHANNEL NANOSTRUCTURESJuly 2023September 2024Allow1310NoNo
18360895Multi-gate transistors with Backside Power Rail And Reduced Gate-Drain CapacitanceJuly 2023June 2024Allow1100YesNo
18358668FINFET STRUCTURE WITH AIRGAP AND METHOD OF FORMING THE SAMEJuly 2023April 2025Allow2030NoNo
18358140Self-Aligned Etch in Semiconductor DevicesJuly 2023April 2024Allow900NoNo
18357637BACKSIDE CONTACT WITH AIR SPACERJuly 2023August 2024Allow1310NoNo
18356997MICROELECTRONIC DEVICES WITH A POLYSILICON STRUCTURE ABOVE A STAIRCASE STRUCTURE, AND RELATED METHODSJuly 2023September 2024Allow1410NoNo
18356256FIN FIELD EFFECT TRANSISTOR DEVICES INCLUDING NMOS DEVICE AND PMOS DEVICE WITH VARIED GEOMETRY OF WORK FUNCTION LAYERSJuly 2023August 2024Allow1310YesNo
18356802BACKSIDE PN JUNCTION DIODEJuly 2023August 2024Allow1310NoNo
18224088FinFET device structure having dielectric features between a plurality of gate electrodes and methods of forming the sameJuly 2023August 2024Allow1310YesNo
18355498HYBRID SEMICONDUCTOR DEVICEJuly 2023August 2024Allow1310NoNo
18351957Method of Forming Interconnect Structure having a Barrier LayerJuly 2023August 2024Allow1310YesNo
18350187METHOD OF MANUFACTURING MULTI-CHANNEL FIELD EFFECT TRANSISTORSJuly 2023May 2024Allow1000YesNo
18348904SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAMEJuly 2023April 2024Allow900NoNo
18344581FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAMEJune 2023July 2024Allow1210NoNo
18344176FIELD EFFECT TRANSISTOR DEVICE WITH AIR GAP SPACER IN SOURCE/DRAIN CONTACTJune 2023September 2024Allow1510NoNo
18212304METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICEJune 2023February 2024Allow800NoNo
18211055METHOD FOR FORMING EPITAXIAL SOURCE/DRAIN FEATURES AND SEMICONDUCTOR DEVICES FABRICATED THEREOFJune 2023December 2024Allow1820YesNo
18332298A METHOD OF MANUFACTURING A HORIZONTAL-NANOSHEET FIELD-EFFECT TRANSISTORJune 2023May 2024Allow1100YesNo
18330082FinFET Device having source/drain regions including a plurality of conductivity types and Manufacturing Method ThereforJune 2023August 2024Allow1410YesNo
18328520GATE-ALL-AROUND DEVICES HAVING SELF-ALIGNED CAPPING BETWEEN CHANNEL AND BACKSIDE POWER RAILJune 2023June 2024Allow1210NoNo
18204469MULTI-BRIDGE CHANNEL TRANSISTORS WITH STACKED SOURCE/DRAIN STRUCTURE AND METHOD OF FORMING THE SAMEJune 2023June 2024Allow1310YesNo
18324682Semiconductor Devices including Horizontal Gate-All-Around (hGAA) Nanostructure Transistors and Methods of FormingMay 2023November 2024Allow1820NoNo
18323575INTEGRATED CIRCUIT DEVICE WITH POWER CONTROL CIRCUIT HAVING VARIOUS TRANSISTOR TYPES AND METHODMay 2023July 2024Allow1410YesNo
18321620BACKSIDE GATE CONTACTMay 2023January 2024Allow800NoNo
18143767METHOD OF FORMING A STATIC RANDOM-ACCESS MEMORY (SRAM) CELL WITH FIN FIELD EFFECT TRANSISTORSMay 2023October 2024Allow1820YesNo
18138865VERTICAL CONDUCTIVE STRUCTURE SURROUNDED BY GUARD RING AND METHOD OF MAKINGApril 2023June 2024Allow1310YesNo
18306629NANOSTRUCTURE FIELD-EFFECT TRANSISTOR DEVICE WITH DIELECTRIC LAYER FOR REDUCING SUBSTRATE LEAKAGE OR WELL ISOLATION LEAKAGE AND METHODS OF FORMINGApril 2023June 2024Allow1410YesNo
18306851Semiconductor Device with Implant and Method of Manufacturing SameApril 2023May 2024Allow1310YesNo
18303360SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAMEApril 2023July 2025Allow2600NoNo
18301554Semiconductor Device Structure with Uneven Gate ProfileApril 2023August 2024Allow1610NoNo
18299438Transistor Gate Electrodes with VoidsApril 2023April 2024Allow1310YesNo
18297892PROTECTIVE LINER FOR SOURCE/DRAIN CONTACT TO PREVENT ELECTRICAL BRIDGING WHILE MINIMIZING RESISTANCEApril 2023January 2025Allow2230YesNo
18190754Channel Configurations with Stacked Segments for Gate-All-Around Based Devices and Methods of Fabrication ThereofMarch 2023January 2025Allow2220YesNo
18190563Backside Via With A Low-K SpacerMarch 2023April 2024Allow1310NoNo
18182928Gate Structure with Non-Linear Profile for TransistorsMarch 2023October 2024Allow1920NoNo
18182837TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGESMarch 2023April 2024Allow1310NoNo
18175221Multigate Device Having Reduced Contact ResistivityFebruary 2023April 2024Allow1410NoNo
18114033DISPLAY DEVICEFebruary 2023February 2024Allow1210NoNo
18169679SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METALFebruary 2023March 2024Allow1310NoNo
18168363ETCH PROFILE CONTROL OF GATE CONTACT OPENINGFebruary 2023March 2024Allow1310NoNo
18166379INTEGRATED CIRCUIT MULTI-GATE TRANSISTORS STRUCTURE WITH GATE VIA AND MANUFACTURING METHOD THEREOFFebruary 2023June 2024Allow1620YesNo
18165102BACK END OF LINE NANOWIRE POWER SWITCH TRANSISTORSFebruary 2023March 2024Allow1310NoNo
18160256FORMING SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALSJanuary 2023March 2024Allow1410YesNo
18101603QUANTUM DOT DEVICE AND QUANTUM DOTSJanuary 2023February 2024Allow1310NoNo
18158148DUAL SIDE CONTACT STRUCTURES IN SEMICONDUCTOR DEVICESJanuary 2023March 2024Allow1410NoNo
18155322METHOD OF MANUFACTURING HEAT DISSIPATION SUBSTRATE WITH HIGH THERMAL CONDUCTIVITY FOR SEMICONDUCTOR DEVICEJanuary 2023August 2024Allow1920YesNo

Appeals Overview

No appeal data available for this record. This may indicate that no appeals have been filed or decided for applications in this dataset.

Examiner YI, CHANGHYUN - Prosecution Strategy Guide

Executive Summary

Examiner YI, CHANGHYUN works in Art Unit 2812 and has examined 205 patent applications in our dataset. With an allowance rate of 100.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 18 months.

Allowance Patterns

Examiner YI, CHANGHYUN's allowance rate of 100.0% places them in the 99% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by YI, CHANGHYUN receive 1.21 office actions before reaching final disposition. This places the examiner in the 21% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by YI, CHANGHYUN is 18 months. This places the examiner in the 94% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.0% benefit to allowance rate for applications examined by YI, CHANGHYUN. This interview benefit is in the 11% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 43.4% of applications are subsequently allowed. This success rate is in the 94% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 23.3% of cases where such amendments are filed. This entry rate is in the 22% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Petition Practice

When applicants file petitions regarding this examiner's actions, 18.2% are granted (fully or in part). This grant rate is in the 10% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 22% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.0% of allowed cases (in the 65% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.