USPTO Examiner RAMALLO GUSTAVO G - Art Unit 2812

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18727085Method of Fabricating a 3D NAND flash memory With Increased Data Retention CapabilityFebruary 2025November 2025Allow1610NoNo
18678141Multi-Die Package Structures Including an Interconnected Package Component disposed in a Substrate CavityMay 2024August 2025Allow1410NoNo
18657259CROSS-POINT MEMORY ARRAY WITH ACCESS LINESMay 2024February 2026Allow2211NoNo
18638220LIGHT-EMITTING ELEMENT WITH A CUSHION PARTApril 2024July 2025Allow1511NoNo
18598250MULTI-DIE PACKAGE STRUCTURES INCLUDING REDISTRIBUTION LAYERSMarch 2024September 2025Allow1821NoNo
18593752INTERCONNECTION STRUCTURE WITH ANTI-ADHESION LAYERMarch 2024September 2025Allow1810NoNo
18588407Memory Array Comprising Strings Of Memory Cells And Conductive Gate Lines Of Different Vertical ThicknessesFebruary 2024December 2024Allow1000NoNo
18442116METHOD FOR FORMING MEMORY DEVICE WITH BURIED GATE IN PERIPHERAL CIRCUIT REGIONFebruary 2024April 2025Allow1420NoNo
18422550THERMAL INTERFACE MATERIAL HAVING DIFFERENT THICKNESSES IN PACKAGESJanuary 2024December 2025Allow2311NoNo
18452910DISPLAY DEVICE AND ELECTRONIC APPARATUS WITH HIGH DENSITY PIXELSAugust 2023May 2025Allow2111NoNo
18452668SEMICONDUCTOR DEVICE WITH PROTECTIVE PROTRUSIONAugust 2023February 2026Allow3040NoNo
18450865MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE WITH A STEPPED MEMORY FILMAugust 2023July 2025Allow2311NoNo
18446776THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH HIGH ASPECT RATIOAugust 2023February 2026Allow3111YesNo
18446160METHOD FOR FORMING FINFET WITH SOURCE/DRAIN REGIONS COMPRISING AN INSULATOR LAYERAugust 2023July 2025Allow2311NoNo
18364662IMAGE SENSOR WITH A HIGH ABSORPTION LAYERAugust 2023December 2025Allow2911NoNo
18196505VERTICAL MEMORY DEVICES INCLUDING INSULATING INTERLAYER COVERING CIRCUIT PATTERN AND INTERMEDIATE INSULATION LAYER ON THE INSULATING INTERLAYERMay 2023April 2025Allow2311NoNo
183085943D SEMICONDUCTOR DEVICE AND ARRAY LAYOUT WITH ISOLATED CONDUCTIVE PILLARSApril 2023March 2025Allow2211NoNo
18307698MICROELECTRONIC DEVICES WITH INCREASED GRAIN SIZEApril 2023January 2026Allow3311NoNo
18139347DOUBLE PATTERNING METHOD OF MANUFACTURING SELECT GATES AND WORD LINESApril 2023February 2026Allow3410NoNo
18138189SEMICONDUCTOR DEVICE HAVING SELECTION LINE STUD CONNECTED TO STRING SELECTION LINEApril 2023June 2025Allow2611YesNo
18306092METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE INCLUDING CHANNEL POSTS OF DIFFERENT SHAPESApril 2023September 2024Allow1710NoNo
18300997MEMORY DEVICE WITH DEFECT-FREE SLITSApril 2023January 2026Allow3311NoNo
18126760Integrated Circuitry, Comprising A Pair Of Opposing Lateral Projections In Insulating Material In A CavityMarch 2023December 2024Allow2110NoNo
18186961MEMORY DEVICE WITH REFORMED INSULATING LAYER AND METHOD OF FABRICATING THE SAMEMarch 2023January 2026Allow3411NoNo
18182385SEMICONDUCTOR STRUCTURE WITH ENHANCES STRENGTH AND MANUFACTURING METHOD THEREOFMarch 2023February 2026Allow3511NoNo
18177921PACKAGE STRUCTURE WITH ADHESIVE ELEMENT OVER SEMICONDUCTOR CHIPMarch 2023July 2025Allow2811NoNo
18177055SEMICONDUCTOR DEVICE WITH IMPROVED CHANNEL MOBILITYMarch 2023January 2026Allow3411NoNo
18172076MICROELECTRONIC DEVICES WITH IMPROVED ALIGNMENT FOR CONTACT STRUCTURESFebruary 2023July 2025Allow2911YesNo
18110935METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE WITH A LOW VOLTAGE TRANSISTORFebruary 2023January 2025Allow2310NoNo
18169877MEMORY DEVICE WITH REDUCED GLOBAL SELECTION LINE STRUCTURES AND METHOD OF FABRICATING THE SAMEFebruary 2023February 2026Allow3611NoNo
18169187ELECTRONIC DEVICE COMPRISING AN ELECTROSTATIC DISCHARGE PROTECTIVE UNITFebruary 2023January 2025Allow2310NoNo
18168582MEMORY STRUCTURE WITH REDUCED BRIDGING AND MANUFACTURING METHOD THEREOFFebruary 2023December 2025Allow3411NoNo
18106306MEMORY DEVICE WITH MULTI CHANNEL STRUCTURES AND METHOD OF MANUFACTURING THE SAMEFebruary 2023September 2025Allow3110NoNo
18163299THREE-DIMENSIONAL MEMORY DEVICE WITH LOW RESISTANCE BUFFER PILLARFebruary 2023December 2025Allow3411NoNo
18103070SEMICONDUCTOR DEVICES WITH STRING SELECT CHANNEL LAYERJanuary 2023December 2024Allow2211NoNo
18005929THREE-DIMENSIONAL FLASH MEMORY HAVING IMPROVED INTEGRATION DENSITYJanuary 2023March 2026Allow3820NoNo
18098552SEMICONDUCTOR MEMORY DEVICE WITH DECREASED PARASITIC CAPACITANCEJanuary 2023November 2025Allow3401NoNo
18154982THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH DIFFUSION STOP LAYER AND ELECTRONIC SYSTEM INCLUDING THE SAMEJanuary 2023January 2026Allow3611YesNo
18154919SEMICONDUCTOR PACKAGE WITH INCREASED THERMAL DISSIPATIONJanuary 2023February 2025Allow2521YesNo
18154210THREE-DIMENSIONAL FLASH MEMORY WITH REDUCED WIRE LENGTH AND MANUFACTURING METHOD THEREFORJanuary 2023October 2024Allow2110YesNo
18094007SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN WITH IMPROVED RETENTION CHARACTERISTICSJanuary 2023June 2025Allow2911YesNo
18151379SEMICONDUCTOR STORAGE DEVICE WITH REDUCED THRESHOLD VOLTAGE FLUCTUATIONSJanuary 2023February 2026Allow3711NoNo
18090981THREE-DIMENSIONAL MEMORY WITH STACKED SELECT-GATE STRUCTURESDecember 2022October 2025Allow3311NoNo
18083431Metal-Containing Structures, and Methods of Treating Metal-Containing Material to Increase Grain Size and/or Reduce Contaminant ConcentrationDecember 2022July 2025Allow3110NoNo
18081040SEMICONDUCTOR MEMORY DEVICE WITH REDUCED STEPPED AREADecember 2022March 2026Allow3911NoNo
18079043Conductive Structure Connection With Interconnect StructureDecember 2022December 2024Allow2411NoNo
18075487THREE-DIMENSIONAL NAND MEMORY DEVICE WITH REDUCED RESISTANCE-CAPACITANCE DELAYDecember 2022March 2025Allow2721YesNo
17994936METHODS OF FORMING 3D NAND STRUCTURES WITH DECREASED PITCHNovember 2022April 2025Allow2830YesNo
17993997MEMORY DEVICE WITH INCREASED DENSITY AND METHOD OF FABRICATING THE SAMENovember 2022January 2026Allow3811NoNo
17991337MULTI-LED STRUCTURES WITH SINGLE CURRENT AND VOLTAGE SUPPLIESNovember 2022August 2025Allow3311NoNo
17990148METHOD FOR FABRICATING SEMICONDUCTOR DEVICE THROUGH ETCH STOP LAYER CONVERSIONNovember 2022October 2025Abandon3530NoNo
17986371VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING GATE ELECTRODES WITH METAL-DOPED GRAPHENENovember 2022December 2025Allow3711YesNo
18051763SEMICONDUCTOR MEMORY DEVICE WITH MESH SUPPORT STRUCTURENovember 2022February 2026Allow3911NoNo
18047109Method of Manufacturing Semiconductor Device Comprising Doping Element in the Charge Storage LayerOctober 2022July 2025Allow3301NoNo
18046756ELECTROMAGNETIC SHIELDS WITH BONDING WIRES FOR SUB-MODULESOctober 2022June 2025Allow3221NoNo
17936842PIXEL STRUCTURE, DISPLAY APPARATUS INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE FOR INCREASING EFFICIENCY OF LIGHT EMISSIONSeptember 2022August 2025Allow3431YesNo
17932942THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING SELECTIVE METAL NITRIDE DEPOSITION ON DIELECTRIC METAL OXIDE BLOCKING DIELECTRICSeptember 2022September 2025Allow3611NoNo
17943172THREE-DIMENSIONAL MEMORY DEVICES WITH DRAIN-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAMESeptember 2022February 2025Allow3021NoNo
17940441METHOD FOR FORMING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH AN IMPROVED ETCHING STEPSeptember 2022January 2025Allow2811YesNo
17898148MEMORY DEVICE WITH PERIODICALLY VARYING MEMORY FILM THICKNESSAugust 2022August 2025Allow3611NoNo
17820031MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURESAugust 2022January 2025Allow2911NoNo
17882053MEMORY CIRCUITRY AND METHOD USED IN FORMING MEMORY CIRCUITRY THAT HAS AN INSULATOR TIER DIRECTLY BELOW A LOWEST UPPER FIRST TIER AND DIRECTLY ABOVE AN UPPERMOST LOWER FIRST TIERAugust 2022January 2026Allow4221NoNo
17881184DISPLAY DEVICE WITH REDUCED PARASITIC CAPACITANCEAugust 2022September 2025Allow3811NoNo
17876036METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH MATERIAL IN MONOCRYSTALLINE PHASEJuly 2022May 2025Allow3401NoNo
17875527CONTACT OVER ACTIVE GATE STRUCTUREJuly 2022September 2024Allow2630YesNo
17876326LATERAL ETCH STOPS FOR ACCESS LINE FORMATION IN A MEMORY DIEJuly 2022October 2025Allow3811NoNo
17874927THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH INCREASED ELECTRON MOBILITY AND ELECTRONIC SYSTEM INCLUDING THE SAMEJuly 2022October 2025Allow3911YesNo
17872894METHOD FOR EVALUATING NON-UNIFORM STRESSJuly 2022April 2025Allow3211NoNo
17813847ELECTRONIC DEVICES INCLUDING AN IMPLANT STRUCTURE, FOR PROTECTION AGAINST CORROSION, AND RELATED SYSTEMS AND METHODSJuly 2022December 2025Allow4121NoNo
17813795ELECTRONIC DEVICES COMPRISING PILLARS EXTENDING THROUGH A SEMICONDUCTOR MATERIAL AND ADJACENT TO A SOURCE IMPLANT REGION, AND RELATED ELECTRONIC SYSTEMS AND METHODSJuly 2022February 2026Allow4321NoNo
17861573THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING VERTICAL STRUCTURES AND SEED LAYERJuly 2022August 2025Allow3711YesNo
17851310THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH INCREASED PROCESS MARGINJune 2022January 2025Allow3111YesNo
17844585METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH SELECTIVELY FORMED NITRIDE FILMJune 2022July 2025Allow3711NoNo
17806842VERTICAL MEMORY DEVICE WITH MULTIPLE SUPPORT LAYERSJune 2022January 2025Allow3111YesNo
17837227MEMORY DEVICE WITH MULTI-LAYERED CHARGE STORAGE STACKJune 2022June 2025Allow3611YesNo
17836799MEMORY DEVICE WITH REDUCED BENDING STACKJune 2022May 2024Allow2411NoNo
17805167MICROELECTRONIC DEVICES INCLUDING IMPLANT REGIONS ADJACENT TO DIELECTRIC SLOT STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODSJune 2022October 2025Allow4111NoNo
17664479Dielectric Spacer to Prevent Contacting ShortingMay 2022March 2024Allow2210NoNo
17740039METHOD FOR MANUFACTURING PEROVSKITE NANOCRYSTAL PARTICLE LIGHT-EMITTER WHERE ORGANIC LIGAND IS SUBSTITUTED, NANOCRYSTAL PARTICLE LIGHT-EMITTER MANUFACTURED THEREBY, AND LIGHT EMITTING DEVICE USING SAMEMay 2022June 2024Allow2500NoNo
17705885SEMICONDUCTOR DEVICE STRUCTURE WITH ETCH STOP LAYER FOR REDUCING RC DELAYMarch 2022September 2024Allow3020NoNo
17699931STACKED OFFSET SEMICONDUCTOR PACKAGEMarch 2022May 2025Allow3710YesNo
17588938THIN FILM TRANSISTORS WITH SPACER CONTROLLED GATE LENGTHJanuary 2022January 2024Allow2410YesNo
17556745THREE-DIMENSIONAL MEMORY DEVICE WITHOUT GATE LINE SLITS AND METHOD FOR FORMING THE SAMEDecember 2021December 2023Allow2410YesNo
17549685ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTACT CONNECTIONDecember 2021November 2025Allow4720YesNo
17457787THREE-DIMENSIONAL MEMORY DEVICE WITH CHARGE TRAP LAYER INCLUDING CARBON REGION AND FABRICATION METHOD THEREOFDecember 2021July 2025Allow4340YesNo
17540190MANUFACTURING METHOD OF THREE-DIMENSIONAL MEMORY DEVICE WITH IMPROVED RC DELAYDecember 2021February 2024Allow2610NoNo
17529331SEMICONDUCTOR DEVICE INCLUDING SUPPORT STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAMENovember 2021February 2025Allow3911YesNo
17528574MRAM MTJ WITH DIRECTLY COUPLED TOP ELECTRODE CONNECTIONNovember 2021August 2024Allow3320YesNo
17451583METHOD OF FORMING A THREE-DIMENSIONAL NAND MEMORY DEVICE WITH REDUCED RC DELAYOctober 2021September 2024Allow3520YesNo
17501951Methods of Forming Integrated Assemblies with Improved Charge Migration ImpedanceOctober 2021July 2024Allow3300NoNo
17500297METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH IMPROVED GATE INSULATION STEPOctober 2021July 2024Allow3301NoNo
17488879THREE-DIMENSIONAL MEMORY DEVICE WITH IMPROVED CHARGE LATERAL MIGRATION AND METHOD FOR FORMING THE SAMESeptember 2021August 2024Allow3420NoNo
17488915THREE-DIMENSIONAL MEMORY DEVICE WITH RESTRAINED CHARGE MIGRATION AND METHOD FOR FORMING THE SAMESeptember 2021September 2024Allow3510NoNo
17488576SEMICONDUCTOR DEVICE INCLUDING SEPARATION PATTERNS AND AN ELECTRONIC SYSTEMSeptember 2021August 2024Allow3511NoNo
17476206METHOD OF FORMING VERTICAL MEMORY DEVICES WITH IMPROVED DUMMY CHANNEL STRUCTURESSeptember 2021July 2024Allow3410NoNo
17465496SEMICONDUCTOR MEMORY DEVICE WITH INCREASED RELIABILITY AND METHOD FOR MANUFACTURING THE SAMESeptember 2021October 2024Allow3811NoNo
17460116SELF-ALIGNED DISPLAY APPARTUSAugust 2021March 2024Allow3020YesNo
17412933METHOD FOR MANUFACTURING A SEMICONDUCTOR STORAGE DEVICE INCLUDING A DIVISION FILMAugust 2021August 2024Allow3611NoNo
17411805ORGANIC SEMICONDUCTOR DEVICE WITH PROTECTIVE SPINEL OXIDE LAYERAugust 2021January 2026Allow5251YesNo
17410895SEMICONDUCTOR DEVICE WITH ADSORPTION PROMOTING LAYERAugust 2021December 2024Allow4021NoNo

Appeals Overview

No appeal data available for this record. This may indicate that no appeals have been filed or decided for applications in this dataset.

Examiner RAMALLO, GUSTAVO G - Prosecution Strategy Guide

Executive Summary

Examiner RAMALLO, GUSTAVO G works in Art Unit 2812 and has examined 70 patent applications in our dataset. With an allowance rate of 100.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.

Allowance Patterns

Examiner RAMALLO, GUSTAVO G's allowance rate of 100.0% places them in the 96% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by RAMALLO, GUSTAVO G receive 1.56 office actions before reaching final disposition. This places the examiner in the 29% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by RAMALLO, GUSTAVO G is 35 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +0.0% benefit to allowance rate for applications examined by RAMALLO, GUSTAVO G. This interview benefit is in the 15% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 43.8% of applications are subsequently allowed. This success rate is in the 95% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 35.7% of cases where such amendments are filed. This entry rate is in the 53% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Petition Practice

When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 4% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 24% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 14.3% of allowed cases (in the 91% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.