USPTO Examiner ASSOUMAN HERVE LOUIS Y - Art Unit 2812

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18792267THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICONAugust 2024May 2025Allow920YesNo
18658521AIR SPACERS AROUND CONTACT PLUGS AND METHOD FORMING SAMEMay 2024May 2025Allow1210NoNo
18406345RESISTANCE MEASURING STRUCTURES OF STACKED DEVICESJanuary 2024February 2025Allow1410YesNo
18398194SEMICONDUCTOR PACKAGEDecember 2023April 2025Allow1610NoNo
18390928SEMICONDUCTOR DEVICE PACKAGE ASSEMBLIES WITH DIRECT LEADFRAME ATTACHMENTDecember 2023February 2025Allow1410NoNo
18519263INTEGRATED CIRCUITS WITH GATE CUT FEATURESNovember 2023May 2025Allow1710NoNo
185120923D TRENCH CAPACITOR FOR INTEGRATED PASSIVE DEVICESNovember 2023February 2025Allow1510NoNo
18508255ELECTRONIC DEVICENovember 2023October 2024Allow1110NoNo
18503673CHIP FABRICATION METHOD AND PRODUCT INCLUDING RAISED AND RECESSED ALIGNMENT STRUCTURESNovember 2023April 2024Allow510NoNo
18386497THROUGH SILICON BURIED POWER RAIL IMPLEMENTED BACKSIDE POWER DISTRIBUTION NETWORK SEMICONDUCTOR ARCHITECTURE AND METHOD OF MANUFACTURING THE SAMENovember 2023August 2024Allow1000NoNo
18489915THROUGH SUBSTRATE VIA (TSV) VALIDATION STRUCTURE FOR AN INTEGRATED CIRCUIT AND METHOD TO FORM THE TSV VALIDATION STRUCTUREOctober 2023February 2025Allow1611NoNo
18381668OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICEOctober 2023September 2024Allow1110NoNo
18379946LIGHT-EMITTING DEVICEOctober 2023November 2024Allow1310NoNo
18368772STIFFENER PACKAGE AND METHOD OF FABRICATING STIFFENER PACKAGESeptember 2023September 2024Allow1310NoNo
18365199MANUFACTURING METHOD OF AN INPUT CIRCUIT OF A FLIP-FLOPAugust 2023October 2024Allow1410NoNo
18227798SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFJuly 2023July 2024Allow1210NoNo
18227779SEMICONDUCTOR DEVICE INCLUDING A GATE-ALL-AROUND FIELD EFFECT TRANSISTORJuly 2023July 2024Allow1110NoNo
18226784SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO GATE STRUCTURE ON PMOS REGIONJuly 2023April 2024Allow910NoNo
18360118Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor CellsJuly 2023September 2024Allow1410NoNo
18359892MICRO ELECTRO MECHANICAL SYSTEM (MEMS) DEVICE HAVING METAL SEALING ON NECKING PORTION OF VENT HOLEJuly 2023September 2024Allow1410NoNo
18357198MULTIPLEXER CELL AND SEMICONDUCTOR DEVICE HAVING CAMOUFLAGE DESIGN, AND METHOD FOR FORMING MULTIPLEXER CELLJuly 2023July 2024Allow1210NoNo
18219374INTERCONNECT TECHNIQUES FOR ELECTRICALLY CONNECTING SOURCE/DRAIN REGIONS OF STACKED TRANSISTORSJuly 2023June 2024Allow1110NoNo
18326841INTEGRATED CIRCUIT DEVICES AND FABRICATION TECHNIQUESMay 2023September 2024Allow1610NoNo
18324643THROUGH VIAS OF SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THEREOFMay 2023December 2024Allow1820NoNo
18302210THERMAL INTERCONNECT STRUCTURE FOR THERMAL MANAGEMENT OF ELECTRICAL INTERCONNECT STRUCTUREApril 2023August 2024Allow1610NoNo
18301461SEMICONDUCTOR DEVICE HAVING A PLURALITY OF III-V SEMICONDUCTOR LAYERSApril 2023June 2024Allow1410NoNo
18110971ORGANIC LIGHT-EMITTING DISPLAY APPARATUSFebruary 2023January 2024Allow1110NoNo
18105648SUBSTRATE PROCESS APPARATUS AND SUBSTRATE PROCESS METHOD USING THE SAMEFebruary 2023May 2025Allow2800NoNo
18156287HIGH BANDWIDTH DIE TO DIE INTERCONNECT WITH PACKAGE AREA REDUCTIONJanuary 2023April 2025Allow2620NoNo
18005418CARTRIDGE FOR INSPECTIONJanuary 2023November 2024Allow2210NoNo
18150934SEMICONDUCTOR STRUCTURE HAVING BURIED WORD LINE STRUCTURE WITH DIELECTRIC LAYERS OF DIFFERENT DIELECTRIC CONSTANTS, AND MANUFACTURING METHOD THEREOFJanuary 2023June 2025Allow3010NoNo
17994841Semiconductor Devices and Methods of ManufacturingNovember 2022April 2024Allow1710NoNo
17990733SEMICONDUCTOR DEVICE FOR ENHANCING QUALITY FACTOR OF INDUCTOR AND METHOD OF FORMING THE SAMENovember 2022October 2024Allow2310NoNo
18053021METAL RAIL CONDUCTORS FOR NON-PLANAR SEMICONDUCTOR DEVICESNovember 2022June 2024Allow1910NoNo
18052510SILICON CARBIDE POWER DEVICE WITH IMPROVED ROBUSTNESS AND CORRESPONDING MANUFACTURING PROCESSNovember 2022June 2024Allow2010NoNo
18046387SEMICONDUCTOR DEVICE, IMAGING UNIT, AND ELECTRONIC APPARATUSOctober 2022June 2024Allow2010NoNo
17934959SEMICONDUCTOR DEVICE HAVING WORD LINE SEPARATION LAYERSeptember 2022February 2024Allow1610NoNo
17888727SEMICONDUCTOR DEVICES INCLUDING SUPPORTERAugust 2022January 2024Allow1710NoNo
17871310MEMS ELECTRICAL AND PHYSICAL CONNECTION VIA SOLDER COUPLINGSJuly 2022May 2025Allow3400NoNo
17845891SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEJune 2022March 2024Allow2110NoNo
17838507METHOD OF REPAIRING A DISPLAY PANEL AND REPAIRED DISPLAY PANELJune 2022June 2025Allow3610NoNo
17805552Air Spacers Around Contact Plugs and Method Forming SameJune 2022February 2024Allow2020NoNo
17752795SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAMEMay 2022March 2025Allow3420YesNo
17752078THREE-DIMENSIONAL MEMORY DEVICE WITH CAPACITORS AND VERTICAL WORD-LINEMay 2022June 2025Allow3611NoNo
17749842STANDARD CELL DESIGN WITH DUMMY PADDINGMay 2022April 2025Allow3510NoNo
17663290NANOSTRUCTURE FET AND METHOD OF FORMING SAMEMay 2022May 2025Allow3611YesNo
17755934MEMS DEVICE, ASSEMBLY COMPRISING THE MEMS DEVICE, AND METHODS FOR OPERATING THE MEMS DEVICEMay 2022November 2024Allow3000NoNo
17741983IMAGE SENSOR, CAMERA DEVICE INCLUDING THE IMAGE SENSOR, ELECTRONIC DEVICE INCLUDING THE CAMERA DEVICE, AND METHOD OF MANUFACTURING THE IMAGE SENSORMay 2022May 2025Allow3610YesNo
17731821DISPLAY DEVICEApril 2022June 2025Allow3821NoNo
17720695MICROELECTRONIC DEVICES INCLUDING SLOT STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS OF FORMING THE MICROELECTRONIC DEVICESApril 2022May 2025Allow3711NoNo
17719281SEMICONDUCTOR DEVICE PACKAGEApril 2022July 2024Allow2810NoNo
17718801MAGNETIC DOMAIN WALL MOVEMENT ELEMENT AND MAGNETIC ARRAYApril 2022March 2025Allow3510NoNo
17715872ELECTRONIC PACKAGEApril 2022March 2025Allow3510NoNo
17710499SEMICONDUCTOR DEVICE STRUCTURE WITH FIN AND METHOD FOR FORMING THE SAMEMarch 2022June 2025Allow3811NoNo
17754250ARRAY SUBSTRATE AND DISPLAY PANELMarch 2022February 2025Allow3510NoNo
17704095DISPLAY APPARATUSMarch 2022April 2025Allow3720NoNo
17674803DISPLAY APPARATUS HAVING DISPLAY AREA SURROUNDING PORTION OF OPENING AREAFebruary 2022April 2025Allow3811NoNo
17672757THROUGH VIAS WITH TEST STRUCTUREFebruary 2022April 2025Allow3811NoNo
17672215GATE METAL-INSULATOR-FIELD PLATE METAL INTEGRATED CIRCUIT CAPACITOR AND METHOD OF FORMING THE SAMEFebruary 2022December 2024Allow3410NoNo
17648903SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING SAME AND STACKED STRUCTUREJanuary 2022September 2024Allow3210NoNo
17648598INTEGRATED CIRCUIT DEVICEJanuary 2022September 2024Allow3210NoNo
17581084SEMICONDUCTOR DEVICE INCLUDING BACKSIDE WIRING STRUCTURE WITH SUPER VIAJanuary 2022November 2024Allow3310YesNo
17577800GATE TO SOURCE DRAIN INTERCONNECTSJanuary 2022January 2025Allow3611NoNo
17576007INTEGRATED CIRCUIT DEVICES INCLUDING A POWER RAIL AND METHODS OF FORMING THE SAMEJanuary 2022October 2024Allow3311NoNo
17571564MEMORY DEVICE AND METHOD OF FORMING THE SAMEJanuary 2022October 2024Allow3310YesNo
17647458SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND STACKED STRUCTUREJanuary 2022September 2024Allow3310NoNo
17647046SEMICONDUCTOR DEVICE AND METHOD FOR FORMING CAPACITOR STRUCTUREJanuary 2022April 2025Allow4020NoNo
17551754DISPLAY APPARATUSDecember 2021August 2024Allow3210NoNo
17547700INTEGRATED CIRCUIT DEVICES INCLUDING A METAL RESISTOR AND METHODS OF FORMING THE SAMEDecember 2021January 2025Allow3811NoNo
17545373ELECTRONIC DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF FABRICATING THE SAMEDecember 2021February 2025Allow3821YesNo
17595704SEMICONDUCTOR DEVICE INCLUDING BASE MEMBER WITH PROTRUDING PORTION AT CIRCUMFERENTIAL EDGENovember 2021August 2024Allow3311YesNo
17455576RECESS STRUCTURE FOR PADLESS STACK VIANovember 2021December 2024Allow3620YesNo
17522376INTEGRATED CIRCUIT DEVICE WITH ANTENNA EFFECT PROTECTION CIRCUIT AND METHOD OF MANUFACTURINGNovember 2021April 2024Allow3010NoNo
17453041ELECTRONIC DEVICES INCLUDING TIERED STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES, AND RELATED SYSTEMS AND METHODSNovember 2021August 2024Allow3310NoNo
17451393SEMICONDUCTOR STRUCTUREOctober 2021March 2024Allow2910NoNo
17502140DIRECTIONAL ETCH FOR IMPROVED DUAL DECK THREE-DIMENSIONAL NAND ARCHITECTURE MARGINOctober 2021June 2024Allow3211YesNo
17450504DOUBLE GATE THIN FILM TRANSISTOR DEVICE WITH MIXED SEMICONDUCTOR LAYERSOctober 2021May 2025Allow4340YesNo
17496185THREE-DIMENSIONAL CAPACITIVE STRUCTURES AND THEIR MANUFACTURING METHODSOctober 2021January 2024Allow2800YesNo
17602138PIXEL, DISPLAY DEVICE INCLUDING SAME, AND MANUFACTURING METHOD THEREFOROctober 2021April 2024Allow3110NoNo
17449414DISPLAY APPARATUSSeptember 2021January 2024Allow2700NoNo
17448892SEMICONDUCTOR STRUCTURE WITH CONDUCTIVE PLUG AND CAPACITOR ARRAYSeptember 2021April 2024Allow3010NoNo
17442382ELECTRONIC ELEMENT HOUSING PACKAGE AND ELECTRONIC APPARATUSSeptember 2021September 2024Allow3610YesNo
17441738DISPLAY DEVICE, DISPLAY PANEL AND FABRICATION METHOD THEREOFSeptember 2021November 2024Allow3820NoNo
17476140NANOSHEET DEVICE ARCHITECTURE FOR CELL-HEIGHT SCALINGSeptember 2021June 2024Allow3311YesNo
17463022SEMICONDUCTOR DEVICE SEGMENTED INTERCONNECTAugust 2021February 2024Allow3011NoNo
17434712DISPLAY SUBSTRATE, SPLICED DISPLAY PANEL AND DISPLAY APPARATUSAugust 2021May 2024Allow3310NoNo
17408485Semiconductor Device Including Three-Dimensional Inductor Structure and Method of Forming the SameAugust 2021May 2024Allow3221NoNo
17402416INSPECTION DEVICE, RESIN MOLDING APPARATUS, AND METHOD OF MANUFACTURING RESIN MOLDED PRODUCTAugust 2021September 2024Abandon3720NoNo
17427805FLEXIBLE INTERPOSERAugust 2021August 2024Allow3760YesNo
17444026STRUCTURE FORMATION IN A SEMICONDUCTOR DEVICEJuly 2021April 2024Allow3220YesNo
17348882DISPLAY PANEL AND FABRICATING METHOD THEREOF, AND DISPLAYING DEVICEJune 2021January 2025Allow4311NoNo
17414113SURFACE SHIELDING ASSEMBLY FOR LED PACKAGEJune 2021December 2024Abandon4210NoNo
17347447PHOTOELECTRIC CONVERSION DEVICEJune 2021January 2025Allow4310YesNo
17347147DISPLAY DEVICE HAVING BANK AND A LIGHT EMITTING ELEMENT IN AN OPENINGJune 2021January 2025Allow4311NoNo
17347411DISPLAY DEVICE AND MANUFACTURING METHOD THEREOFJune 2021January 2025Allow4311NoNo
17312934GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAMEJune 2021January 2025Allow4430YesNo
17299901IMAGING DEVICE HAVING A PLURALITY OF IN-LAYER LENSES WITH CORRESPONDING ON-CHIP LENSESJune 2021April 2025Allow4750YesNo
17332782DISPLAY DEVICEMay 2021December 2024Allow4321YesNo
17327027CHIP HEAT DISSIPATING STRUCTURE, CHIP STRUCTURE, CIRCUIT BOARD AND SUPERCOMPUTING DEVICEMay 2021August 2024Allow3820YesNo
17187179SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFFebruary 2021February 2024Allow3510NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner ASSOUMAN, HERVE-LOUIS Y.

Strategic Value of Filing an Appeal

Total Appeal Filings
1
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
1
(100.0%)
Filing Benefit Percentile
4.7%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner ASSOUMAN, HERVE-LOUIS Y - Prosecution Strategy Guide

Executive Summary

Examiner ASSOUMAN, HERVE-LOUIS Y works in Art Unit 2812 and has examined 137 patent applications in our dataset. With an allowance rate of 98.5%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 30 months.

Allowance Patterns

Examiner ASSOUMAN, HERVE-LOUIS Y's allowance rate of 98.5% places them in the 96% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by ASSOUMAN, HERVE-LOUIS Y receive 1.36 office actions before reaching final disposition. This places the examiner in the 28% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by ASSOUMAN, HERVE-LOUIS Y is 30 months. This places the examiner in the 42% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +2.0% benefit to allowance rate for applications examined by ASSOUMAN, HERVE-LOUIS Y. This interview benefit is in the 19% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 43.1% of applications are subsequently allowed. This success rate is in the 94% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 39.3% of cases where such amendments are filed. This entry rate is in the 52% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 91% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 33.3% are granted (fully or in part). This grant rate is in the 27% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 21% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 27% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.