USPTO Examiner SEDOROOK DAVID PAUL - Art Unit 2812

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18768561METHOD FOR FORMING SEMICONDUCTOR STRUCTUREJuly 2024May 2025Allow1000NoNo
18510736MEMORY DEVICE WITH VERTICALLY STACKED SEMICONDUCTOR STRUCTURESNovember 2023April 2025Allow1710YesNo
18373291HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FORMING THE SAME USING THE METAL GATE LAYER AND SPACER AS AN ETCH MASKSeptember 2023April 2025Allow1931NoNo
18365435Asymmetric Source/Drain for Backside Source ContactAugust 2023March 2025Allow1920YesNo
17797218Reverse Conducting Power Semiconductor Device and Method for Manufacturing the SameAugust 2022June 2025Allow3410NoNo
17764430METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT COMPRISING A MASK, TRANSVERAL EPITAXIAL GROWTH, AND PEELINGMarch 2022April 2025Abandon3620NoNo
17677152LIGHT EMITTING SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING A PLURALITY OF LIGHT EMITTING SEMICONDUCTOR CHIPSFebruary 2022January 2025Abandon3501NoNo
17671604IMPACT-RESISTANT MICROMECHANICAL ARMSFebruary 2022June 2025Allow4021NoNo
17578569Ni(Al)O P-TYPE SEMICONDUCTOR VIA SELECTIVE OXIDATION OF NiAl AND METHODS OF FORMING THE SAMEJanuary 2022February 2024Allow2510YesNo
17571149RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAMEJanuary 2022February 2025Allow3721YesNo
17647086FORMING PASSIVATION STACK HAVING ETCH STOP LAYERJanuary 2022July 2024Allow3030YesNo
17556224DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, DISPLAY APPARATUS AND SPLICING DISPLAY APPARATUSDecember 2021June 2025Allow4220NoNo
17553772MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAMEDecember 2021April 2025Allow4030YesNo
17549523Organic Light Emitting Display Device that Detects Moisture by Emitting Light Responsive to Ultraviolet Light IrradiationDecember 2021February 2025Allow3820YesNo
17526321PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE INVOLVING THE REPLACEMENT OF DIELECTRIC LAYER WITH GATENovember 2021April 2025Allow4130NoNo
17515782TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORYNovember 2021June 2025Allow4431YesNo
17516310STRETCHABLE DISPLAY DEVICE WITH CONNECTION LINES IN DIFFERENT DIRECTIONS BETWEEN PIXELSNovember 2021May 2025Allow4330YesNo
17513948HIGH VOLTAGE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFOctober 2021August 2024Allow3430YesNo
17502708CONTAMINATED INTERFACE MITIGATION IN A SEMICONDUCTOR DEVICEOctober 2021February 2025Allow4021YesNo
17503077PAD STRUCTURES FOR SEMICONDUCTOR DEVICESOctober 2021July 2025Allow4541YesNo
17502044DISPLAY DEVICE HAVING SURFACE CONTROL LAYER IN TRANSMISSION AREAOctober 2021May 2025Allow4330NoNo
17599580DISPLAY PANEL AND DISPLAY DEVICE THAT INCLUDE AN ANNULAR REPAIR CIRCUITSeptember 2021November 2024Allow3810NoNo
17599587MASK AND METHOD FOR MANUFACTURING SAME, DISPLAY PANEL, AND DISPLAY DEVICESeptember 2021May 2025Allow4420NoNo
17599268TERMINAL DEVICE AND DISPLAY SCREEN THEREOF, AND PREPARATION METHOD FOR DISPLAY SCREENSeptember 2021May 2025Allow4430NoNo
17436058SEMICONDUCTOR DEVICE THAT COMPRISES AN HEMT AND AN HHMT WITH A BACKSIDE CONTACT ELECTRODE AND THE MANUFACTURING METHOD THEREOFSeptember 2021April 2025Allow4320NoNo
17458672A Nano-FET Transistor with Alternating Nanostructures and Method of Forming ThereofAugust 2021October 2024Allow3830YesNo
17410410ELECTRONIC DEVICE COMPRISNG A MICRO-LENS AND PHOTODIODE ARRAY WITH AMORPHIC N-TYPE AND P-TYPE LAYERSAugust 2021January 2025Allow4130YesNo
17433231Epitaxial Wafer of Red Light-Emitting Diode, and Preparation Method ThereforAugust 2021May 2024Abandon3310NoNo
17405517IMAGE SENSOR COMPRISING A GRID PATTERN AND A CONDUCTIVE PATTERNAugust 2021March 2024Allow3110YesNo
17400712Method for Forming a Semiconductor Structure Having a Porous Semiconductor Layer in RF DevicesAugust 2021April 2025Allow4471NoNo
17426736IMAGING DEVICE AND IMAGING SYSTEMJuly 2021May 2024Abandon3410NoNo
17386575DYNAMIC RANDOM ACCESS MEMORY DEVICE WITH ACTIVE REGIONS OF DIFFERENT PROFILE ROUGHNESS AND METHOD FOR FORMING THE SAMEJuly 2021March 2025Allow4331NoNo
17382001Interconnect Structure Including Graphite and Method Forming SameJuly 2021February 2025Allow4341NoNo
17419348DISPLAY PANEL AND DISPLAY DEVICE WITH NANOCRYSTALLINE PARTICLES THAT IMPROVE THE LIGHT INTENSITIES OF THE LIGHT-EMITTING AREASJune 2021March 2025Allow4530NoNo
17419305Display Substrate with Stepped Wire Configuration, Dummy Rectangle Units and Display Apparatus, and Manufacturing Method ThereofJune 2021March 2025Allow4520NoNo
17418744TWO STEP PHOSPHOR DEPOSITION TO MAKE A MATRIX ARRAYJune 2021May 2025Allow4740YesNo
17353051OHMIC ELECTRODE FOR TWO-DIMENSIONAL CARRIER GAS (2DCG) SEMICONDUCTOR DEVICEJune 2021June 2024Allow3620YesNo
17344478Semiconductor Device with Backside Power Rail and Method for Forming the SameJune 2021July 2024Allow3821YesNo
17333045HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FORMING THE SAMEMay 2021August 2024Allow3930YesNo
17308678Asymmetric Source/Drain for Backside Source ContactMay 2021November 2024Allow4331YesNo
17237249METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH FINS USING A MULTILAYER MASK STRUCTURE FOR ETCHING TO FORM NANOSTRUCTURESApril 2021May 2024Allow3630YesNo
17231895Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells Including Forming A Pair Of Elevationally-Extending Walls That Are Laterally-Spaced Relative One Another And That Are Individually Horizontally-Longitudinally-ElongatedApril 2021September 2024Allow4141YesNo
17220072METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICEApril 2021October 2024Abandon4240NoNo
17217348POWER DEVICE ASSEMBLIES AND COOLING DEVICES FOR COOLING HEAT- GENERATING DEVICESMarch 2021April 2024Allow3620YesNo
17211739PIXEL OF A LIGHT SENSOR AND METHOD FOR MANUFACTURING SAMEMarch 2021November 2024Allow4331YesNo
17205213METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH MEMORY DEVICEMarch 2021February 2024Allow3431NoNo
17193053Light Emitting Diode Devices With Patterned TCO Layer Including Different ThicknessesMarch 2021May 2024Allow3841NoNo
17273459OPTOELECTRONIC SEMICONDUCTOR DEVICE HAVING A SUPPORT ELEMENT AND AN ELECTRIC CONTACT ELEMENT, AN OPTOELECTRONIC COMPONENT AND A METHOD OF PRODUCING THE OPTOELECTRONIC SEMICONDUCTOR DEVICEMarch 2021May 2024Abandon3810NoNo
17273721SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOFMarch 2021March 2025Abandon4820NoNo
17272825LIGHT-EMITTING DEVICE AND DISPLAY DEVICE INCLUDING BANK STRUCTURES COMPRISED OF COLOR FILTER MATERIALMarch 2021March 2025Allow4930YesNo
17270969ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICEFebruary 2021June 2024Allow4010NoNo
17249247CONTACT PADS OF THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOFFebruary 2021June 2024Allow4020YesNo
17165593SEMICONDUCTOR DEVICE INCLUDING BONDING STRUCTURES AND CHIP GUARDSFebruary 2021July 2024Allow4140YesNo
17162515LIGHT EMITTING DIODE STRUCTURE WITH INDIVIDUAL FUCTIONABLE LED UNITS AND METHOD FOR MANUFACTURING THE SAMEJanuary 2021December 2024Allow4640YesNo
17158888MICROELECTRONIC DEVICES WITH VERTICALLY RECESSED CHANNEL STRUCTURES AND DISCRETE, SPACED INTER-SLIT STRUCTURES, AND RELATED METHODS AND SYSTEMSJanuary 2021March 2025Allow4941NoYes
17158259Integrated Assemblies and Methods of Forming Integrated AssembliesJanuary 2021April 2025Allow5171YesNo
17153100LED UNIT, LED DISPLAY, AND MANUFACTURING METHOD INVOLVING ASSEMBLY FLUID AND GUIDING PLATE ASSEMBLYJanuary 2021August 2024Abandon4320YesNo
17250415IMAGING ELEMENT AND ELECTRONIC APPARATUS INCLUDING A STEPPED STRUCTUREJanuary 2021May 2024Allow4010NoNo
17250349LIGHT-RECEIVING ELEMENT AND DISTANCE-MEASURING MODULEJanuary 2021April 2024Abandon3910NoNo
17258621LIGHT-EMITTING DEVICE COMPRISING BANKS AND ELECTRODES THEREON, AND DISPLAY DEVICE COMPRISING SAMEJanuary 2021August 2024Allow4320YesNo
17117337LATERAL GATE MATERIAL ARRANGEMENTS FOR QUANTUM DOT DEVICESDecember 2020October 2024Allow4620YesNo
16949924PIXEL ARRAY INCLUDING OCTAGON PIXEL SENSORSNovember 2020February 2024Allow3940YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner SEDOROOK, DAVID PAUL.

Strategic Value of Filing an Appeal

Total Appeal Filings
1
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
1
(100.0%)
Filing Benefit Percentile
4.7%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner SEDOROOK, DAVID PAUL - Prosecution Strategy Guide

Executive Summary

Examiner SEDOROOK, DAVID PAUL works in Art Unit 2812 and has examined 61 patent applications in our dataset. With an allowance rate of 85.2%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 40 months.

Allowance Patterns

Examiner SEDOROOK, DAVID PAUL's allowance rate of 85.2% places them in the 56% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by SEDOROOK, DAVID PAUL receive 2.59 office actions before reaching final disposition. This places the examiner in the 87% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by SEDOROOK, DAVID PAUL is 40 months. This places the examiner in the 8% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.

Interview Effectiveness

Conducting an examiner interview provides a +25.5% benefit to allowance rate for applications examined by SEDOROOK, DAVID PAUL. This interview benefit is in the 76% percentile among all examiners. Recommendation: Interviews are highly effective with this examiner and should be strongly considered as a prosecution strategy. Per MPEP § 713.10, interviews are available at any time before the Notice of Allowance is mailed or jurisdiction transfers to the PTAB.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 36.9% of applications are subsequently allowed. This success rate is in the 80% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 30.2% of cases where such amendments are filed. This entry rate is in the 35% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 91% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 100.0% are granted (fully or in part). This grant rate is in the 96% percentile among all examiners. Strategic Note: Petitions are frequently granted regarding this examiner's actions compared to other examiners. Per MPEP § 1002.02(c), various examiner actions are petitionable to the Technology Center Director, including prematureness of final rejection, refusal to enter amendments, and requirement for information. If you believe an examiner action is improper, consider filing a petition.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 22% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 28% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.
  • Prioritize examiner interviews: Interviews are highly effective with this examiner. Request an interview after the first office action to clarify issues and potentially expedite allowance.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Plan for extended prosecution: Applications take longer than average with this examiner. Factor this into your continuation strategy and client communications.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.