USPTO Examiner PATEL REEMA - Art Unit 2812

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18865498METHOD FOR TRANSFERRING A LAYER FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATENovember 2024May 2025Allow610NoNo
18766944DISPLAY DEVICEJuly 2024April 2025Allow910NoNo
18767291SEMICONDUCTOR DEVICES WITH MODIFIED SOURCE/DRAIN FEATURE AND METHODS THEREOFJuly 2024August 2025Allow1420YesNo
18761585PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERNJuly 2024July 2025Allow1211NoNo
18755342MULTI-GATE DEVICE AND RELATED METHODSJune 2024March 2025Allow801NoNo
18749899SEMICONDUCTOR STRUCTURE WITH AIR GAP IN PATTERN-DENSE REGION AND METHOD OF MANUFACTURING THE SAMEJune 2024January 2025Allow710NoNo
18739140SILVER PATTERNING AND INTERCONNECT PROCESSESJune 2024December 2024Allow600NoNo
18737600IMAGE SENSOR DEVICE AND METHODS OF FORMING THE SAMEJune 2024March 2025Allow1010NoNo
18733564GATE STRUCTURES AND SPACERS IN SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFJune 2024July 2025Allow1311NoNo
18676465SEMICONDUCTOR STRUCTURES OF ANTI-FUSE DEVICES AND CORE DEVICES WITH DIFFERENT DIELECTRIC LAYERSMay 2024April 2025Allow1120NoNo
18662267CUPROUS OXIDE DEVICES AND FORMATION METHODSMay 2024April 2025Allow1110NoNo
18656610BACKSIDE ILLUMINATED IMAGE SENSOR AND MANUFACTURING METHOD THEREOFMay 2024March 2025Allow1010NoNo
18645678SEMICONDUCTOR COMPONENT ARRANGEMENT, METHOD FOR FABRICATION THEREOF AND HEAT DISSIPATION DEVICEApril 2024September 2025Allow1710NoNo
18645181REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGESApril 2024November 2024Allow700NoNo
18631560SWITCHING ELEMENTApril 2024March 2025Allow1110NoNo
18586925SURFACE MODIFICATION LAYER FOR CONDUCTIVE FEATURE FORMATIONFebruary 2024March 2025Allow1210NoNo
18585660DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMEFebruary 2024January 2025Allow1110NoNo
18438047METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEFebruary 2024January 2025Allow1110NoNo
18431112SEMICONDUCTOR DEVICESFebruary 2024March 2025Allow1341NoNo
18426794SAG NANOWIRE GROWTH WITH A PLANARIZATION PROCESSJanuary 2024December 2024Allow1110NoNo
18424800LIGHT-EMITTING DEVICE AND DISPLAY DEVICE USING THE SAMEJanuary 2024February 2025Allow1311NoNo
18417984SINGLE CRYSTAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAMEJanuary 2024February 2025Allow1311YesNo
18407025SEMICONDUCTOR DEVICE WITH A POROUS PORTION, WAFER COMPOSITE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEJanuary 2024May 2025Allow1621YesNo
18405159SEMICONDUCTOR DEVICE HAVING IMPROVED ELECTROSTATIC DISCHARGE PROTECTIONJanuary 2024October 2024Allow1001NoNo
18397293NANOSHEET TRANSISTORDecember 2023April 2025Allow1510NoNo
18543745DISPLAY DEVICEDecember 2023March 2026Allow2600NoNo
18569607SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEDecember 2023March 2026Allow2700NoNo
18534537DISPLAY DEVICE INCLUDING A FLEXIBLE SUBSTRATEDecember 2023October 2024Allow1010NoNo
18513624SEMICONDUCTOR DEVICE AND FABRICATION METHODNovember 2023December 2024Allow1211NoNo
18505563Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory CellsNovember 2023July 2025Allow2021NoNo
18504307SEMICONDUCTOR DEVICENovember 2023February 2026Allow2700NoNo
18386346Integrated Assemblies and Methods of Forming Integrated AssembliesNovember 2023September 2024Allow1011NoNo
18383158SEMICONDUCTOR STRUCTURE WITH AIR GAP IN PATTERN-DENSE REGION AND METHOD OF MANUFACTURING THE SAMEOctober 2023September 2024Allow1111NoNo
18480378FORMATION OF SINGLE CRYSTAL SEMICONDUCTORS USING PLANAR VAPOR LIQUID SOLID EPITAXYOctober 2023December 2024Allow1411NoNo
18471730SEMICONDUCTOR DEVICESeptember 2023December 2025Allow2700NoNo
18369321HARDMASK STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR STRUCTURESeptember 2023March 2026Allow3010NoNo
18452581CHANNEL STRUCTURES INCLUDING DOPED 2D MATERIALS FOR SEMICONDUCTOR DEVICESAugust 2023November 2024Allow1511YesNo
18547151Method For Fabricating Semiconductor StructuresAugust 2023November 2025Allow2700NoNo
18234678SEMICONDUCTOR INTEGRATED CIRCUIT DEVICEAugust 2023June 2025Allow2210NoNo
18232881METHOD FOR MANUFACTURING METAL OXYNITRIDE FILMAugust 2023January 2025Allow1711NoNo
18447927SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKINGAugust 2023July 2024Allow1101NoNo
18446681Seam-Filling of Metal Gates with Si-Containing LayersAugust 2023August 2024Allow1210NoNo
18446151MULTIGATE DEVICE WITH AIR GAP SPACER AND BACKSIDE RAIL CONTACT AND METHOD OF FABRICATING THEREOFAugust 2023January 2025Allow1720NoNo
18231486NANOSTRUCTURED CHANNEL REGIONS FOR SEMICONDUCTOR DEVICESAugust 2023September 2024Allow1411YesNo
18366392MULTI-GATE DEVICE AND RELATED METHODSAugust 2023March 2025Allow1930NoNo
18365995NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIALAugust 2023August 2024Allow1210NoNo
18365680IMAGE SENSOR DEVICE AND METHODS OF FORMING THE SAMEAugust 2023March 2024Allow800YesNo
18365402METHOD FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATEAugust 2023August 2024Allow1210YesNo
18365405Local Gate Height Tuning by CMP and Dummy Gate DesignAugust 2023October 2024Allow1521NoNo
18363692SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAMEAugust 2023September 2024Allow1311NoNo
18362240STRAIN RELIEF TRENCHES FOR EPITAXIAL GROWTHJuly 2023December 2025Allow2941YesNo
18361262PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTSJuly 2023January 2025Allow1811NoNo
18358530PASSIVATION SCHEME DESIGN FOR WAFER SINGULATIONJuly 2023November 2024Allow1511NoNo
18358689SEMICONDUCTOR CHIPJuly 2023May 2024Allow910NoNo
18225994CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAMEJuly 2023August 2024Abandon1310NoNo
18220963SEMICONDUCTOR STRUCTURE WITH AIR GAP IN PATTERN-DENSE REGION AND METHOD OF MANUFACTURING THE SAMEJuly 2023October 2025Allow2710NoNo
18221358HYBRID BONDING CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICEJuly 2023June 2024Allow1211NoNo
18219986GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINSJuly 2023September 2024Allow1411NoNo
18347778DISPLAY DEVICEJuly 2023April 2024Allow910NoNo
18345266MEMORY DEVICEJune 2023January 2026Allow3110NoNo
18211502SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTIONJune 2023March 2026Allow3310NoNo
18327785SILVER PATTERNING AND INTERCONNECT PROCESSESJune 2023February 2024Allow901NoNo
18204259PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERNMay 2023March 2024Allow1010NoNo
18324314HIGH-FREQUENCY MODULE AND COMMUNICATION DEVICEMay 2023December 2025Allow3010NoNo
18144648ELECTROLUMINESCENCE DISPLAYMay 2023February 2026Allow3311NoNo
18311220SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAMEMay 2023March 2026Allow3401NoNo
18141552BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONSMay 2023February 2026Allow3411NoNo
18303557SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFApril 2023March 2025Allow2331YesNo
18032276DISPLAY DEVICE INCLUDING SELF-ALIGNED LEDS AND METHOD FOR MANUFACTURING DISPLAY DEVICEApril 2023January 2026Allow3310NoNo
18132868METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEApril 2023November 2023Allow700YesNo
18131486SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF RECYCLING SUBSTRATEApril 2023July 2024Allow1520NoNo
18125859SEMICONDUCTOR STRUCTURE HAVING FIN STRUCTURESMarch 2023February 2024Allow1120NoNo
18246398PIXEL STRUCTURE AND METHOD FOR MANUFACTURING A PIXEL STRUCTUREMarch 2023January 2026Abandon3410NoNo
18188399MULTI-PATTERN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAMEMarch 2023October 2025Allow3110YesNo
18122783CMOS STRUCTURE, AND FABRICATION METHODS OF FINFET CMOS, FD CMOS AND GAA CMOSMarch 2023March 2026Allow3611NoNo
17598893SEMICONDUCTOR DEVICE HAVING IMPROVED P-TYPE DOPED NITRIDE-BASED SEMICONDUCTOR LAYER AND METHOD FOR MANUFACTURING THE SAMEMarch 2023October 2025Allow4910NoNo
18026494LIGHT EMITTING PANEL AND MANUFACTURING METHOD THEREOF, AND LIGHT EMITTING APPARATUSMarch 2023September 2025Allow3010NoNo
18179408CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEMarch 2023January 2026Allow3411NoNo
18178948Surface Modification Layer for Conductive Feature FormationMarch 2023November 2023Allow810NoNo
18024296SEMICONDUCTOR DEVICE INCLUDING A SILICON SEMICONDUCTOR LAYER AND A NITRIDE SEMICONDUCTOR LAYERMarch 2023September 2025Allow3110NoNo
18113686SELF-ALIGNED SUBSTRATE ISOLATION (SASI) OF GATE-ALL-AROUND NANOSHEET FIELD EFFECT TRANSISTORSFebruary 2023March 2026Allow3711YesNo
18113385Ultrafast Laser Annealing of Thin FilmsFebruary 2023December 2023Abandon1010NoNo
18112853CARRIER STRUCTURE AND METHODS OF FORMING THE SAMEFebruary 2023December 2025Allow3411NoNo
18112916LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAMEFebruary 2023February 2024Allow1110NoNo
18171508EPITAXIAL FORMATION WITH TREATMENT AND SEMICONDUCTOR DEVICES RESULTING THEREFROMFebruary 2023December 2025Allow3411NoNo
18170411SILICON LAYER-BASED SILICIDE CONTACTSFebruary 2023November 2025Allow3311YesNo
18104836METHOD FOR MANUFACTURING FOR FORMING SOURCE/DRAIN CONTACT FEATURES AND DEVICES MANUFACTURED THEREOFFebruary 2023November 2025Allow3411NoNo
18163785SEMICONDUCTOR STRUCTURE INCLUDING GATE SPACER LAYER AND DIELECTRIC LAYER HAVING PORTION LOWER THAN TOP SURFACE OF GATE SPACER LAYERFebruary 2023December 2025Allow3411NoNo
18158750DISPLAY DEVICE INCLUDING A FLEXIBLE SUBSTRATEJanuary 2023August 2023Allow710NoNo
18098633N/P-INDEPENDENTLY STRAINED POST-REPLACEMENT METAL GATE (RMG) GATE CUT FOR PERFORMANCE ENHANCED FINFETJanuary 2023January 2026Allow3621YesNo
18016411CHIP HEAT SINK AND NUCLEIC ACID EXTRACTION DEVICEJanuary 2023May 2025Allow2800NoNo
18005608PACKAGE SUBSTRATE MANUFACTURING METHODJanuary 2023September 2025Allow3210NoNo
18016177COMPOUND SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR SUBSTRATEJanuary 2023August 2025Allow3210NoNo
18096791PIN DIODE INCLUDING A CONDUCTIVE LAYER, AND FABRICATION PROCESSJanuary 2023December 2023Abandon1111NoNo
18093861DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAMEJanuary 2023November 2023Allow1111NoNo
18150861Volume-less Fluorine Incorporation MethodJanuary 2023November 2025Allow3411NoNo
18090872THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAMEDecember 2022January 2026Allow3721NoNo
18148056OPTICAL SENSOR DEVICEDecember 2022August 2025Allow3110NoNo
18146886SYSTEM, ELECTRONIC DEVICE AND PACKAGE WITH VERTICAL TO HORIZONTAL SUBSTRATE INTEGRATED WAVEGUIDE TRANSITION AND HORIZONTAL GROUNDED COPLANAR WAVEGUIDE TRANSITIONDecember 2022August 2025Allow3200NoNo
18068992COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) WITH BALANCED N AND P DRIVE CURRENTDecember 2022August 2025Allow3210NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PATEL, REEMA.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
3
Examiner Affirmed
2
(66.7%)
Examiner Reversed
1
(33.3%)
Reversal Percentile
52.7%
Higher than average

What This Means

With a 33.3% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
11
Allowed After Appeal Filing
3
(27.3%)
Not Allowed After Appeal Filing
8
(72.7%)
Filing Benefit Percentile
39.8%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 27.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner PATEL, REEMA - Prosecution Strategy Guide

Executive Summary

Examiner PATEL, REEMA works in Art Unit 2812 and has examined 1,167 patent applications in our dataset. With an allowance rate of 88.0%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 21 months.

Allowance Patterns

Examiner PATEL, REEMA's allowance rate of 88.0% places them in the 68% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by PATEL, REEMA receive 1.42 office actions before reaching final disposition. This places the examiner in the 23% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PATEL, REEMA is 21 months. This places the examiner in the 91% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +6.0% benefit to allowance rate for applications examined by PATEL, REEMA. This interview benefit is in the 33% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 35.2% of applications are subsequently allowed. This success rate is in the 79% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 49.2% of cases where such amendments are filed. This entry rate is in the 74% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 66.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 55% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 70.0% of appeals filed. This is in the 56% percentile among all examiners. Of these withdrawals, 42.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 45.6% are granted (fully or in part). This grant rate is in the 39% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 3.2% of allowed cases (in the 80% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.3% of allowed cases (in the 70% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.