USPTO Art Unit 2897 Prosecution Statistics

Art Unit Information

Art Unit: 2897
Group: 2890
Tech Center: 2800
Total Cases: 13,950
Last Active: September 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19328034ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSSeptember 2025February 2026Allow510NoNo
19301777THIN FILM SEMICONDUCTOR SWITCHING DEVICEAugust 2025February 2026Allow610NoNo
19233197DISPLAY UNIT, DISPLAY MODULE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING THE DISPLAY UNITJune 2025October 2025Allow400NoNo
19200034THROUGHPUT IMPROVEMENTS FOR LOW-TEMPERATURE/BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS METHODS INCLUDING PROCESSING IN RETASKED TOOLSMay 2025July 2025Allow200NoNo
19190673LDMOS DEVICE AND FABRICATION METHOD THEREOFApril 2025June 2025Allow200NoNo
19062566HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAMEFebruary 2025August 2025Allow610NoNo
19060198THIN FILM SEMICONDUCTOR SWITCHING DEVICEFebruary 2025June 2025Allow410NoNo
19054779CHIP DEFECT MODIFYING DEVICE AND METHODFebruary 2025July 2025Allow501YesNo
19030747SEMICONDUCTOR ASSEMBLY COMPRISING A 3D BLOCK AND METHOD OF MAKING THE SAMEJanuary 2025July 2025Allow610NoNo
19013905HETEROGENEOUS ANNEALING METHOD AND DEVICEJanuary 2025September 2025Allow810YesNo
190041603D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLSDecember 2024November 2025Allow1110NoNo
19000144THROUGHPUT IMPROVEMENTS FOR LOW-TEMPERATURE/BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS METHODS INCLUDING PROCESSING IN RETASKED TOOLSDecember 2024April 2025Allow310NoNo
18986698CAPACITIVE TOUCH LED DISPLAYDecember 2024July 2025Allow720NoNo
18969220Vertical Power Semiconductor Device and Manufacturing Method ThereofDecember 2024September 2025Allow911NoNo
18967181BAFFLES FOR ELECTRONIC CIRCUITS IMMERSED IN COOLING FLUID IN A TANKDecember 2024February 2025Allow200NoNo
189636303D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERSNovember 2024June 2025Allow700NoNo
18865491METHOD FOR TRANSFERRING A LAYER FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATENovember 2024May 2025Allow610NoNo
18858306Robotic Cover SealerOctober 2024July 2025Allow901YesNo
18900415DOUBLE-SIDED INTEGRATED CIRCUIT DIE AND INTEGRATED CIRCUIT PACKAGE INCLUDING THE SAMESeptember 2024March 2025Allow510NoNo
18843295Nanoelectric System for Cooling Processors and RAM MemoriesSeptember 2024April 2025Allow810NoNo
188000573D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITSAugust 2024June 2025Allow1000NoNo
18794859METHOD OF SELECTIVE RELEASE OF COMPONENTS USING THERMAL RELEASE LAYERAugust 2024June 2025Abandon1010NoNo
18789620DISPLAY WITH SUBPIXELS ARRANGED IN DIVIDED TETRAGONJuly 2024November 2025Allow1600NoNo
18787506EMBEDDED COOLING SYSTEMS FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAMEJuly 2024March 2025Allow720NoNo
18783461Display Substrate With Central Region With Lower Pixel Density and Preparation Method Thereof, and Display ApparatusJuly 2024February 2026Allow1910NoNo
18775719SELECTIVE TRANSFER OF MICRO DEVICESJuly 2024March 2026Allow2010NoNo
18773350Display DeviceJuly 2024June 2025Allow1110NoNo
18768003SEMICONDUCTOR DEVICEJuly 2024October 2025Allow1511NoNo
18767750DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAFER BONDINGJuly 2024April 2025Allow900NoNo
18765888METHODS AND APPARATUS FOR MASK PATTERNING DEBRIS REMOVALJuly 2024July 2025Allow1210NoNo
18764973SEMICONDUCTOR DEVICESJuly 2024May 2025Allow1100NoNo
18764317SEMICONDUCTOR DEVICEJuly 2024April 2025Allow1000NoNo
18762656FABRICATING A SENSING COMPONENT ENCAPSULATED BY AN ENCAPSULATION LAYER WITH ROUGHED SURFACE HAVING A HOLLOW REGIONJuly 2024August 2025Allow1310NoNo
18763481BUMP INTEGRATION WITH REDISTRIBUTION LAYERJuly 2024March 2026Allow2010NoNo
18761522DISPLAY PANEL AND DISPLAY DEVICEJuly 2024August 2025Allow1410NoNo
18760598DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAMEJuly 2024July 2025Allow1310NoNo
18759008POWER DELIVERY FOR EMBEDDED BRIDGE DIE UTILIZING TRENCH STRUCTURESJune 2024September 2025Allow1520NoNo
18757428THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESSJune 2024March 2026Allow2021NoNo
18754195METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICEJune 2024March 2026Allow2011YesNo
18751021ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024March 2025Allow810YesNo
18751105ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024October 2024Allow400NoNo
18750260METHOD OF FORMING AN INTERMETALLIC PHASE LAYER WITH A PLURALITY OF NICKEL PARTICLESJune 2024February 2025Allow800NoNo
18750894MINI ENVIRONMENT INSTRUMENTED WAFERJune 2024November 2025Allow1710YesNo
18750571PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGEJune 2024April 2025Allow1010NoNo
18749055DETECTION DEVICE AND DISPLAY DEVICEJune 2024January 2025Allow700NoNo
18749542JOINT STRUCTURE IN SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFJune 2024March 2025Allow900NoNo
18748862CONTAMINANT COLLECTION ON SOIJune 2024October 2025Allow1610NoNo
18744975SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR PREPARING THE SAMEJune 2024February 2025Allow800NoNo
18745773SELF-ALIGNED VIA FOR INTERCONNECT STRUCTUREJune 2024June 2025Allow1210NoNo
18744728SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOFJune 2024August 2025Allow1410NoNo
18744108CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIALJune 2024January 2026Allow1920NoNo
18743810METAL INSULATOR METAL CAPACITOR STRUCTURE HAVING HIGH CAPACITANCEJune 2024July 2025Allow1310YesNo
18742517MULTI-CHIP OR MULTI-CHIPLET FAN-OUT DEVICE FOR LAMINATE AND LEADFRAME PACKAGESJune 2024June 2025Allow1230NoNo
18739329DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAMEJune 2024January 2025Allow700NoNo
18739424SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVEGUIDE AND METHOD THEREFORJune 2024February 2026Allow2011NoNo
18738281SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMSJune 2024May 2025Allow1200NoNo
18737527SEMICONDUCTOR PACKAGEJune 2024April 2025Allow1001NoNo
18736077DISPLAY DEVICEJune 2024December 2025Allow1910NoNo
18735126PACKAGE STRUCTURE INCLUDING STACKED PILLAR PORTIONS AND METHOD FOR FABRICATING THE SAMEJune 2024May 2025Allow1110NoNo
18734140WIRING STRUCTURE OF PIXEL DRIVING CIRCUIT, DISPLAY PANEL, AND DISPLAY DEVICEJune 2024August 2025Allow1411NoNo
18734765EDGE INTERFACE PLACEMENTS TO ENABLE CHIPLET ROTATION INTO MULTI-CHIPLET CLUSTERJune 2024June 2025Allow1310NoNo
18731940INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIESJune 2024January 2026Allow1920NoNo
18731643METHOD OF ETCHING OBJECT AND ETCHING DEVICEJune 2024October 2025Abandon1601NoNo
187313403D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERSJune 2024October 2024Allow500NoNo
18731337METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICEJune 2024May 2025Allow1101YesNo
18678963SEMICONDUCTOR DIES INCLUDING LOW AND HIGH WORKFUNCTION SEMICONDUCTOR DEVICESMay 2024January 2025Allow700NoNo
18678306SEMICONDUCTOR DEVICE HAVING A PASSIVATION LAYERMay 2024June 2025Allow1210NoNo
18679298ECO-EFFICIENCY (SUSTAINABILITY) DASHBOARD FOR SEMICONDUCTOR MANUFACTURINGMay 2024June 2025Allow1301YesNo
18677345LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICESMay 2024December 2024Allow720YesNo
18675406SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEMay 2024May 2025Allow1210NoNo
18675785CHIP PACKAGE STRUCTURE WITH METAL-CONTAINING LAYERMay 2024April 2025Allow1110NoNo
18674950SEMICONDUCTOR DEVICEMay 2024May 2025Allow1110NoNo
18674652METHOD OF FABRICATING A DISPLAY PANEL HAVING AT LEAST ONE LIGHT-TRANSMITTING PORTIONMay 2024June 2025Allow1200NoNo
18672820THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR, AND DISPLAY APPARATUS INCLUDING THE THIN FILM TRANSISTORMay 2024July 2025Allow1410NoNo
18671478INTERCONNECTING A PLURALITY OF DIES HAVING SPARE INPUT/OUTPUT CIRCUITMay 2024June 2025Allow1310NoNo
18670338INTEGRATED TOOL LIFTMay 2024January 2026Allow2011YesNo
18668743SEMICONDUCTOR DEVICES HAVING SUPPORTER STRUCTURESMay 2024December 2024Allow700NoNo
18669220METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICESMay 2024May 2025Allow1210NoNo
18668329ETCH STOP LAYER FOR MEMORY DEVICE FORMATIONMay 2024May 2025Allow1210NoNo
18669118SEMICONDUCTOR PACKAGEMay 2024February 2026Allow2111YesNo
18668922BUMP JOINT STRUCTURE WITH DISTORTION AND METHOD FORMING SAMEMay 2024May 2025Allow1210NoNo
18668736SYSTEM FOR BUILDING BALANCE-POINT-BASED SEASONAL FUEL CONSUMPTION FORECASTING WITH THE AID OF A DIGITAL COMPUTERMay 2024January 2025Allow810NoNo
18668038SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITSMay 2024August 2025Allow1510NoNo
18666964NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREOFMay 2024January 2026Allow2000NoNo
18666521FLEXIBLE SUBSTRATE AND FABRICATION METHOD THEREOF, AND FLEXIBLE DISPLAY APPARATUSMay 2024February 2025Allow910NoNo
18666686METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATEMay 2024June 2025Allow1301YesNo
18664386FIELD-EFFECT TRANSISTORS WITH AIRGAP SPACERSMay 2024September 2024Allow410YesNo
18664508SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREMay 2024May 2025Allow1210NoNo
18664195SEMICONDUCTOR DEVICEMay 2024October 2025Allow1700NoNo
18662749Vertically Stacked Semiconductor Device Including a Hybrid Bond Contact Junction Circuit and Methods for Forming the SameMay 2024February 2026Allow2110NoNo
18662033Electrical Discharge Machining Processing for Semiconductor WorkpieceMay 2024June 2025Allow1311YesNo
18661658DISPLAY PANEL AND DISPLAY APPARATUSMay 2024March 2025Allow1010NoNo
18660276ISOLATION STRUCTURE FOR BOND PAD STRUCTUREMay 2024June 2025Allow1310NoNo
18657689ELECTRONIC DEVICE MULTILEVEL PACKAGE SUBSTRATE FOR IMPROVED ELECTROMIGRATION PREFORMANCEMay 2024April 2025Allow1210NoNo
18655495INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAPMay 2024October 2025Allow1720NoNo
18655763Polishing Interconnect Structures In Semiconductor DevicesMay 2024August 2025Allow1610NoNo
18655382DISPLAY DEVICEMay 2024December 2024Allow700NoNo
18655932SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEMay 2024July 2025Allow1510YesNo
18655227LOW CAPACITANCE BIDIRECTIONAL TRANSIENT VOLTAGE SUPPRESSORMay 2024April 2025Allow1201YesNo
18654028SiC SEMICONDUCTOR DEVICEMay 2024July 2025Allow1500NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2897.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
79
Examiner Affirmed
50
(63.3%)
Examiner Reversed
29
(36.7%)
Reversal Percentile
69.3%
Higher than average

What This Means

With a 36.7% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
283
Allowed After Appeal Filing
115
(40.6%)
Not Allowed After Appeal Filing
168
(59.4%)
Filing Benefit Percentile
89.2%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 40.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2897 - Prosecution Statistics Summary

Executive Summary

Art Unit 2897 is part of Group 2890 in Technology Center 2800. This art unit has examined 13,950 patent applications in our dataset, with an overall allowance rate of 89.1%. Applications typically reach final disposition in approximately 21 months.

Comparative Analysis

Art Unit 2897's allowance rate of 89.1% places it in the 89% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2897 receive an average of 1.42 office actions before reaching final disposition (in the 17% percentile). The median prosecution time is 21 months (in the 94% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.