USPTO Art Unit 2897 Prosecution Statistics

Art Unit Information

Art Unit: 2897
Group: 2890
Tech Center: 2800
Total Cases: 15,504
Last Active: December 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18967181BAFFLES FOR ELECTRONIC CIRCUITS IMMERSED IN COOLING FLUID IN A TANKDecember 2024February 2025Allow200NoNo
189636303D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERSNovember 2024June 2025Allow700NoNo
18865491METHOD FOR TRANSFERRING A LAYER FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATENovember 2024May 2025Allow610NoNo
18900415DOUBLE-SIDED INTEGRATED CIRCUIT DIE AND INTEGRATED CIRCUIT PACKAGE INCLUDING THE SAMESeptember 2024March 2025Allow510NoNo
18843295Nanoelectric System for Cooling Processors and RAM MemoriesSeptember 2024April 2025Allow810NoNo
188000573D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITSAugust 2024June 2025Allow1000NoNo
18794859METHOD OF SELECTIVE RELEASE OF COMPONENTS USING THERMAL RELEASE LAYERAugust 2024June 2025Abandon1010NoNo
18773350Display DeviceJuly 2024June 2025Allow1110NoNo
18767750DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAFER BONDINGJuly 2024April 2025Allow900NoNo
18764973SEMICONDUCTOR DEVICESJuly 2024May 2025Allow1100NoNo
18764317SEMICONDUCTOR DEVICEJuly 2024April 2025Allow1000NoNo
18751021ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024March 2025Allow810YesNo
18751105ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITSJune 2024October 2024Allow400NoNo
18750260METHOD OF FORMING AN INTERMETALLIC PHASE LAYER WITH A PLURALITY OF NICKEL PARTICLESJune 2024February 2025Allow800NoNo
18750571PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGEJune 2024April 2025Allow1010NoNo
18749055DETECTION DEVICE AND DISPLAY DEVICEJune 2024January 2025Allow700NoNo
18749542JOINT STRUCTURE IN SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFJune 2024March 2025Allow900NoNo
18744975SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR PREPARING THE SAMEJune 2024February 2025Allow800NoNo
18745773SELF-ALIGNED VIA FOR INTERCONNECT STRUCTUREJune 2024June 2025Allow1210NoNo
18742517MULTI-CHIP OR MULTI-CHIPLET FAN-OUT DEVICE FOR LAMINATE AND LEADFRAME PACKAGESJune 2024June 2025Allow1230NoNo
18739329DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAMEJune 2024January 2025Allow700NoNo
18738281SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMSJune 2024May 2025Allow1200NoNo
18737527SEMICONDUCTOR PACKAGEJune 2024April 2025Allow1001NoNo
18735126PACKAGE STRUCTURE INCLUDING STACKED PILLAR PORTIONS AND METHOD FOR FABRICATING THE SAMEJune 2024May 2025Allow1110NoNo
18734765EDGE INTERFACE PLACEMENTS TO ENABLE CHIPLET ROTATION INTO MULTI-CHIPLET CLUSTERJune 2024June 2025Allow1310NoNo
187313403D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERSJune 2024October 2024Allow500NoNo
18731337METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICEJune 2024May 2025Allow1101YesNo
18678963SEMICONDUCTOR DIES INCLUDING LOW AND HIGH WORKFUNCTION SEMICONDUCTOR DEVICESMay 2024January 2025Allow700NoNo
18678306SEMICONDUCTOR DEVICE HAVING A PASSIVATION LAYERMay 2024June 2025Allow1210NoNo
18679298ECO-EFFICIENCY (SUSTAINABILITY) DASHBOARD FOR SEMICONDUCTOR MANUFACTURINGMay 2024June 2025Allow1301YesNo
18677345LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICESMay 2024December 2024Allow710YesNo
18675406SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEMay 2024May 2025Allow1210NoNo
18675785CHIP PACKAGE STRUCTURE WITH METAL-CONTAINING LAYERMay 2024April 2025Allow1110NoNo
18674950SEMICONDUCTOR DEVICEMay 2024May 2025Allow1110NoNo
18674652METHOD OF FABRICATING A DISPLAY PANEL HAVING AT LEAST ONE LIGHT-TRANSMITTING PORTIONMay 2024June 2025Allow1200NoNo
18671478SYSTEMS AND METHODS FOR INTERCONNECTING DIESMay 2024June 2025Allow1310NoNo
18668743SEMICONDUCTOR DEVICES HAVING SUPPORTER STRUCTURESMay 2024December 2024Allow700NoNo
18669220METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICESMay 2024May 2025Allow1210NoNo
18668329ETCH STOP LAYER FOR MEMORY DEVICE FORMATIONMay 2024May 2025Allow1210NoNo
18668922BUMP JOINT STRUCTURE WITH DISTORTION AND METHOD FORMING SAMEMay 2024May 2025Allow1210NoNo
18668736SYSTEM FOR BUILDING BALANCE-POINT-BASED SEASONAL FUEL CONSUMPTION FORECASTING WITH THE AID OF A DIGITAL COMPUTERMay 2024January 2025Allow810NoNo
18666521FLEXIBLE SUBSTRATE AND FABRICATION METHOD THEREOF, AND FLEXIBLE DISPLAY APPARATUSMay 2024February 2025Allow910NoNo
18666686METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATEMay 2024June 2025Allow1301YesNo
18664386FIELD-EFFECT TRANSISTORS WITH AIRGAP SPACERSMay 2024September 2024Allow410YesNo
18664508SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREMay 2024May 2025Allow1210NoNo
18661658DISPLAY PANEL AND DISPLAY APPARATUSMay 2024March 2025Allow1010NoNo
18660276ISOLATION STRUCTURE FOR BOND PAD STRUCTUREMay 2024June 2025Allow1310NoNo
18657689ELECTRONIC DEVICE MULTILEVEL PACKAGE SUBSTRATE FOR IMPROVED ELECTROMIGRATION PREFORMANCEMay 2024April 2025Allow1210NoNo
18655382DISPLAY DEVICEMay 2024December 2024Allow700NoNo
18655227LOW CAPACITANCE BIDIRECTIONAL TRANSIENT VOLTAGE SUPPRESSORMay 2024April 2025Allow1201YesNo
18653511Array SubstrateMay 2024April 2025Allow1110NoNo
18649389CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERSApril 2024January 2025Allow800NoNo
18648781METAL-OXIDE-SEMICONDUCTOR CAPACITOR BASED PASSIVE AMPLIFIERApril 2024May 2025Allow1210NoNo
18645786SEMICONDUCTOR PACKAGE STRUCTUREApril 2024May 2025Allow1301NoNo
18644098METHOD OF MANUFACTURING A DISPLAY APPARATUSApril 2024March 2025Allow1110NoNo
18643409DISPLAY PANEL AND DISPLAY DEVICE WITH REDUCED DISPERSIONApril 2024March 2025Allow1110NoNo
18642280METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM)April 2024January 2025Abandon810NoNo
18642784DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAMEApril 2024November 2024Allow700NoNo
18641492DISPLAY DEVICEApril 2024May 2025Allow1301YesNo
18640682MEMORY DEVICE WITH LOW DENSITY THERMAL BARRIERApril 2024June 2025Allow1410YesNo
18637737SEMICONDUCTOR DEVICE WITH COMPOSITE MIDDLE INTERCONNECTORSApril 2024June 2025Allow1411NoNo
18635387SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE CONTACTS OF DIFFERENT WIDTHS AND METHOD FOR PREPARING THE SAMEApril 2024December 2024Allow800NoNo
18634621SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOFApril 2024April 2025Allow1210NoNo
18634558PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAMEApril 2024March 2025Allow1110NoNo
18634809METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMSApril 2024April 2025Allow1200NoNo
18634628METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATEApril 2024December 2024Allow800NoNo
18632919DIRECT BONDING IN MICROELECTRONIC ASSEMBLIESApril 2024April 2025Allow1210NoNo
18632494LED PACKAGING STRUCTUREApril 2024September 2024Allow510NoNo
18633172DISPLAY PANEL HAVING INITIALIZATION LINES AND DISPLAY APPARATUS INCLUDING THE SAMEApril 2024March 2025Allow1110NoNo
18632047PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROLApril 2024March 2025Allow1110NoNo
18629670PACKAGE BONDING STRUCTURES AND METHOD OF FORMATIONApril 2024June 2025Allow1510NoNo
18622472DYNAMIC PRECURSOR DOSING FOR ATOMIC LAYER DEPOSITIONMarch 2024June 2025Allow1410NoNo
18622796DISPLAY DEVICE HAVING CONDUCTIVE PATTERNS WITH REDUCED DISPLAY ELEMENT OVERLAPMarch 2024June 2025Allow1511NoNo
18620753INTEGRATED COOLING ASSEMBLY INCLUDING COOLANT CHANNEL ON THE BACKSIDE SEMICONDUCTOR DEVICEMarch 2024August 2024Allow500NoNo
18620327METHOD FOR SEPARATING DIES FROM A SEMICONDUCTOR SUBSTRATEMarch 2024August 2024Allow410NoNo
18618058CAPACITOR ELEMENT, MODULE, AND SEMICONDUCTOR COMPOSITE DEVICEMarch 2024December 2024Allow900NoNo
18618432FLIP-CHIP SEMICONDUCTOR-ON-INSULATOR TRANSISTOR LAYOUTMarch 2024March 2025Allow1210NoNo
18615867DISPLAY DEVICE INCLUDING AN ENCAPSULATION STRUCTUREMarch 2024February 2025Allow1110YesNo
18614310EMBEDDED METAL LINESMarch 2024September 2024Allow600NoNo
18609908AMORPHOUS LAYERS FOR REDUCING COPPER DIFFUSION AND METHOD FORMING SAMEMarch 2024February 2025Allow1100NoNo
18608940HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATING METHOD OF THE SAMEMarch 2024February 2025Allow1110NoNo
18607630DISPLAY DEVICEMarch 2024March 2025Allow1110NoNo
18607569DISPLAY DEVICEMarch 2024January 2025Allow1010NoNo
18607339MEMORY DEVICES WITH BACKSIDE BOND PADS UNDER A MEMORY ARRAYMarch 2024March 2025Allow1210NoNo
18606765EXTRINSIC FIELD TERMINATION STRUCTURES FOR IMPROVING RELIABILITY OF HIGH-VOLTAGE, HIGH-POWER ACTIVE DEVICESMarch 2024November 2024Allow810NoNo
18606876CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONSMarch 2024January 2025Allow1010NoNo
18604542BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAMEMarch 2024May 2025Allow1410NoNo
18604627DEVICE INTEGRATION SCHEMES LEVERAGING A BULK SEMICONDUCTOR SUBSTRATE HAVING A <111> CRYSTAL ORIENTATIONMarch 2024June 2025Allow1510NoNo
18604127METHOD AND APPARATUS FOR COATING PHOTO RESIST OVER A SUBSTRATEMarch 2024March 2025Allow1201YesNo
18603483SEMICONDUCTOR DEVICE STRUCTURESMarch 2024March 2025Allow1210YesNo
18602533INFO PACKAGES INCLUDING THERMAL DISSIPATION BLOCKSMarch 2024March 2025Allow1210NoNo
18601003SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFMarch 2024June 2025Allow1510NoNo
18600278MITIGATING SURFACE DAMAGE OF PROBE PADS IN PREPARATION FOR DIRECT BONDING OF A SUBSTRATEMarch 2024July 2025Allow1620YesNo
18594703DEVICE FOR CONTROLLING TRAPPED IONSMarch 2024April 2025Allow1310NoNo
18594011METHOD OF FORMING ELECTRICAL FUSE MATRIXMarch 2024May 2025Allow1400NoNo
18594560DISPLAY DEVICEMarch 2024September 2024Allow700NoNo
18595049INTEGRATED CIRCUIT DEVICE WITH IMPROVED LAYOUTMarch 2024January 2025Allow1010NoNo
18594262DYNAMIC 3D OBJECT RECOGNITION AND PRINTINGMarch 2024April 2025Allow1301YesNo
18594816SEMICONDUCTOR DEVICEMarch 2024September 2024Allow700NoNo
18593536INTEGRATED CIRCUIT PACKAGE AND METHODMarch 2024January 2025Allow1110NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2897.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
71
Examiner Affirmed
45
(63.4%)
Examiner Reversed
26
(36.6%)
Reversal Percentile
69.6%
Higher than average

What This Means

With a 36.6% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
269
Allowed After Appeal Filing
109
(40.5%)
Not Allowed After Appeal Filing
160
(59.5%)
Filing Benefit Percentile
85.6%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 40.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2897 - Prosecution Statistics Summary

Executive Summary

Art Unit 2897 is part of Group 2890 in Technology Center 2800. This art unit has examined 15,504 patent applications in our dataset, with an overall allowance rate of 90.1%. Applications typically reach final disposition in approximately 21 months.

Comparative Analysis

Art Unit 2897's allowance rate of 90.1% places it in the 90% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2897 receive an average of 1.35 office actions before reaching final disposition (in the 15% percentile). The median prosecution time is 21 months (in the 92% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.