USPTO Examiner BRADFORD PETER - Art Unit 2897

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18789620DISPLAY WITH SUBPIXELS ARRANGED IN DIVIDED TETRAGONJuly 2024November 2025Allow1600NoNo
18783461Display Substrate With Central Region With Lower Pixel Density and Preparation Method Thereof, and Display ApparatusJuly 2024February 2026Allow1910NoNo
18640528NONVOLATILE MEMORY WITH VERTICAL CONTACT THROUGH MEMORY STACKApril 2024September 2025Allow1710YesNo
18640682MEMORY DEVICE WITH LOW DENSITY THERMAL BARRIERApril 2024June 2025Allow1410YesNo
18622472DYNAMIC PRECURSOR DOSING FOR ATOMIC LAYER DEPOSITIONMarch 2024June 2025Allow1410NoNo
18401722ELECTRONIC DEVICEJanuary 2024August 2025Abandon1920YesNo
18545278METHOD OF DETERMINING THE SPREAD OF AN ORGANIC LAYER IN AN OLEDDecember 2023January 2025Allow1310YesNo
18540249Display Device with Protrusion on Inclined Side of BankDecember 2023September 2024Allow910NoNo
18387080DISPLAY DEVICE HAVING A SEALING FILM COVERING A CATHODENovember 2023September 2024Allow1010NoNo
18366353METHOD OF FORMING MEMORY TRANSISTOR WITH SACRIFICIAL POLYSILICON LAYERAugust 2023November 2024Allow1510NoNo
18230281DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAMEAugust 2023April 2024Allow800NoNo
18200579MICROLED CONNECTION WITH CU BUMP ON TI/AL WIREMay 2023December 2025Allow3101NoNo
18320373PIXEL WITH RING SHAPE AROUND AN ISLAND, ARRAY SUBSTRATE AND DISPLAY APPARATUSMay 2023December 2025Allow3131YesNo
18195593DISPLAY PANEL INCLUDING INORGANIC LAYER WITH OPENINGS IN NON-DISPLAY AREA, AND DISPLAY TERMINALMay 2023January 2026Allow3310NoNo
18303948METHOD OF MANUFACTURING OLED WITH SELF-ASSEMBLED MATERIAL ON PIXEL ELECTRODEApril 2023November 2025Abandon3140YesNo
18247407METHOD OF MANUFACTURING OLED USING SOLVENTS WITH DIFFERENT VAPOR PRESSURESMarch 2023February 2026Allow3410NoNo
18185825OLED PIXEL WITH APERTURE PROPORTIONAL TO CAPACITANCEMarch 2023January 2025Allow2220YesNo
18176626DISPLAY WITH TFTMarch 2023May 2024Allow1420YesNo
18175556DISPLAY WITH TWO STACKED PIXEL DEFINITION LAYERSFebruary 2023February 2026Allow3520YesNo
18023381Display Substrate with Isolation Groove Disposed Between Pixels and Display ApparatusFebruary 2023October 2025Allow3210YesNo
18174180ORGANIC LIGHT-EMITTING DISPLAY APPARATUS WITH FOCUS LENSFebruary 2023April 2024Allow1410NoNo
18168655DISPLAY DEVICE HAVING ORGANIC LAYERS AND AN ELECTRODE LOCATED UNDER A RIBFebruary 2023October 2025Allow3210YesNo
18164686OLED WITH A FLATTENING LAYER BETWEEN TWO BARRIER LAYERSFebruary 2023February 2024Allow1210NoNo
18102917METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOWJanuary 2023March 2024Allow1420NoNo
18090530OLED WITH A RIB AND A PARTITION BETWEEN SUBPIXELSDecember 2022January 2026Allow3710NoNo
17980004SEMICONDUCTOR PACKAGE HAVING A LEAD FRAME AND A CLIP FRAMENovember 2022January 2025Abandon2610NoNo
17977301Integrated Circuit Package and MethodOctober 2022May 2025Allow3012YesNo
17976867LIGHTING DEVICE WITH LIGHT PARTIALLY COVERED BY LIGHT ADJUSTING LAYER AND METHOD FOR MAKINGOctober 2022September 2023Allow1110NoNo
17961092DISPLAY DEVICE COMPRISING A DISPLAY PANEL HAVING INSULATING LAYERS OVER A PAD AND METHOD OF PROVIDING THE DISPLAY PANELOctober 2022December 2025Allow3811YesNo
17932888OLED WITH MESH METAL LAYER IN FLEXIBLE SUBSTRATESeptember 2022April 2025Allow3131NoNo
17909419ARRAY SUBSTRATE WITH SYMMETRICAL SUBPIXELGROUPS, DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE ARRAY SUBSTRATESeptember 2022August 2025Allow3510NoNo
17896546SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYERS IN ISOLATION STRUCTURESAugust 2022December 2025Allow3910YesNo
17892705DISPLAY DEVICE WITH COLOR FILTER OVER NONEMITTING REFLECTIVE AREAAugust 2022February 2026Allow4211YesNo
17887768SEMICONDUCTOR ISOLATION BRIDGE FOR THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORYAugust 2022February 2026Allow4220NoNo
17884687DEEP TRENCH ISOLATION STRUCTURE AND METHOD OF MAKING THE SAMEAugust 2022December 2024Allow2821YesNo
17880614UV LED WITH ELECTRODE WITH IRREGULAR SURFACEAugust 2022March 2025Allow3111NoNo
17878893METHOD OF DIFFUSING NITROGEN INTO A TUNNEL LAYER OF A NONVOLATILE MEMORYAugust 2022April 2023Allow910NoNo
17872276METHOD OF FORMING DEEP TRENCH ISOLATION IN RADIATION SENSING SUBSTRATE AND IMAGE SENSOR DEVICEJuly 2022October 2025Allow3921NoNo
17809535METHODS FOR FORMING MULTILAYER HORIZONTAL NOR-TYPE THIN-FILM MEMORY STRINGSJune 2022January 2025Allow3120NoNo
17788030DEVICE FORMED BY EPITAXIAL GROWTH FROM THE SIDE SURFACE OF A STEPJune 2022June 2025Allow3610NoNo
17845586ELECTROLUMINESCENT DISPLAY DEVICE WITH BANK BETWEEN SAME COLOR SUB-PIXELSJune 2022March 2024Allow2120YesNo
17805131STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICEJune 2022May 2024Allow2401NoNo
17828849METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHODMay 2022September 2024Abandon2810NoNo
17751849INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITHOUT PARASITIC CHANNELSMay 2022August 2023Allow1410NoNo
17750887SEMICONDUCTOR DEVICE WITH SELF-ALIGNED VIASMay 2022January 2025Allow3101NoNo
17748363Hybrid Integrated Circuit Dies and Methods of Forming the SameMay 2022February 2025Allow3312NoNo
17745903MEMORY DEVICE WITH SOURCE LINE OVER A BONDING PADMay 2022October 2025Allow4111YesNo
17661642VERTICAL ETCH HETEROLITHIC INTEGRATED CIRCUIT DEVICESMay 2022November 2023Allow1920YesNo
17729363FILM STRUCTURE FOR BOND PADApril 2022November 2024Allow3120YesNo
17725890DEVICE CRACK-STOP STRUCTURE TO PREVENT DAMAGE DUE TO DICING CRACKApril 2022April 2024Allow2412NoNo
17724746SOLID-STATE IMAGING DEVICE, WITH TRANSFER TRANSISTOR GATE ELECTRODE HAVING TRENCH GATE SECTIONSApril 2022April 2024Allow2411NoNo
17721791DISPLAY PANEL WITH OPENINGS IN CORNERS, DISPLAY DEVICE INCLUDING THE DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE DISPLAY DEVICEApril 2022October 2025Allow4210YesNo
17721023Array Substrate, Method of Fabricating Array Substrate, Display Panel, and Method of Fabricating Display PanelApril 2022April 2023Allow1210NoNo
17721088METHOD FOR FORMING MEMORY PATTERNS AND WIRE PATTERNS SIMULTANEOUSLYApril 2022October 2025Allow4311NoNo
17718561SEMICONDUCTOR ELEMENT MEMORY DEVICEApril 2022June 2025Abandon3910NoNo
17716259PIEZOELECTRIC ACCOUSTIC SENSOR WITH MULTIPLE VIBRATING AREASApril 2022January 2026Allow4521YesNo
17715033LIGHTING DEVICE WITH CONNECTION TO ELEMENT ELECTRODES USING FILLERApril 2022March 2025Allow3511NoNo
17713913Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory CellsApril 2022April 2025Allow3711NoNo
17710564FERROELECTRIC MEMORY WITH MULTIPLE FERROELETRIC LAYERS THROUGH A STACK OF GATE LINESMarch 2022October 2025Allow4311NoNo
17657000FLEXIBLE DISPLAY INCLUDING LAYER WITHIN GROOVE OR OPENING OF FLEXIBLE SUBSTRATEMarch 2022January 2025Allow3430NoNo
17656002ELECTRODES OF SEMICONDUCTOR MEMORY DEVICES HAVING CORNERS OF ACUTE ANGLESMarch 2022October 2025Allow4311NoNo
17655589VARIABLE RESISTANCE MEMORY DEVICE HAVING AN ANTI-OXIDATION LAYER AND A METHOD OF MANUFACTURING THE SAMEMarch 2022March 2023Allow1210YesNo
17694402High Resolution Profile Measurement Based On A Trained Parameter Conditioned Measurement ModelMarch 2022September 2025Allow4310NoNo
17654773CROSS-POINT MAGNETORESISTIVE RANDOM MEMORY ARRAY AND METHOD OF MAKING THEREOF USING SELF-ALIGNED PATTERNINGMarch 2022June 2025Allow3911NoNo
17694613AN OLED MASK WITH END PORTIONED CORNERSMarch 2022January 2024Allow2230YesNo
17641519LASER PROCESSING DEVICE FOR FORMING A MODIFIED REGION IN AN OBJECT AND LASER PROCESSING METHODMarch 2022November 2024Allow3210NoNo
17640899METHOD OF DESIGNING AN ALIGNMENT MARKMarch 2022November 2024Allow3210YesNo
17640814ALIGNMENT METHOD FOR BACKSIDE PHOTOLITHOGRAPHY PROCESSMarch 2022May 2025Allow3820YesNo
17686485DISPLAY WITH TFT HAVING A TWO-LAYER GATE INSULATORMarch 2022November 2025Allow4421NoNo
17653428METHOD OF ETCHING A MEMORY STACK BY ETCHING A BLIND HOLEMarch 2022December 2024Allow3410NoNo
17685436SEMICONDUCTOR DEVICE WITH DEPRESSION IN PACKAGE AND METHOD FOR MANUFACTURING SAMEMarch 2022October 2024Allow3110NoNo
17682210SUBSTRATE PROCESSING APPARATUS, FURNACE OPENING ASSEMBLY, SUBSTRATE PROCESSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY TANGIBLE MEDIUMFebruary 2022April 2025Allow3811NoNo
17677078SPIN-ORBIT TORQUE DEVICE AND MANUFACTURING METHOD THEREOFFebruary 2022June 2025Allow4021YesNo
17675838SEMICONDUCTOR DEVICE WITH A VERTICAL CHANNEL WRAPPED AROUND GATE, AND METHOD FOR MANUFACTURING THE SAMEFebruary 2022June 2025Allow4011NoNo
17670999SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEFebruary 2022December 2024Allow3421YesNo
17668473OLED WITH CAPACITOR ELECTRODE ON BANKFebruary 2022May 2025Allow3911NoNo
17591262DISPLAY PANEL AND DISPLAY APPARATUS WITH PIXEL CIRCUITS BEHIND LIGHT BLOCKING ASSEMBLYFebruary 2022December 2024Allow3410NoNo
17590561METHOD OF MAKING MAGNETORESISTIVE MEMORY CELL OVER A SELECTOR PILLARFebruary 2022May 2023Allow1510NoNo
17590501DISPLAY DEVICE WITH DISCONNECTED CHARGE GENERATION REGIONSFebruary 2022September 2025Allow4321YesNo
17586049SEMICONDUCTOR DEVICE WITH LOW POTENTIAL TERMINALS CONNECTED TO WELLSJanuary 2022June 2025Allow4030YesNo
17585405SEMICONDUCTOR DEVICE WITH TEST PATTERN STRUCTURESJanuary 2022June 2025Allow4121YesNo
17579732OLED INCLUDING ORGANIC LAYERS INCLUDING OVERLAPPING EDGESJanuary 2022July 2025Allow4221NoNo
17597593MODULATION OF OXIDATION PROFILE FOR SUBSTRATE PROCESSINGJanuary 2022April 2024Allow2700NoNo
17626434DISPLAY SUBSTRATE WITH SPACERS ON CATHODE POWER LINE AND DISPLAY APPARATUSJanuary 2022February 2025Allow3720YesNo
17572360High Voltage Gallium Nitride Vertical PN DiodeJanuary 2022December 2024Allow3510YesNo
17563214FINFET STACK GATE MEMORY AND METHOD OF FORMING THEREOFDecember 2021January 2023Allow1310NoNo
17563275NON-VOLATILE MEMORY DEVICES WITH DUMMY CHANNEL STRUCTURES IN CONTACT REGION AND ASSOCIATED SYSTEMSDecember 2021August 2025Allow4421YesNo
17622458EPITAXIAL GROWTH APPARATUS AND METHOD OF PRODUCING EPITAXIAL WAFERDecember 2021September 2024Allow3210NoNo
17622071DISPLAY PANEL CONTAINING SUB-PIXEL IN THE SHAPE OF RIGHT ANGLE WITH EQUAL SIDES AND METHOD FOR PREPARING THE SAMEDecember 2021March 2025Allow3920NoNo
17540916INTERFACE CIRCUIT AND DIFFERENTIAL INTERFACE CIRCUIT WITH INTEGRATED COMPLEMENTARY SENSORSDecember 2021June 2025Allow4211NoNo
17528128Methods Used in Fabricating Integrated Circuitry and Methods of Forming 2T-1C Memory Cell ArraysNovember 2021December 2023Allow2520YesNo
17611646MIRROR CIRCUIT DEVICES WITH WIDE WIRINGSNovember 2021January 2025Allow3810NoNo
17522702RETROSYNTHESIS PROCESSING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUMNovember 2021March 2024Allow2801NoNo
17521017MAGNETORESISTIVE STACK/STRUCTURE WITH ONE OR MORE TRANSITION METALS IN AN INSERTION LAYER FOR A MEMORY AND METHODS THEREFORNovember 2021February 2024Allow2821YesNo
17519340SOLID-STATE IMAGING DEVICE WITH ORGANIC PHOTOELECTRIC CONVERSION FILM OVER PHOTODIODESNovember 2021April 2024Allow3040NoNo
17512645Display Substrate with Pixel Define Layer within Color SubpixelOctober 2021September 2024Allow3531NoNo
17510283DISPLAY WITH OVERLAPPING CONDUCTIVE LINES HAVING A BRIDGE PORTIONOctober 2021February 2025Allow3911NoNo
17451534DYNAMIC PRECURSOR DOSING FOR ATOMIC LAYER DEPOSITIONOctober 2021December 2023Allow2620YesNo
17500462DISPLAY DEVICE WITH ROW OF LEDS BETWEEN BANKSOctober 2021December 2024Allow3811NoNo
17498247DEPOSITION OF METAL FILMS WITH TUNGSTEN LINEROctober 2021February 2024Allow2830YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BRADFORD, PETER.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
7
Examiner Affirmed
4
(57.1%)
Examiner Reversed
3
(42.9%)
Reversal Percentile
65.9%
Higher than average

What This Means

With a 42.9% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
13
Allowed After Appeal Filing
7
(53.8%)
Not Allowed After Appeal Filing
6
(46.2%)
Filing Benefit Percentile
85.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 53.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner BRADFORD, PETER - Prosecution Strategy Guide

Executive Summary

Examiner BRADFORD, PETER works in Art Unit 2897 and has examined 689 patent applications in our dataset. With an allowance rate of 81.6%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 27 months.

Allowance Patterns

Examiner BRADFORD, PETER's allowance rate of 81.6% places them in the 53% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by BRADFORD, PETER receive 2.03 office actions before reaching final disposition. This places the examiner in the 53% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by BRADFORD, PETER is 27 months. This places the examiner in the 73% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +3.4% benefit to allowance rate for applications examined by BRADFORD, PETER. This interview benefit is in the 26% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 28.8% of applications are subsequently allowed. This success rate is in the 53% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 27.5% of cases where such amendments are filed. This entry rate is in the 39% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 33.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 33% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 53.3% of appeals filed. This is in the 24% percentile among all examiners. Of these withdrawals, 12.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.

Petition Practice

When applicants file petitions regarding this examiner's actions, 51.1% are granted (fully or in part). This grant rate is in the 50% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.9% of allowed cases (in the 66% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 3.6% of allowed cases (in the 76% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.