Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 19301777 | THIN FILM SEMICONDUCTOR SWITCHING DEVICE | August 2025 | February 2026 | Allow | 6 | 1 | 0 | No | No |
| 19062566 | HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAME | February 2025 | August 2025 | Allow | 6 | 1 | 0 | No | No |
| 19060198 | THIN FILM SEMICONDUCTOR SWITCHING DEVICE | February 2025 | June 2025 | Allow | 4 | 1 | 0 | No | No |
| 19004160 | 3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS | December 2024 | November 2025 | Allow | 11 | 1 | 0 | No | No |
| 18963630 | 3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS | November 2024 | June 2025 | Allow | 7 | 0 | 0 | No | No |
| 18900415 | DOUBLE-SIDED INTEGRATED CIRCUIT DIE AND INTEGRATED CIRCUIT PACKAGE INCLUDING THE SAME | September 2024 | March 2025 | Allow | 5 | 1 | 0 | No | No |
| 18787506 | EMBEDDED COOLING SYSTEMS FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAME | July 2024 | March 2025 | Allow | 7 | 2 | 0 | No | No |
| 18767750 | DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAFER BONDING | July 2024 | April 2025 | Allow | 9 | 0 | 0 | No | No |
| 18731340 | 3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS | June 2024 | October 2024 | Allow | 5 | 0 | 0 | No | No |
| 18662749 | Vertically Stacked Semiconductor Device Including a Hybrid Bond Contact Junction Circuit and Methods for Forming the Same | May 2024 | February 2026 | Allow | 21 | 1 | 0 | No | No |
| 18650225 | SEMICONDUCTOR PACKAGES WITH STACKED DIES AND METHODS OF FORMING THE SAME | April 2024 | February 2026 | Allow | 21 | 1 | 0 | Yes | No |
| 18643753 | 4CPP SRAM CELL AND ARRAY | April 2024 | September 2025 | Allow | 16 | 1 | 0 | No | No |
| 18617013 | DISPLAY SUBSTRATE AND RELATED DEVICES WITH IMPROVED RESOLUTION | March 2024 | July 2025 | Allow | 16 | 1 | 0 | No | No |
| 18615528 | SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | March 2024 | July 2025 | Allow | 15 | 1 | 0 | No | No |
| 18610263 | SEMICONDUCTOR INTERCONNECT STRUCTURES WITH VERTICALLY OFFSET BONDING SURFACES, AND ASSOCIATED SYSTEMS AND METHODS | March 2024 | July 2025 | Allow | 16 | 1 | 0 | No | No |
| 18607339 | MEMORY DEVICES WITH BACKSIDE BOND PADS UNDER A MEMORY ARRAY | March 2024 | March 2025 | Allow | 12 | 1 | 0 | No | No |
| 18604542 | BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAME | March 2024 | May 2025 | Allow | 14 | 1 | 0 | No | No |
| 18604627 | DEVICE INTEGRATION SCHEMES LEVERAGING A BULK SEMICONDUCTOR SUBSTRATE HAVING A <111> CRYSTAL ORIENTATION | March 2024 | June 2025 | Allow | 15 | 1 | 0 | No | No |
| 18594703 | DEVICE FOR CONTROLLING TRAPPED IONS | March 2024 | April 2025 | Allow | 13 | 1 | 0 | No | No |
| 18440623 | SEMICONDUCTOR MEMORY HAVING MEMORY CELL REGIONS AND OTHER REGIONS ALTERNATELY ARRANGED ALONG A BIT LINE DIRECTION | February 2024 | May 2025 | Allow | 15 | 1 | 0 | No | No |
| 18431177 | 3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS | February 2024 | May 2024 | Allow | 3 | 0 | 0 | No | No |
| 18429477 | SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE | February 2024 | February 2025 | Allow | 12 | 1 | 0 | No | No |
| 18418964 | STACKED-CHIP PACKAGES | January 2024 | December 2024 | Allow | 11 | 1 | 0 | No | No |
| 18406018 | INTERCONNECT ARCHITECTURE WITH SILICON INTERPOSER AND EMIB | January 2024 | March 2025 | Allow | 14 | 1 | 0 | No | No |
| 18400497 | SEMICONDUCTOR PACKAGE | December 2023 | October 2024 | Allow | 9 | 0 | 0 | No | No |
| 18390395 | STANDALONE ISOLATION CAPACITOR | December 2023 | March 2025 | Allow | 14 | 1 | 0 | No | No |
| 18536332 | SEMICONDUCTOR PACKAGES | December 2023 | February 2025 | Allow | 14 | 1 | 0 | No | No |
| 18536254 | ELECTRONIC DEVICE INCLUDING CONDUCTIVE ELEMENT ON SIDE SURFACE OF SUBSTRATE | December 2023 | January 2025 | Allow | 13 | 1 | 0 | No | No |
| 18518591 | SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME | November 2023 | January 2025 | Allow | 14 | 0 | 0 | No | No |
| 18517774 | CHIPLETS 3D SOIC SYSTEM INTEGRATION AND FABRICATION METHODS | November 2023 | January 2025 | Allow | 14 | 0 | 0 | No | No |
| 18388840 | 3D MEMORY DEVICES AND STRUCTURES WITH METAL LAYERS | November 2023 | January 2024 | Allow | 2 | 0 | 0 | No | No |
| 18381911 | SEMICONDUCTOR PACKAGE STRUCTURE HAVING MULTIPLE BONDING PADS | October 2023 | October 2024 | Allow | 12 | 1 | 0 | No | No |
| 18489016 | SEMICONDUCTOR STRUCTURE INCLUDING THERMAL ENHANCED BONDING STRUCTURE | October 2023 | November 2024 | Allow | 13 | 1 | 0 | No | No |
| 18489557 | SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | October 2023 | April 2025 | Allow | 18 | 1 | 0 | No | No |
| 18488741 | FIELD-EFFECT TRANSISTOR, AND METHODS FOR PRODUCTION | October 2023 | February 2026 | Allow | 28 | 0 | 0 | No | No |
| 18380863 | SYSTEMS AND METHODS FOR DIRECT BONDING IN SEMICONDUCTOR DIE MANUFACTURING | October 2023 | October 2024 | Allow | 12 | 1 | 0 | No | No |
| 18487247 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR PACKAGES | October 2023 | January 2025 | Allow | 15 | 0 | 0 | No | No |
| 18485318 | SEMICONDUCTOR PACKAGE WITH PLURALITY OF LEADS AND SEALING RESIN | October 2023 | May 2025 | Allow | 19 | 1 | 0 | No | No |
| 18377530 | SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP | October 2023 | May 2024 | Allow | 7 | 0 | 0 | No | No |
| 18469637 | DISPLAY DEVICE | September 2023 | February 2026 | Allow | 29 | 0 | 0 | No | No |
| 18469910 | THREE DIMENSIONAL CIRCUIT IMPLEMENTING MACHINE TRAINED NETWORK | September 2023 | November 2024 | Allow | 14 | 1 | 0 | No | No |
| 18243726 | SEMICONDUCTOR DEVICES | September 2023 | February 2026 | Allow | 29 | 0 | 0 | No | No |
| 18460203 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE | September 2023 | January 2026 | Allow | 29 | 0 | 0 | No | No |
| 18459628 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | September 2023 | August 2024 | Allow | 12 | 0 | 0 | No | No |
| 18459440 | HIGH FREQUENCY MODULE AND COMMUNICATION APPARATUS | September 2023 | January 2026 | Allow | 28 | 0 | 0 | No | No |
| 18239368 | Backside Integrated Voltage Regulator For Integrated Circuits | August 2023 | April 2025 | Allow | 20 | 1 | 0 | No | No |
| 18239117 | 3D MEMORY DEVICES AND STRUCTURES WITH CONTROL CIRCUITS | August 2023 | October 2023 | Allow | 2 | 0 | 0 | No | No |
| 18455960 | HIGH-SPEED DIE CONNECTIONS USING A CONDUCTIVE INSERT | August 2023 | October 2024 | Allow | 14 | 1 | 0 | No | No |
| 18454189 | DISPLAY MODULE AND AN ELECTRONIC DEVICE INCLUDING THE SAME | August 2023 | December 2025 | Allow | 28 | 0 | 0 | No | No |
| 18236858 | CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE | August 2023 | March 2024 | Allow | 7 | 0 | 0 | No | No |
| 18228139 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING | July 2023 | September 2024 | Allow | 13 | 1 | 0 | No | No |
| 18358186 | BACKSIDE CONTACT TO IMPROVE THERMAL DISSIPATION AWAY FROM SEMICONDUCTOR DEVICES | July 2023 | October 2024 | Allow | 15 | 1 | 0 | No | No |
| 18357818 | BONDING STRUCTURE AND METHOD OF FORMING SAME | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18357350 | BOND PAD WITH ENHANCED RELIABILITY | July 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18356289 | SEMICONDUCTOR PACKAGE | July 2023 | November 2025 | Allow | 28 | 0 | 0 | No | No |
| 18356808 | Deep Partition Power Delivery with Deep Trench Capacitor | July 2023 | April 2024 | Allow | 8 | 0 | 0 | No | No |
| 18356224 | PACKAGE HAVING DIFFERENT METAL DENSITIES IN DIFFERENT REGIONS AND MANUFACTURING METHOD THEREOF | July 2023 | July 2024 | Allow | 12 | 1 | 0 | No | No |
| 18353167 | SEMICONDUCTOR PACKAGE INCLUDING PADS | July 2023 | November 2025 | Allow | 28 | 0 | 0 | No | No |
| 18348170 | STACKED LAYERS WITH FILLING STRUCTURES | July 2023 | March 2026 | Allow | 32 | 1 | 0 | No | No |
| 18346396 | WAFER-LEVEL BONDING OF OBSTRUCTIVE ELEMENTS | July 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18346550 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME | July 2023 | January 2024 | Allow | 7 | 0 | 0 | No | No |
| 18213952 | BIDIRECTIONAL SWITCHING DEVICES, ITS TERMINAL STRUCTURES, AND ELECTRONIC DEVICES | June 2023 | September 2025 | Allow | 27 | 0 | 0 | No | No |
| 18211561 | A DEVICE STRUCTURE WITH A REDISTRIBUTION LAYER AND A BUFFER LAYER | June 2023 | June 2024 | Allow | 12 | 1 | 0 | No | No |
| 18335578 | COPPER-BONDED MEMORY STACKS WITH COPPER-BONDED INTERCONNECTION MEMORY SYSTEMS | June 2023 | July 2024 | Allow | 14 | 1 | 0 | No | No |
| 18207378 | MULTI-DIE PHYSICALLY UNCLONABLE FUNCTION ENTROPY SOURCE | June 2023 | October 2025 | Allow | 28 | 0 | 0 | No | No |
| 18206040 | 3D DRAM MEMORY DEVICES AND STRUCTURES WITH CONTROL CIRCUITS | June 2023 | August 2023 | Allow | 2 | 0 | 0 | No | No |
| 18205329 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | June 2023 | August 2025 | Allow | 27 | 0 | 0 | No | No |
| 18320791 | BONDING LAYER AND PROCESS | May 2023 | December 2025 | Allow | 31 | 1 | 0 | No | No |
| 18198163 | DISPLAY APPARATUS THAT INCLUDES CONCAVO-CONVEX STRUCTURE ON UPPER SURFACE OF PIXEL DEFINING LAYER AND METHOD OF MANUFACTURING THE SAME | May 2023 | April 2024 | Allow | 11 | 1 | 0 | No | No |
| 18197607 | Flip-Chip Packaged Power Transistor Module Having Built-in Gate Driver | May 2023 | August 2025 | Allow | 27 | 0 | 0 | No | No |
| 18252891 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | May 2023 | February 2026 | Allow | 33 | 1 | 0 | No | No |
| 18195096 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | May 2023 | June 2024 | Allow | 13 | 2 | 0 | No | No |
| 18144744 | DISPLAY DEVICE | May 2023 | February 2026 | Allow | 33 | 1 | 0 | No | No |
| 18311712 | STRUCTURE INCLUDING PASSIVE COMPONENT TRAVERSING MULTIPLE SEMICONDUCTOR CHIPS, WITH RELATED METHODS AND SYSTEMS | May 2023 | March 2026 | Allow | 34 | 1 | 0 | No | No |
| 18309678 | SEMICONDUCTOR DEVICES WITH HYBRID BONDING LAYERS AND PROCESS OF MAKING THE SAME | April 2023 | February 2026 | Allow | 34 | 1 | 0 | Yes | No |
| 18307165 | CAP LAYER FOR PAD OXIDATION PREVENTION | April 2023 | March 2026 | Allow | 34 | 1 | 0 | No | No |
| 18138270 | DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAFER BONDING | April 2023 | April 2024 | Allow | 12 | 1 | 0 | No | No |
| 18304834 | ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT AND TRANSISTOR CONNECTED IN SERIES | April 2023 | December 2023 | Allow | 8 | 0 | 0 | No | No |
| 18304591 | SEMICONDUCTOR DEVICE INCLUDING MOLDED DIE STACK AND METHODS OF FORMING THE SAME | April 2023 | February 2026 | Allow | 34 | 1 | 0 | No | No |
| 18302106 | INTERCONNECT STRUCTURES FOR IMPROVED LIGHT-EMITTING DIODE CHIP PERFORMANCE | April 2023 | January 2026 | Allow | 33 | 1 | 0 | No | No |
| 18297012 | SEMICONDUCTOR DEVICE INCLUDING TWO OR MORE SEMICONDUCTOR STRUCTURES THAT ARE STACKED ONE ON ANOTHER AND METHOD FOR FABRICATING THE SAME | April 2023 | February 2026 | Allow | 35 | 1 | 0 | No | No |
| 18297266 | SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME | April 2023 | February 2026 | Allow | 34 | 1 | 0 | Yes | No |
| 18126893 | STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTS AND METHOD OF MAKING THE SAME | March 2023 | March 2024 | Allow | 12 | 1 | 0 | No | No |
| 18126761 | SRAM DEVICE AND 3D SEMICONDUCTOR INTEGRATED CIRCUIT THEREOF | March 2023 | July 2025 | Allow | 28 | 0 | 0 | No | No |
| 18124771 | BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAME | March 2023 | December 2023 | Allow | 9 | 0 | 0 | No | No |
| 18181731 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PAD | March 2023 | December 2025 | Allow | 33 | 1 | 0 | Yes | No |
| 18112810 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME | February 2023 | November 2025 | Allow | 33 | 1 | 0 | Yes | No |
| 18111287 | SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS | February 2023 | January 2026 | Allow | 35 | 1 | 0 | No | No |
| 18108935 | SEMICONDUCTOR INTERCONNECT STRUCTURES WITH VERTICALLY OFFSET BONDING SURFACES, AND ASSOCIATED SYSTEMS AND METHODS | February 2023 | November 2023 | Allow | 9 | 1 | 0 | No | No |
| 18103346 | SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | January 2023 | July 2023 | Allow | 6 | 0 | 0 | No | No |
| 18157335 | ORGANIC LIGHT-EMITTING DEVICE INCLUDING A FIRST EXCIPLEX AND A SECOND EXCIPLEX IN AN EMISSION LAYER | January 2023 | March 2024 | Allow | 14 | 1 | 0 | No | No |
| 18098726 | INTERCONNECTION STRUCTURE OF SYSTEM ON WAFER AND PCB BASE ON TSV PROCESS AND METHOD FOR MANUFACTURING THE SAME | January 2023 | April 2023 | Allow | 3 | 0 | 0 | No | No |
| 18156022 | NANOGAP STRUCTURE AND METHOD OF MANUFACTURING NANOGAP STRUCTURE THROUGH UNDERCUT | January 2023 | May 2025 | Allow | 28 | 0 | 0 | No | No |
| 18015669 | THREE-DIMENSIONAL FLASH MEMORY WITH HIGH DEGREE OF INTEGRATION | January 2023 | December 2025 | Allow | 35 | 1 | 0 | No | No |
| 18015427 | LED DISPLAY MODULE AND LED DISPLAY DEVICE | January 2023 | October 2025 | Allow | 33 | 1 | 0 | No | No |
| 18152740 | SEMICONDUCTOR STRUCTURE WITH VERTICAL CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF | January 2023 | February 2026 | Allow | 37 | 1 | 0 | Yes | No |
| 18093880 | SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP | January 2023 | July 2023 | Allow | 6 | 0 | 0 | No | No |
| 18014009 | WAFER BONDING STRUCTURE, WAFER BONDING METHOD AND CHIP BONDING STRUCTURE | December 2022 | October 2025 | Allow | 33 | 1 | 0 | No | No |
| 18087384 | HETEROGENEOUS INTEGRATION STRUCTURE WITH VOLTAGE REGULATION | December 2022 | December 2025 | Allow | 35 | 1 | 0 | No | No |
| 18086172 | MULTI SENSOR RADIO FREQUENCY DETECTION | December 2022 | July 2023 | Allow | 7 | 0 | 0 | No | No |
No appeal data available for this record. This may indicate that no appeals have been filed or decided for applications in this dataset.
Examiner DIALLO, MAMADOU L works in Art Unit 2897 and has examined 163 patent applications in our dataset. With an allowance rate of 98.2%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 27 months.
Examiner DIALLO, MAMADOU L's allowance rate of 98.2% places them in the 91% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by DIALLO, MAMADOU L receive 0.99 office actions before reaching final disposition. This places the examiner in the 8% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by DIALLO, MAMADOU L is 27 months. This places the examiner in the 73% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.
Conducting an examiner interview provides a +2.1% benefit to allowance rate for applications examined by DIALLO, MAMADOU L. This interview benefit is in the 22% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 38.1% of applications are subsequently allowed. This success rate is in the 87% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 76.9% of cases where such amendments are filed. This entry rate is in the 95% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.
When applicants file petitions regarding this examiner's actions, 62.5% are granted (fully or in part). This grant rate is in the 67% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 8.6% of allowed cases (in the 92% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.5% of allowed cases (in the 71% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.