USPTO Examiner KUSUMAKAR KAREN M - Art Unit 2897

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18731940INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIESJune 2024January 2026Allow1920NoNo
18675406SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEMay 2024May 2025Allow1210NoNo
18668329ETCH STOP LAYER FOR MEMORY DEVICE FORMATIONMay 2024May 2025Allow1210NoNo
18668038SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITSMay 2024August 2025Allow1510NoNo
18664508SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREMay 2024May 2025Allow1210NoNo
18655495INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAPMay 2024October 2025Allow1720NoNo
18655763Polishing Interconnect Structures In Semiconductor DevicesMay 2024August 2025Allow1610NoNo
18635387SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE CONTACTS OF DIFFERENT WIDTHS AND METHOD FOR PREPARING THE SAMEApril 2024December 2024Allow800NoNo
18634628METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATEApril 2024December 2024Allow800NoNo
18634809METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMSApril 2024April 2025Allow1200NoNo
18618058CAPACITOR ELEMENT, MODULE, AND SEMICONDUCTOR COMPOSITE DEVICEMarch 2024December 2024Allow900NoNo
18609908AMORPHOUS LAYERS FOR REDUCING COPPER DIFFUSION AND METHOD FORMING SAMEMarch 2024February 2025Allow1100NoNo
18417555SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUMJanuary 2024November 2024Allow1000NoNo
18407517PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIAJanuary 2024September 2025Allow2020YesNo
18402992HEAT DISSIPATION FOR FIELD EFFECT TRANSISTORSJanuary 2024March 2026Allow2600NoNo
18401988THREE-DIMENSIONAL MEMORY DEVICE AND METHODJanuary 2024August 2025Allow2020NoNo
18400680MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMSDecember 2023January 2025Allow1310NoNo
18395126SUBTRACTIVE PLUG AND TAB PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) SPACER-BASED INTERCONNECTSDecember 2023August 2024Allow800NoNo
18521210DEEP LINES AND SHALLOW LINES IN SIGNAL CONDUCTING PATHSNovember 2023April 2025Allow1600NoNo
18517706DIAGONAL BACKSIDE POWER AND SIGNAL ROUTING FOR AN INTEGRATED CIRCUITNovember 2023April 2025Allow1710NoNo
18515130SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAMENovember 2023July 2025Allow2010YesNo
18500370DUAL ETCH-STOP LAYER STRUCTURENovember 2023June 2025Allow1910YesNo
18384582ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICESOctober 2023September 2024Allow1110NoNo
18288083DISPLAY APPARATUS AND ELECTRONIC DEVICEOctober 2023February 2026Allow2700NoNo
18491334WINDOW, DISPLAY DEVICE INCLUDING THE SAME AND METHOD FOR MANUFACTURING THE WINDOWOctober 2023January 2026Allow2700NoNo
18489864SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAMEOctober 2023June 2024Allow800NoNo
18487957UNIT SPECIFIC VARIABLE OR ADAPTIVE METAL FILL AND SYSTEM AND METHOD FOR THE SAMEOctober 2023February 2025Allow1600NoNo
18487092SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEOctober 2023January 2026Allow2700NoNo
18378472CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CONTACT RESISTANCEOctober 2023October 2024Allow1210NoNo
18480567SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTUREOctober 2023February 2024Allow510NoNo
18371816LIGHT EMITTING DISPLAY APPARATUSSeptember 2023January 2026Allow2800NoNo
18464332SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMESeptember 2023January 2026Allow2800NoNo
18236996SEMICONDUCTOR DEVICEAugust 2023December 2025Allow2700NoNo
18236503METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING NITROGEN TREATMENTAugust 2023December 2025Allow2800NoNo
18234218DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAMEAugust 2023May 2024Allow900NoNo
18450255METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAugust 2023May 2024Allow900NoNo
18447561SEMICONDUCTOR STRUCTURE INCLUDING CAP LAYER OF TWO-DIMENSIONAL MATERIAL AND METHOD FOR MANUFACTURING THE SAMEAugust 2023March 2026Allow3110NoNo
18447889SELF-ALIGNED SCHEME FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEAugust 2023April 2025Allow2010NoNo
18362739SEMICONDUCTOR DEVICE WITH CONTACT STRUCTUREJuly 2023August 2024Allow1201NoNo
18228324Antenna Package For Signal TransmissionJuly 2023February 2025Allow1820YesNo
18227726ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURESJuly 2023November 2024Allow1620YesNo
18360901Contact Via FormationJuly 2023September 2024Allow1400NoNo
18361567NOVEL SELF-ALIGN VIA STRUCTURE BY SELECTIVE DEPOSITIONJuly 2023April 2025Allow2020NoNo
18361743CUT METAL GATE PROCESS FOR REDUCING TRANSISTOR SPACINGJuly 2023April 2025Allow2010NoNo
18358216EMBEDDED FERROELECTRIC MEMORY IN HIGH-K FIRST TECHNOLOGYJuly 2023January 2025Allow1810NoNo
18225736SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKINGJuly 2023April 2024Allow900NoNo
18224592SEMICONDUCTOR DEVICE HAVING INTER-METAL DIELECTRIC PATTERNS AND METHOD FOR FABRICATING THE SAMEJuly 2023July 2024Allow1220NoNo
18354012BONDING PROCESS FOR FORMING SEMICONDUCTOR DEVICE STRUCTUREJuly 2023November 2024Allow1610NoNo
18220886INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAMEJuly 2023October 2025Allow2700NoNo
18346999TERRACED CONDUCTOR STRUCTURE FOR SEMICONDUCTOR DEVICESJuly 2023March 2026Allow3210NoNo
18217724SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTUREJuly 2023January 2026Allow3110YesNo
18339569INTEGRATED CIRCUIT DEVICEJune 2023December 2025Allow3000NoNo
18331789CHIP AND ITS MANUFACTURING, MOUNTING METHOD AND PRINTED CIRCUIT BOARDJune 2023March 2026Abandon3310NoNo
18325905PIT-LESS CHEMICAL MECHANICAL PLANARIZATION PROCESS AND DEVICE STRUCTURES MADE THEREFROMMay 2023July 2024Allow1310NoNo
18202131SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOFMay 2023March 2026Allow3410NoNo
18322607SEMICONDUCTOR DEVICES INCLUDING CONTACT PLUGS HAVING SILICIDE LAYERS AND METHODS FOR FABRICATING THE SAMEMay 2023March 2026Allow3310NoNo
18318044METHOD FOR PRODUCING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUITMay 2023October 2025Allow2900NoNo
18317759PASSIVATION LAYER FOR INTEGRATED CIRCUIT STRUCTURE AND FORMING THE SAMEMay 2023June 2024Allow1300NoNo
18252459CMOS-COMPATIBLE GRAPHENE STRUCTURES, INTERCONNECTS AND FABRICATION METHODSMay 2023August 2025Allow2800NoNo
18313480HYBRID METAL LINE STRUCTUREMay 2023August 2024Allow1610NoNo
18310527SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFMay 2023November 2024Allow1811NoNo
18308785RAISED SOURCE/DRAIN TRANSISTORApril 2023November 2025Allow3110NoNo
18303839ETCH PROFILE CONTROL OF GATE CONTACT OPENINGApril 2023May 2024Allow1300NoNo
18032700SEMICONDUCTOR LIGHT EMITTING ELEMENT, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY DEVICEApril 2023October 2025Allow3010NoNo
18300613SEMICONDUCTOR DEVICES INCLUDING AN AIR GAP ADJACENT TO AN INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAMEApril 2023March 2026Allow3510NoNo
18300700SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICEApril 2023September 2024Allow1720NoNo
18133061METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING NITROGEN TREATMENT AND SEMICONDUCTOR STRUCTURE THEREOFApril 2023October 2025Allow3010NoNo
18190328SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAMEMarch 2023July 2024Allow1610NoNo
18190297Reducing Spacing Between Conductive Features Through ImplantationMarch 2023May 2024Allow1410NoNo
18186348SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREMarch 2023February 2024Allow1100NoNo
18183004INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAPMarch 2023January 2024Allow1000NoNo
18179676ALUMINUM STRUCTURESMarch 2023March 2026Allow3610YesNo
18179518METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH AIR GAPS FOR LOW CAPACITANCE INTERCONNECTSMarch 2023February 2026Allow3601NoNo
18118372SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEMarch 2023May 2024Allow1410NoNo
18178773AIR GAPS IN MEMORY ARRAY STRUCTURESMarch 2023April 2024Allow1410NoNo
18116433DISPLAY APPARATUS AND ELECTRONIC APPARATUS INCLUDING THE SAMEMarch 2023June 2025Allow2800NoNo
18174692PASS-THROUGH WIRING IN NOTCHED INTERCONNECTFebruary 2023August 2025Allow2900NoNo
18174431SEMICONDUCTOR DEVICEFebruary 2023March 2026Abandon3720NoNo
18167944SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE VIA STRUCTURE AND METHOD FOR FORMING THE SAMEFebruary 2023February 2026Allow3610NoNo
18107085SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEFebruary 2023August 2024Allow1900NoNo
18106697SELECTIVE ETCHING OF SILICON-CONTAINING MATERIAL RELATIVE TO METAL-DOPED BORON FILMSFebruary 2023October 2025Allow3210YesNo
18164903APPARATUSES INCLUDING DEVICE STRUCTURES INCLUDING PILLAR STRUCTURESFebruary 2023July 2024Allow1710NoNo
18163856METHOD FOR FORMING CONTACT STRUCTURE, SEMICONDUCTOR STRUCTURE AND MEMORYFebruary 2023January 2026Allow3510NoNo
18163580METHOD OF PROCESSING SUBSTRATE, RECORDING MEDIUM, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEFebruary 2023May 2024Allow1521NoNo
18160793DOUBLE PATTERNING APPROACH BY DIRECT METAL ETCHJanuary 2023November 2024Allow2130NoNo
18157962MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING CONDUCTIVE LEVELS HAVING VARYING COMPOSITIONSJanuary 2023August 2024Allow1810NoNo
18099229INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAMEJanuary 2023February 2026Allow3720NoNo
18155751METHOD FOR FORMING INTEGRATED CIRCUITJanuary 2023April 2024Allow1501NoNo
18097418SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEJanuary 2023February 2024Allow1310NoNo
18151743Semiconductor Devices and Methods of Forming the SameJanuary 2023October 2025Allow3310NoNo
18093763METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATEJanuary 2023December 2023Allow1200NoNo
18090031GATELINE MASK DESIGN FOR REMOVING SACRIFICIAL GATELINE POLYSILICON WITHIN STAIR STEP AREADecember 2022July 2025Allow3100NoNo
18086569MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOFDecember 2022April 2024Allow1610NoNo
18068615Nitrogen Plasma Treatment For Improving Interface Between Etch Stop Layer And Copper InterconnectDecember 2022July 2024Allow1920YesNo
18083818FLEXIBLE MOL AND/OR BEOL STRUCTUREDecember 2022February 2026Allow3820NoNo
18078454SEMICONDUCTOR STRUCTURE WITH BACKSIDE METALLIZATION LAYERSDecember 2022August 2025Allow3210NoNo
18075087VIA MANUFACTURING METHODDecember 2022June 2025Allow3000NoNo
18061676CAPPING LAYER FOR LINER-FREE CONDUCTIVE STRUCTURESDecember 2022March 2024Allow1610YesNo
18061642SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAMEDecember 2022October 2025Allow3510YesNo
18059698HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAMENovember 2022September 2025Allow3410NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner KUSUMAKAR, KAREN M.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
2
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
14.5%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
9
Allowed After Appeal Filing
3
(33.3%)
Not Allowed After Appeal Filing
6
(66.7%)
Filing Benefit Percentile
53.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner KUSUMAKAR, KAREN M - Prosecution Strategy Guide

Executive Summary

Examiner KUSUMAKAR, KAREN M works in Art Unit 2897 and has examined 973 patent applications in our dataset. With an allowance rate of 93.4%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.

Allowance Patterns

Examiner KUSUMAKAR, KAREN M's allowance rate of 93.4% places them in the 81% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by KUSUMAKAR, KAREN M receive 0.95 office actions before reaching final disposition. This places the examiner in the 7% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by KUSUMAKAR, KAREN M is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +2.3% benefit to allowance rate for applications examined by KUSUMAKAR, KAREN M. This interview benefit is in the 23% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 37.3% of applications are subsequently allowed. This success rate is in the 85% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 63.7% of cases where such amendments are filed. This entry rate is in the 88% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 50.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 45% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 77.8% of appeals filed. This is in the 69% percentile among all examiners. Of these withdrawals, 14.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 48.1% are granted (fully or in part). This grant rate is in the 44% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.3% of allowed cases (in the 56% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 3.1% of allowed cases (in the 74% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.