USPTO Examiner VU VU A - Art Unit 2897

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19200034THROUGHPUT IMPROVEMENTS FOR LOW-TEMPERATURE/BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS METHODS INCLUDING PROCESSING IN RETASKED TOOLSMay 2025July 2025Allow200NoNo
19013905HETEROGENEOUS ANNEALING METHOD AND DEVICEJanuary 2025September 2025Allow810YesNo
19000144THROUGHPUT IMPROVEMENTS FOR LOW-TEMPERATURE/BEOL-COMPATIBLE HIGHLY SCALABLE GRAPHENE SYNTHESIS METHODS INCLUDING PROCESSING IN RETASKED TOOLSDecember 2024April 2025Allow310NoNo
18865491METHOD FOR TRANSFERRING A LAYER FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATENovember 2024May 2025Allow610NoNo
18794859METHOD OF SELECTIVE RELEASE OF COMPONENTS USING THERMAL RELEASE LAYERAugust 2024June 2025Abandon1010NoNo
18775719SELECTIVE TRANSFER OF MICRO DEVICESJuly 2024March 2026Allow2010NoNo
18668736SYSTEM FOR BUILDING BALANCE-POINT-BASED SEASONAL FUEL CONSUMPTION FORECASTING WITH THE AID OF A DIGITAL COMPUTERMay 2024January 2025Allow810NoNo
18657689ELECTRONIC DEVICE MULTILEVEL PACKAGE SUBSTRATE FOR IMPROVED ELECTROMIGRATION PREFORMANCEMay 2024April 2025Allow1210NoNo
18653575DISPLAY DEVICE AND MANUFACTURING METHOD THEREOFMay 2024October 2025Allow1820NoNo
18620327METHOD FOR SEPARATING DIES FROM A SEMICONDUCTOR SUBSTRATEMarch 2024August 2024Allow410NoNo
18606876CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONSMarch 2024January 2025Allow1010NoNo
18589531PACKAGE STRUCTURE WITH THROUGH VIASFebruary 2024August 2025Allow1720NoNo
18589231DIRECT BONDED STACK STRUCTURES FOR INCREASED RELIABILITY AND IMPROVED YIELD IN MICROELECTRONICSFebruary 2024January 2025Allow1110YesNo
18439002SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFFebruary 2024February 2025Allow1220YesNo
18433307BAND EDGE EMISSION ENHANCED ORGANIC LIGHT EMITTING DIODE WITH A LOCALIZED EMITTERFebruary 2024March 2025Allow1410NoNo
18420972PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERSJanuary 2024October 2024Allow910NoNo
18416215SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESJanuary 2024June 2025Allow1730NoNo
18412760DISPLAY PANEL AND METHOD OF FABRICATING THE SAMEJanuary 2024November 2024Allow1010NoNo
18399189NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURESDecember 2023November 2024Allow1110NoNo
18390439ION IMPLANTATION WITH ANNEALING FOR SUBSTRATE CUTTINGDecember 2023February 2025Allow1420YesNo
18391075SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESDecember 2023February 2025Allow1420NoNo
18544590THERMALLY CONDUCTIVE WAFER LAYERDecember 2023November 2024Allow1130NoNo
18540220SEMICONDUCTOR INTEGRATED CIRCUIT DEVICEDecember 2023October 2024Allow1110NoNo
18536188SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEDecember 2023September 2024Allow910NoNo
18516703SEMICONDUCTOR PROCESSING APPARATUS AND METHOD UTILIZING ELECTROSTATIC DISCHARGE (ESD) PREVENTION LAYERNovember 2023November 2024Allow1210NoNo
18478597PARALLEL ASSEMBLY OF DISCRETE COMPONENTS ONTO A SUBSTRATESeptember 2023August 2024Allow1110YesNo
18374107DIE PACKAGE AND METHOD OF FORMING A DIE PACKAGESeptember 2023August 2024Allow1120NoNo
18550805A GIMBAL BONDING TOOL AND A METHOD TO CORRECT SURFACE NON-UNIFORMITIES USING A BONDING TOOLSeptember 2023August 2024Allow1100NoNo
18244789LIGHT RECEIVING ELEMENT, RANGING MODULE, AND ELECTRONIC APPARATUSSeptember 2023August 2024Allow1110NoNo
18459043PACKAGING METHOD AND PACKAGE MEMBERAugust 2023March 2026Allow3110NoNo
18457338SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICEAugust 2023March 2026Allow3010NoNo
18456197METHOD FOR MANUFACTURING DISPLAY PANEL, DISPLAY PANEL, AND DISPLAY APPARATUSAugust 2023August 2024Allow1210NoNo
18453721METHOD OF REDUCING RESIDUAL CONTAMINATION IN SINGULATED SEMICONDUCTOR DIEAugust 2023August 2024Allow1110NoNo
18451538LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEMEAugust 2023November 2024Abandon1510NoNo
18448220SEMICONDUCTOR PACKAGE AND METHODAugust 2023March 2026Allow3110NoNo
18448667Semiconductor Device Carriers and Methods of Making and UsingAugust 2023February 2026Allow3010NoNo
18362989SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAugust 2023June 2024Allow1110NoNo
18362960INTEGRATED CIRCUIT DEVICE AND METHODAugust 2023October 2024Allow1510NoNo
18363247JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODSAugust 2023July 2024Allow1210NoNo
18227348SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAMEJuly 2023February 2026Allow3110YesNo
18360883ORGANIC INTERPOSER INCLUDING A DUAL-LAYER INDUCTOR STRUCTURE AND METHODS OF FORMING THE SAMEJuly 2023July 2024Allow1110NoNo
18359887METHOD OF TESTING SEMICONDUCTOR PACKAGEJuly 2023October 2024Allow1520NoNo
18359924PACKAGE STRUCTURE WITH UNDERFILLJuly 2023February 2025Allow1820NoNo
18359138LIFT-OFF METHODJuly 2023March 2026Allow3110YesNo
18358904METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTORJuly 2023August 2024Allow1210NoNo
18357942APPARATUS FOR FABRICATING DISPLAY PANEL AND FABRICATING METHOD THEREOFJuly 2023February 2026Allow3110NoNo
18356227METHOD OF FABRICATING PACKAGE STRUCTUREJuly 2023August 2024Allow1310NoNo
18273507SYSTEM AND METHOD FOR CONNECTING ELECTRONIC ASSEMBLIESJuly 2023April 2024Allow910YesNo
18223035SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WAFER-ATTACHED STRUCTUREJuly 2023July 2024Allow1210NoNo
18354633PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJuly 2023July 2024Allow1210NoNo
18272453Method for manufacturing an electronic device and associated transfer deviceJuly 2023February 2026Allow3110NoNo
18350730SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOFJuly 2023June 2024Allow1110YesNo
18341085DEVICE WAFER PROCESSING METHODJune 2023February 2026Allow3210YesNo
18339548SELF-ALIGNING BONDING BY HYDROPHILIC CONTRASTJune 2023February 2026Allow3210NoNo
18211656METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICEJune 2023February 2026Allow3210NoNo
18336088INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICESJune 2023July 2024Allow1320NoNo
18332508PROCESSING APPARATUS USING LASER, METHOD OF LASER LIFT-OFF AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEJune 2023February 2026Allow3310YesNo
18265902CHIP BONDING METHODJune 2023January 2026Allow3110NoNo
18330295INTEGRATED PHOTODETECTOR WITH DIRECT BINNING PIXELJune 2023May 2024Allow1210NoNo
18329588SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAMEJune 2023November 2025Allow2920NoNo
18328913PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAMEJune 2023August 2024Allow1420YesNo
18204956PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2023December 2025Allow3110NoNo
18325707STRUCTURES AND METHODS FOR PHASE DETECTION AUTO FOCUSMay 2023December 2025Allow3010YesNo
18322579WAFER PROCESSING METHODMay 2023September 2025Allow2810NoNo
18317093METHODS FOR MAKING SEMICONDUCTOR DEVICESMay 2023January 2026Allow3210NoNo
18315991Semiconductor Device and Method of Controlling Warpage During LABMay 2023May 2024Allow1210NoNo
18035911ADHESIVE TAPE AND PROCESSING METHODMay 2023March 2026Abandon3410NoNo
18312655WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTUREMay 2023October 2024Allow1820YesNo
18312641WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTUREMay 2023May 2024Allow1220YesNo
18142142SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTUREMay 2023June 2024Allow1320NoNo
18140425SELF ALIGNED PATTERN FORMATION POST SPACER ETCHBACK IN TIGHT PITCH CONFIGURATIONSApril 2023May 2024Allow1310YesNo
18137014SEMICONDUCTOR PACKAGE AND METHOD FOR MARKING A SEMICONDUCTOR PACKAGEApril 2023March 2026Allow3520NoNo
18135623SEMICONDUCTOR PACKAGEApril 2023November 2025Allow3110YesNo
18031735METHOD FOR PRODUCING A LIGHT EMITTING DIODE SUPPLY SUBSTRATE, METHOD FOR PRODUCING A LIGHT EMITTING DIODE DISPLAY, METHOD FOR PRODUCING A DIVISION UNIT FOR A LIGHT EMITTING DIODE DISPLAY, AND METHOD FOR PRODUCING A DEVICE SUPPLY SUBSTRATEApril 2023February 2026Allow3410NoNo
18132199PARTICLE CAPTURE USING TRANSFER STAMPApril 2023May 2024Allow1420NoNo
18127539NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURESMarch 2023May 2024Allow1420NoNo
18246855FILM FOR TEMPORARY FIXATION, LAYERED PRODUCT FOR TEMPORARY FIXATION, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICEMarch 2023November 2025Allow3210NoNo
18190949TEST METHOD, MANUFACTURING METHOD, PANEL LEVEL PACKAGE, AND TEST APPARATUSMarch 2023February 2026Allow3521NoNo
18188084SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEMarch 2023November 2025Allow3210NoNo
18186202SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAMEMarch 2023February 2026Allow3520YesNo
18181960SYSTEM FOR PLOT-BASED BUILDING SEASONAL FUEL CONSUMPTION FORECASTING WITH THE AID OF A DIGITAL COMPUTERMarch 2023February 2024Allow1110NoNo
18025443WORKPIECE SEPARATION DEVICE AND WORKPIECE SEPARATION METHODMarch 2023April 2024Abandon1410NoNo
18177739SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEMarch 2023January 2026Allow3520NoNo
18176736CONNECTIONS FROM BURIED INTERCONNECTS TO DEVICE TERMINALS IN MULTIPLE STACKED DEVICES STRUCTURESMarch 2023August 2025Allow2910YesNo
18177072SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICEMarch 2023September 2025Allow3110NoNo
18043578SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREFORFebruary 2023December 2025Allow3410NoNo
18115043CARRIER PLATE FOR PREPARING PACKAGE SUBSTRATE, PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOFFebruary 2023December 2025Allow3410NoNo
18176143METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR PRODUCING SEMICONDUCTOR PACKAGEFebruary 2023February 2024Allow1210NoNo
18024042BASE PLATE AND SUBSTRATE ASSEMBLYFebruary 2023February 2026Allow3620NoNo
18174866SEMICONDUCTOR MODULEFebruary 2023August 2025Allow3010NoNo
18172975WAFER LEVEL PACKAGING PROCESS FOR THIN FILM INDUCTORSFebruary 2023September 2025Allow3110NoNo
18112466WAFER SUPPORTING MECHANISM AND METHOD FOR WAFER DICINGFebruary 2023June 2024Allow1620NoNo
18171662SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOFFebruary 2023December 2025Allow3320NoNo
18021813Substrate and Preparation Method thereof, Integrated Passive Device, and Electronic ApparatusFebruary 2023December 2025Allow3410NoNo
18169625FILM FRAME CARRIER FOR A CURVED WAFER STAGEFebruary 2023March 2026Allow3720NoNo
18104982INTEGRATED WAFER DEBONDING AND CLEANING APPARATUS AND DEBONDING AND CLEANING METHODFebruary 2023July 2025Allow3010NoNo
18007103HYBRID RELEASE LAYER FOR MICRODEVICE CARTRIDGEJanuary 2023December 2025Allow3420NoNo
18016853FLEXIBLE OPTOELECTRONIC DEVICE AND PROCESS FOR MANUFACTURING SAMEJanuary 2023October 2025Allow3310NoNo
18153630SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAMEJanuary 2023September 2025Allow3210YesNo
18152558Three-Dimensional Semiconductor Device and MethodJanuary 2023December 2025Allow3511NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner VU, VU A.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
1
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
14.5%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
3
Allowed After Appeal Filing
1
(33.3%)
Not Allowed After Appeal Filing
2
(66.7%)
Filing Benefit Percentile
53.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner VU, VU A - Prosecution Strategy Guide

Executive Summary

Examiner VU, VU A works in Art Unit 2897 and has examined 101 patent applications in our dataset. With an allowance rate of 96.0%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 31 months.

Allowance Patterns

Examiner VU, VU A's allowance rate of 96.0% places them in the 86% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by VU, VU A receive 1.56 office actions before reaching final disposition. This places the examiner in the 29% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by VU, VU A is 31 months. This places the examiner in the 56% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +4.7% benefit to allowance rate for applications examined by VU, VU A. This interview benefit is in the 29% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 41.5% of applications are subsequently allowed. This success rate is in the 93% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 59.5% of cases where such amendments are filed. This entry rate is in the 85% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 97% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 75.0% of appeals filed. This is in the 65% percentile among all examiners. Of these withdrawals, 33.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 66.7% are granted (fully or in part). This grant rate is in the 73% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 28% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 2.1% of allowed cases (in the 68% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.