USPTO Art Unit 2827 Prosecution Statistics

Art Unit Information

Art Unit: 2827
Group: 2820
Tech Center: 2800
Total Cases: 26,354
Last Active: July 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19261799SYSTEMS AND METHODS FOR IMPLEMENTING A FEEDBACK-INFORMED MEMORY PROGRAMMING OF AN INTEGRATED CIRCUITJuly 2025September 2025Allow200YesNo
18975798BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAMEDecember 2024November 2025Allow1100YesNo
18926560LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEMOctober 2024December 2024Allow110NoNo
18888087NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH MULTI-WAY SHARING OF GAIN ELEMENT WITH SERIES TRANSISTORSeptember 2024March 2026Allow1800NoNo
18829968MAGNETIC MEMORYSeptember 2024March 2026Allow1800NoNo
18826515MEMORY SYSTEMS, OPERATING METHODS FOR MEMORY SYSTEMS, CONTROLLER AND STORAGE MEDIUMSeptember 2024March 2026Allow1800NoNo
18825487ADDRESS PATH ROUTING REDUCTION STRATEGY FOR NONVOLATILE MEMORY DECODERSSeptember 2024March 2026Allow1800NoNo
18824515APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKINGSeptember 2024March 2026Allow1800NoNo
18822985BITLINE SENSE AMPLIFIERS AND SEMICONDUCTOR DEVICES INCLUDING THE SAMESeptember 2024March 2026Allow1800NoNo
18820449REFERENCE VOLTAGE CALIBRATION APPARATUS IN MEMORY INTERFACEAugust 2024March 2026Allow1800NoNo
18821402SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND CONTROL METHODAugust 2024March 2026Allow1800NoNo
18821016SEMICONDUCTOR DEVICEAugust 2024February 2026Allow1800NoNo
18818913MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAMEAugust 2024March 2026Allow1800NoNo
18819770MEMORY DEVICEAugust 2024February 2026Allow1800NoNo
18818078HANDLING POWER-LOSS RESET EVENTS WITH BAD BLOCK RISK MITIGATIONAugust 2024March 2026Allow1800NoNo
18816949METHODS OF OPERATING MEMORIES, MEMORIES AND MEMORY SYSTEMSAugust 2024February 2026Allow1800NoNo
18816921MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMS, AND ELECTRONIC DEVICESAugust 2024March 2026Allow1800NoNo
18815547METHOD OF OPERATING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICEAugust 2024March 2026Allow1900NoNo
18814679SEMICONDUCTOR MEMORY DEVICEAugust 2024February 2026Allow1800NoNo
18815802MEMORY DEVICE AND INTERNAL VOLTAGE MEASURING METHOD THEREOFAugust 2024March 2026Allow1800NoNo
18807590MEMORY DEVICE, MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD THEREOFAugust 2024February 2026Allow1800NoNo
18806082LOW DROPOUT REGULATORSAugust 2024February 2026Allow1800NoNo
18806359APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR CLOCK SWITCHING AND LOW POWER CONSUMPTIONAugust 2024February 2026Allow1800NoNo
18804524CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE, OPERATION METHOD OF CONTROLLER, AND STORAGE DEVICE INCLUDING MEMORY DEVICE AND CONTROLLERAugust 2024February 2026Allow1800NoNo
18801328READING VOLTAGE MANAGEMENT METHOD AND STORAGE DEVICEAugust 2024February 2026Allow1800NoNo
18799934NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICEAugust 2024February 2026Allow1800NoNo
18796143MEMORY WITH DOUBLE REDUNDANCYAugust 2024March 2026Allow1900NoNo
18795818MEMORY SYSTEMAugust 2024March 2026Allow1900NoNo
18793984NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACEAugust 2024February 2026Allow1900NoNo
18793177VARIABLE RESISTANCE MEMORY DEVICEAugust 2024March 2026Allow1900NoNo
18791722MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SYSTEMAugust 2024February 2026Allow1900NoNo
18789680SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CIRCUITRYJuly 2024February 2026Allow1800NoNo
18790480READ VOLTAGE LEVEL BIN SELECTIONJuly 2024February 2026Allow1800NoNo
18789364CONFIGURABLE PROGRAM VERIFY LEVELS ACCORDING TO PROGRAM-ERASE CYCLES AT A MEMORY SYSTEMJuly 2024January 2026Allow1800NoNo
18788480READ AND WRITE ENHANCEMENTS FOR ARRAYS OF SUPERCONDUCTING MEMORY CELLSJuly 2024March 2026Allow1910NoNo
18788926NON-VOLATILE MEMORY DEVICEJuly 2024January 2026Allow1700NoNo
18787812CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALINGJuly 2024February 2026Allow1900NoNo
18787957USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCKS IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18788001CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICESJuly 2024February 2026Allow1800NoNo
18787977READ MARGIN HEALTH EVALUATIONS FOR MEMORY SYSTEMSJuly 2024February 2026Allow1800NoNo
18786480PROCESSING IN MEMORY REGISTERSJuly 2024March 2026Allow2000NoNo
18786291MEMORY DEVICE WITH A STORAGE COMPONENTJuly 2024January 2026Allow1800NoNo
18785902EFFICIENT EMPTY PAGE SCAN OPERATIONSJuly 2024January 2026Allow1800NoNo
18784505APPARATUS AND METHODS FOR DETECTING COUPLING FAULTS IN NON-VOLATILE MEMORY DEVICESJuly 2024February 2026Allow1900NoNo
18784152Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory CellsJuly 2024February 2026Allow1800NoNo
18784022ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINESJuly 2024March 2026Allow1900NoNo
18783345SEMICONDUCTOR MEMORY DEVICEJuly 2024March 2026Allow1910NoNo
18781317PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICESJuly 2024January 2026Allow1800NoNo
18781878NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT WITH SERIES TRANSISTOR AND INDIVIDUAL ACCESS TRANSISTORJuly 2024October 2025Allow1500NoNo
18781916NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARED GAIN ELEMENT WITH SERIES TRANSISTORJuly 2024January 2026Allow1800NoNo
18778321MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEURAL NETWORKJuly 2024January 2026Allow1800NoNo
18775312SYSTEM AND METHOD FOR PROVIDING COMPRESSION ATTACHED MEMORY MODULE COMPRESSION CONNECTORSJuly 2024December 2024Allow510NoNo
18773628MEMORY CIRCUIT AND WORD LINE DRIVERJuly 2024June 2025Allow1110NoNo
18774638VOLTAGE SCALING BASED ON ERROR RATE FLUCTUATIONSJuly 2024February 2026Allow1900NoNo
18774226METHODS OF OPERATING MAGNETIC MEMORY DEVICESJuly 2024February 2026Allow1900NoNo
18772721POWER MODE WAKE-UP FOR MEMORY ON DIFFERENT POWER DOMAINSJuly 2024February 2026Allow1900YesNo
18771393ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICESJuly 2024March 2026Allow2010NoNo
18771819ENHANCED COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICEJuly 2024December 2025Allow1800NoNo
18771536ELECTRICAL FUSE BIT CELL IN INTEGRATED CIRCUIT HAVING BACKSIDE CONDUCTING LINESJuly 2024February 2026Allow1900NoNo
18771019SEMICONDUCTOR DEVICEJuly 2024December 2025Allow1700NoNo
18771479ACCESS LINE VOLTAGE RAMP RATE ADJUSTMENTJuly 2024January 2026Allow1900NoNo
18769532COMPUTE-IN-MEMORY DEVICE AND METHODJuly 2024March 2026Allow2020NoNo
18770632MANAGING PROGRAM DISTURB IN MEMORY DEVICESJuly 2024January 2026Allow1800NoNo
18770397Methods for Reading Resistive States of Resistive Change ElementsJuly 2024October 2025Abandon1610NoNo
18769628HANDLING WRITE COMMANDS DURING A REFRESH OPERATION IN A SHINGLED MAGNETIC RECORDING DRIVEJuly 2024January 2026Allow1900NoNo
18768970SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING USING GATE INDUCED DRAIN LEAKAGEJuly 2024December 2025Allow1700NoNo
18768974SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING BY CREATING A PSEUDO PN JUNCTIONJuly 2024February 2026Allow1900NoNo
18768806SECOND READ INITIALIZATION ON LATCH-LIMITED MEMORY DEVICEJuly 2024February 2026Allow1910NoNo
18767238MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAMEJuly 2024January 2026Allow1800NoNo
18727465MAGNETO RESISTIVE MEMORY DEVICEJuly 2024December 2025Allow1700NoNo
18766414POWER CONTROL CHAINJuly 2024January 2026Allow1900NoNo
18765358NON-VOLATILE MEMORY WITH AUXILIARY SELECT GATE LINE DRIVERJuly 2024December 2025Allow1700NoNo
18765076WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICESJuly 2024January 2025Allow700NoNo
18764581MAGNETIC MEMORY AND MEMORY SYSTEMJuly 2024January 2026Allow1800YesNo
18763776MEMORY DEVICE USING SEMICONDUCTOR ELEMENTJuly 2024February 2026Allow1900NoNo
18763048SWITCHES TO REDUCE ROUTING RAILS OF MEMORY SYSTEMJuly 2024May 2025Allow1010NoNo
18761171Staggered Write Control for Dual-Interlocked CellsJuly 2024March 2026Allow2010NoNo
18761264Magnetic Memory Device and Method for Using the SameJuly 2024January 2026Allow1900NoNo
18760971RESISTIVE MEMORY WITH LOW VOLTAGE OPERATIONJuly 2024February 2025Allow700NoNo
18758738SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAMEJune 2024November 2025Allow1700NoNo
18758901MEMORY CELL INCLUDING PROGRAMMABLE RESISTORS WITH TRANSISTOR COMPONENTSJune 2024June 2025Allow1110NoNo
18758749APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGSJune 2024March 2026Allow2000NoNo
18757857SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICESJune 2024February 2026Allow2000NoNo
18755707DATA INVERSION ENCODING CIRCUIT, eFLASH MEMORY DEVICE AND OPERATION METHOD THEREOFJune 2024March 2026Allow2010NoNo
18757302MEMORY WITH REDUNDANT READ OPTIMIZATIONJune 2024November 2025Allow1700NoNo
18757422SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINESJune 2024March 2026Allow2010YesNo
18756406INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKSJune 2024March 2025Allow910NoNo
18754190STORAGE DEVICE AND OPERATING METHOD THEREOFJune 2024June 2025Allow1210NoNo
18754159SOFT PROGRAMMING METHOD AND ERASING METHOD FOR MEMORY DEVICEJune 2024March 2026Allow2010NoNo
18755033DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICESJune 2024January 2025Allow700NoNo
18755329REPAIRING DEFECTIVE COLUMNS OF COMPUTE-IN-MEMORY AND NEAR-MEMORY COMPUTING DEVICESJune 2024February 2026Allow2000NoNo
18753094NON-VOLATILE MEMORY AND CORRESPONDING MANUFACTURING METHODJune 2024December 2025Allow1700NoNo
18752870NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL ARRAY AND A CONTROL CIRCUIT APPLYING A READING VOLTAGEJune 2024February 2025Allow700NoNo
18752801MRAM CIRCUIT AND LAYOUTJune 2024December 2025Allow1800YesNo
18750641MEMORY, OPERATION METHOD OF MEMORY, AND MEMORY SYSTEMJune 2024January 2026Allow1900NoNo
18751094Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell ArrayJune 2024January 2026Allow1900NoNo
18751162DEVICES AND METHODS FOR PROGRAMMING A FUSEJune 2024April 2025Allow1010NoNo
18750232SEMICONDUCTOR DEVICEJune 2024January 2026Allow1900NoNo
18749289STEP VOLTAGE DURING CURRENT FORCE READ OF PROGRAMMABLE RESISTANCE MEMORY CELL WITH THRESHOLD SWITCHING SELECTORJune 2024January 2026Allow1900NoNo
18749538PROGRAM OPERATIONS IN MEMORY DEVICESJune 2024February 2026Allow2000NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2827.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
53
Examiner Affirmed
36
(67.9%)
Examiner Reversed
17
(32.1%)
Reversal Percentile
48.5%
Lower than average

What This Means

With a 32.1% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
398
Allowed After Appeal Filing
201
(50.5%)
Not Allowed After Appeal Filing
197
(49.5%)
Filing Benefit Percentile
96.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 50.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2827 - Prosecution Statistics Summary

Executive Summary

Art Unit 2827 is part of Group 2820 in Technology Center 2800. This art unit has examined 26,354 patent applications in our dataset, with an overall allowance rate of 93.7%. Applications typically reach final disposition in approximately 18 months.

Comparative Analysis

Art Unit 2827's allowance rate of 93.7% places it in the 92% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2827 receive an average of 1.07 office actions before reaching final disposition (in the 6% percentile). The median prosecution time is 18 months (in the 97% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.