USPTO Art Unit 2827 Prosecution Statistics

Art Unit Information

Art Unit: 2827
Group: 2820
Tech Center: 2800
Total Cases: 27,244
Last Active: October 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18926560LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEMOctober 2024December 2024Allow110NoNo
18775312SYSTEM AND METHOD FOR PROVIDING COMPRESSION ATTACHED MEMORY MODULE COMPRESSION CONNECTORSJuly 2024December 2024Allow510NoNo
18773628MEMORY CIRCUIT AND WORD LINE DRIVERJuly 2024June 2025Allow1110NoNo
18765076WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICESJuly 2024January 2025Allow700NoNo
18763048SWITCHES TO REDUCE ROUTING RAILS OF MEMORY SYSTEMJuly 2024May 2025Allow1010NoNo
18760971RESISTIVE MEMORY WITH LOW VOLTAGE OPERATIONJuly 2024February 2025Allow700NoNo
18758901MEMORY CELL INCLUDING PROGRAMMABLE RESISTORS WITH TRANSISTOR COMPONENTSJune 2024June 2025Allow1110NoNo
18756406INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKSJune 2024March 2025Allow910NoNo
18754190STORAGE DEVICE AND OPERATING METHOD THEREOFJune 2024June 2025Allow1210NoNo
18755033DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICESJune 2024January 2025Allow700NoNo
18752870NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL ARRAY AND A CONTROL CIRCUIT APPLYING A READING VOLTAGEJune 2024February 2025Allow700NoNo
18751162DEVICES AND METHODS FOR PROGRAMMING A FUSEJune 2024April 2025Allow1010NoNo
18749271SEMICONDUCTOR STORAGE DEVICEJune 2024May 2025Allow1110NoNo
18744146MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICESJune 2024May 2025Allow1110NoNo
18744280SRAM Design with Four-Poly-PitchJune 2024March 2025Allow910NoNo
18743950DRAM COMPUTATION CIRCUIT AND METHODJune 2024April 2025Allow1010NoNo
18743997RRAM CIRCUIT AND METHODJune 2024January 2025Allow700NoNo
18741021MEMORY DEVICE AND METHODSJune 2024April 2025Allow1010NoNo
18735782MEMORY DEVICE AND OPERATING METHOD THEREOFJune 2024June 2025Allow1210NoNo
18680395On-Die Termination of Address and Command SignalsMay 2024January 2025Allow700NoNo
18677655MEMORY CONTROLLER AND OPERATING METHOD THEREOFMay 2024June 2025Allow1310NoNo
18677095MEMORY DEVICE AND METHOD OF OPERATING THE SAMEMay 2024December 2024Allow600NoNo
18675257MEMORY SYSTEM AND MEMORY DEVICEMay 2024January 2025Allow700NoNo
18675997LOW POWER MANAGEMENT FOR SLEEP MODE OPERATION OF A MEMORY DEVICEMay 2024May 2025Allow1110YesNo
18673246SIGNAL SKEW IN SOURCE-SYNCHRONOUS SYSTEMMay 2024January 2025Allow800NoNo
18670073PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICEMay 2024June 2025Allow1310NoNo
18664199PROGRAMMING TECHNIQUES FOR POLARITY-BASED MEMORY CELLSMay 2024January 2025Allow800NoNo
18663114METHOD FOR MANAGING A MEMORY APPARATUSMay 2024January 2025Allow810NoNo
18662709ONON Sidewall Structure for Memory Device and Method for Making the SameMay 2024December 2024Allow700NoNo
18662971SEMICONDUCTOR MEMORY DEVICEMay 2024December 2024Allow700NoNo
18661300AUTO-REFERENCED MEMORY CELL READ TECHNIQUESMay 2024December 2024Allow700NoNo
18660002TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUSMay 2024January 2025Allow910NoNo
18658864APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAMEMay 2024February 2025Allow910NoNo
18657640DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHODMay 2024February 2025Allow900NoNo
18657376MEMORY DEVICE AND ELECTRONIC DEVICEMay 2024November 2024Allow600NoNo
18654443MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAMEMay 2024April 2025Allow1110NoNo
18654697IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEMMay 2024November 2024Allow600NoNo
18653241MEMORY SYSTEMMay 2024February 2025Allow1010NoNo
18653785SEMICONDUCTOR STORAGE DEVICEMay 2024November 2024Allow700NoNo
18651261SMART PROLOGUE FOR NONVOLATILE MEMORY PROGRAM OPERATIONApril 2024November 2024Allow700NoNo
18651032APPARATUS WITH POST-MANUFACTURING DATA UPDATE MECHANISM AND METHODS FOR OPERATING THE SAMEApril 2024January 2025Allow900NoNo
18649739BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICEApril 2024April 2025Allow1110NoNo
18650058MEMORY DEVICE AND OPERATING METHOD OF THE SAMEApril 2024February 2025Allow1001NoNo
18646059MEMORY COMPONENT WITH PROGRAMMABLE DATA-TO-CLOCK RATIOApril 2024November 2024Allow600NoNo
18646334PHASE-CHANGE MEMORYApril 2024March 2025Allow1100NoNo
18643714OPTIMIZING POWER IN A MEMORY DEVICEApril 2024March 2025Allow1010NoNo
18642253ALGORITHM QUALIFIER COMMANDSApril 2024April 2025Allow1110NoNo
18639690PRE-DECODER CIRCUITRYApril 2024March 2025Allow1110NoNo
18634074DYNAMIC ALLOCATION OF A CAPACITIVE COMPONENT IN A MEMORY DEVICEApril 2024May 2025Allow1310NoNo
18632583PHASE-CHANGE MEMORY CELL AND METHOD FOR FABRICATING THE SAMEApril 2024February 2025Allow1110NoNo
18632856MEMORY DEVICE WITH REDUCED AREAApril 2024March 2025Allow1110NoNo
18631706VERTICAL MEMORY DEVICES AND METHODS FOR OPERATING THE SAMEApril 2024February 2025Allow1000NoNo
18627427MERGED BIT LINES FOR HIGH DENSITY MEMORY ARRAYApril 2024October 2024Allow700NoNo
18626971SEMICONDUCTOR MEMORY DEVICES WITH DIODE-CONNECTED MOSApril 2024October 2024Allow700NoNo
18626227SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMSApril 2024March 2025Allow1210NoNo
18621855SYSTEMS AND METHODS TO STORE MULTI-LEVEL DATAMarch 2024April 2025Allow1310NoNo
18618777SEMICONDUCTOR DEVICE HAVING PDA FUNCTIONMarch 2024April 2025Allow1210NoNo
18618754CROSS-POINT ARRAY REFRESH SCHEMEMarch 2024January 2025Allow1000NoNo
18618460MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICEMarch 2024April 2025Allow1210NoNo
18615214HOME WIRELESS DISCOVERYMarch 2024March 2025Allow1210NoNo
18615399FUSE DELAY OF A COMMAND IN A MEMORY PACKAGEMarch 2024June 2025Allow1511NoNo
18613301LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEMMarch 2024June 2024Allow310NoNo
18613466LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEMMarch 2024May 2024Allow210NoNo
18614180SEMICONDUCTOR MEMORY STRUCTUREMarch 2024April 2025Allow1310NoNo
18610880METHOD AND APPARATUS FOR POWER SAVING IN SEMICONDUCTOR DEVICESMarch 2024February 2025Allow1110NoNo
18607999DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICEMarch 2024December 2024Allow910NoNo
18607725THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLSMarch 2024September 2024Allow600NoNo
18604133LOAD REDUCED MEMORY MODULEMarch 2024September 2024Allow600NoNo
18602521USING EMBEDDED SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEMMarch 2024March 2025Allow1210YesNo
18601456VARIABLE VOLTAGE BIT LINE PRECHARGEMarch 2024March 2025Allow1310NoNo
18601367MEMORY CIRCUIT AND METHOD OF OPERATING SAMEMarch 2024June 2025Allow1510NoNo
18601810STORING ONE DATA VALUE BY PROGRAMMING A FIRST MEMORY CELL AND A SECOND MEMORY CELLMarch 2024March 2025Allow1310NoNo
18601100MEMORY READOUT CIRCUIT AND METHODMarch 2024September 2024Allow600NoNo
18601994METHODS OF WRITING AND FORMING MEMORY DEVICEMarch 2024February 2025Allow1110NoNo
18598237COMMAND-TRIGGERED DATA CLOCK DISTRIBUTION MODEMarch 2024March 2025Allow1210NoNo
18596150CELL CYCLING TO MINIMIZE RESISTIVE MEMORY RANDOM NUMBER CORRELATIONMarch 2024September 2024Allow600NoNo
18596412MEMORY DEVICE AND METHOD OF OPERATING THE SAMEMarch 2024February 2025Allow1210NoNo
18595909MEMORY DEVICE AND OPERATION THEREOFMarch 2024December 2024Allow910NoNo
18595293SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDEMarch 2024April 2025Allow1310NoNo
18595188MEMORY AND OPERATING METHOD THEREOFMarch 2024September 2024Allow700NoNo
18593635ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICEMarch 2024March 2025Allow1310NoNo
18592833INTEGRATED CIRCUIT DEVICE INCLUDING AN SRAM PORTION HAVING END POWER SELECT CIRCUITSMarch 2024April 2025Allow1410NoNo
18589540CIRCUIT DESIGN AND LAYOUT WITH HIGH EMBEDDED MEMORY DENSITYFebruary 2024May 2025Allow1510YesNo
18590207CONTROL METHOD AND CONTROLLER OF 3D NAND FLASHFebruary 2024November 2024Allow910NoNo
18589184READ BROADCAST OPERATIONS ASSOCIATED WITH A MEMORY DEVICEFebruary 2024May 2025Allow1511NoNo
18587872Superconductive Memory Cells and DevicesFebruary 2024November 2024Allow910NoNo
18587443DIFFERENTIAL PROGRAMMING OF TWO-TERMINAL RESISTIVE SWITCHING MEMORY WITH PROGRAM SOAKING AND ADJACENT PATH DISABLEMENTFebruary 2024November 2024Allow910NoNo
18586149VARYING-POLARITY READ OPERATIONS FOR POLARITY-WRITTEN MEMORY CELLSFebruary 2024April 2025Allow1310NoNo
18583510VOLTAGE DETECTION FOR MANAGED MEMORY SYSTEMSFebruary 2024October 2024Allow800NoNo
18581340FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTORFebruary 2024February 2025Allow1210NoNo
18581018NONVOLATILE MEMORY DEVICESFebruary 2024January 2025Allow1110NoNo
18443997MEMORY ARRAY TEST STRUCTURE AND METHOD OF FORMING THE SAMEFebruary 2024September 2024Allow700NoNo
18443358CIRCUIT MODULE WITH RELIABLE MARGIN CONFIGURATIONFebruary 2024February 2025Allow1210NoNo
18442660METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHEFebruary 2024February 2025Allow1210NoNo
18439982SYSTEM FOR DIFFERENTIATED THERMAL THROTTLING OF MEMORY AND METHOD OF OPERATING SAMEFebruary 2024December 2024Allow1010NoNo
18438807Tri-state electrical information storageFebruary 2024January 2025Allow1110NoNo
18438732MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLERFebruary 2024January 2025Allow1110YesNo
18438174MAGNETIC MEMORY USING SPIN-ORBIT TORQUEFebruary 2024January 2025Allow1210YesNo
18434752MEMORY DEVICES, CIRCUITS AND METHODS OF ADJUSTING A SENSING CURRENT FOR THE MEMORY DEVICEFebruary 2024March 2025Allow1310NoNo
18429677Integrated Assemblies and Methods of Forming Integrated AssembliesFebruary 2024November 2024Allow900NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2827.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
47
Examiner Affirmed
32
(68.1%)
Examiner Reversed
15
(31.9%)
Reversal Percentile
48.3%
Lower than average

What This Means

With a 31.9% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
349
Allowed After Appeal Filing
179
(51.3%)
Not Allowed After Appeal Filing
170
(48.7%)
Filing Benefit Percentile
96.3%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 51.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2827 - Prosecution Statistics Summary

Executive Summary

Art Unit 2827 is part of Group 2820 in Technology Center 2800. This art unit has examined 27,244 patent applications in our dataset, with an overall allowance rate of 94.1%. Applications typically reach final disposition in approximately 18 months.

Comparative Analysis

Art Unit 2827's allowance rate of 94.1% places it in the 94% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2827 receive an average of 1.03 office actions before reaching final disposition (in the 6% percentile). The median prosecution time is 18 months (in the 96% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.