USPTO Examiner DINH MINH D - Art Unit 2827

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18815547METHOD OF OPERATING A THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICEAugust 2024March 2026Allow1900NoNo
18793177VARIABLE RESISTANCE MEMORY DEVICEAugust 2024March 2026Allow1900NoNo
18754190STORAGE DEVICE AND OPERATING METHOD THEREOFJune 2024June 2025Allow1210NoNo
18749289STEP VOLTAGE DURING CURRENT FORCE READ OF PROGRAMMABLE RESISTANCE MEMORY CELL WITH THRESHOLD SWITCHING SELECTORJune 2024January 2026Allow1900NoNo
18744146MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICESJune 2024May 2025Allow1110NoNo
18735782MEMORY DEVICE AND OPERATING METHOD THEREOFJune 2024June 2025Allow1210NoNo
18667802PRE-DECODER CIRCUITRYMay 2024July 2025Allow1420NoNo
18666520MEMORY DEVICES AND OPERATION METHODS THEREOF, AND MEMORY SYSTEMSMay 2024January 2026Allow2000NoNo
18658819SEMICONDUCTOR MEMORY DEVICEMay 2024August 2025Allow1610NoNo
18658864APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAMEMay 2024February 2025Allow910NoNo
18636211VOLTAGE MONITOR OF MEMORY DEVICEApril 2024December 2025Allow2000NoNo
18626718POWER SUPPLY GENERATOR ASSISTApril 2024February 2026Allow2210NoNo
18596951ELECTRONIC DEVICE INCLUDING DRAM AND METHOD FOR OPERATING THE SAMEMarch 2024December 2025Allow2100NoNo
18587872Superconductive Memory Cells and DevicesFebruary 2024November 2024Allow910NoNo
18437481VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE FOR DRIVING AN INTERNAL VOLTAGEFebruary 2024November 2025Allow2100NoNo
18421138MEMORY CIRCUIT, INTERFACE CIRCUIT FOR MEMORY CIRCUIT, AND METHOD OF OPERATING MEMORY CIRCUITJanuary 2024January 2026Allow2410NoNo
18420867MEMORY DEVICE FOR CONTROLLING A DATA OUTPUT ORDER AND AN OPERATING METHOD THEREOFJanuary 2024February 2026Allow2510YesNo
18417729RESISTIVE RANDOM ACCESS MEMORY DEVICEJanuary 2024January 2025Allow1220NoNo
18409992CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYSJanuary 2024December 2024Allow1110NoNo
18410985MEMORY DEVICE AND WRAP AROUND READ METHOD THEREOFJanuary 2024September 2025Allow2000NoNo
18407366SELF-OPTIMIZING CORRECTIVE READ OFFSETS WITH LATERAL CHARGE MIGRATION PROXIESJanuary 2024August 2025Allow2000NoNo
18402172Write Driver Boost Circuit for Memory CellsJanuary 2024December 2024Allow1110NoNo
18390423ENHANCED ERROR CORRECTION CODE FOR ERROR DETECTION AND CORRECTION IN MULTI-LEVEL CELL-BASED MEMORY DEVICESDecember 2023February 2026Allow2610NoNo
18533922POWER-AWARE MEMORY CONTROLDecember 2023February 2026Allow2610NoNo
18531907SEMICONDUCTOR MEMORY DEVICEDecember 2023November 2025Allow2410NoNo
18515210SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR DEVICENovember 2023July 2025Allow2000NoNo
18389525DATA PROCESSING NEAR DATA STORAGENovember 2023August 2024Allow910NoNo
18500577SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICENovember 2023September 2024Allow1110YesNo
18370644METHOD OF VOLTAGE CALIBRATION AND APPARATUS THEREOF, MEMORY AND MEMORY SYSTEMSeptember 2023September 2025Allow2410YesNo
18370412ANTIFUSE-TYPE NON-VOLATILE MEMORY AND CONTROL METHOD THEREOFSeptember 2023June 2025Allow2100NoNo
18461504LOW-POWER MEMORY SYSTEM AND MEMORY CONTROLLER WITH COMPATIBILITY AND AN OPERATION METHOD THEREOFSeptember 2023May 2025Allow2000NoNo
18240180MEMORY SYSTEM, METHOD OF OPERATING MEMORY SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUMAugust 2023January 2026Allow2810NoNo
18455385Memory Subsystem Calibration Using Substitute ResultsAugust 2023January 2025Allow1720NoNo
18268651COUNTER-BASED SELECTIVE ROW HAMMER REFRESH APPARATUS AND METHOD FOR ROW HAMMER PREVENTIONAugust 2023May 2025Allow2310NoNo
18226547REGULAR TRANSISTOR THRESHOLD VOLTAGE REFRESH FOR SEMI-CIRCLE DRAIN SIDE SELECT GATESJuly 2023November 2025Allow2710NoNo
18359637ERROR HANDLING DURING A MEMORY COMPACTION PROCESSJuly 2023March 2026Allow3120YesNo
18357359STORAGE DEVICE FOR IDLE POWER OPERATION AND METHOD THEREFORJuly 2023September 2025Allow2610NoNo
18224179MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEMJuly 2023April 2024Allow910NoNo
18348366APPARATUS AND METHOD FOR PROGRAMMING DATA INTO NON-VOLATILE MEMORY DEVICEJuly 2023September 2025Allow2610NoNo
18218434SENSING AND TUNING FOR MEMORY DIE POWER MANAGEMENTJuly 2023December 2024Allow1720NoNo
18346110Method And Apparatus For Quantization And Dequantization Of Neural Network Input And Output Data Using Processing-In-MemoryJune 2023April 2025Allow2200NoNo
18342013COMPUTING-IN-MEMORY DEVICE INCLUDING DIGITAL-TO-ANALOG CONVERTER BASED ON MEMORY STRUCTUREJune 2023April 2025Allow2210NoNo
18213826MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE, AND METHOD OF OPERATING MEMORY DEVICEJune 2023August 2025Allow2610YesNo
18213237Multi-Output Look-Up Table (LUT) for Use in Coarse-Grained Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) ChipJune 2023November 2024Allow1700NoNo
18332674CURRENT STEERING IN READING MAGNETIC TUNNEL JUNCTIONJune 2023September 2024Allow1620NoNo
18204972STORAGE DEVICES DETECTING INTERNAL TEMPERATURE AND DEFECTS BY USING TEMPERATURE SENSORS AND METHODS OF OPERATING THE SAMEJune 2023March 2025Allow2100NoNo
18205057BIT LINE SENSE AMPLIFIER AND BIT LINE SENSING METHOD OF SEMICONDUCTOR MEMORY DEVICEJune 2023April 2025Allow2200NoNo
18327759METHOD OF OPERATING A CONTROLLER AND A MEMORY DEVICE RELATED TO RECOVERING DATAJune 2023July 2025Allow2610YesNo
18326539LEVEL-SHIFTER HAVING A WIDE OPERATING RANGE, A FAST OUTPUT FALL DELAY AND IMPROVED RISE TIMEMay 2023July 2025Allow2510YesNo
18201213FORMING METHOD OF RESISTIVE RANDOM-ACCESS MEMORY ARRAYMay 2023April 2025Allow2310NoNo
18316946CROSSBAR CIRCUITS UTILIZING CURRENT-MODE DIGITAL-TO-ANALOG CONVERTERSMay 2023November 2025Allow3020NoNo
18312630MEMORY DEVICE FOR PERFORMING IN-MEMORY COMPUTATION AND OPERATING METHOD THEREOFMay 2023June 2025Allow2510YesNo
18303580MEMORY CHIPApril 2023May 2025Allow2520NoNo
18301473ONE-TIME PROGRAMMABLE MEMORY CELL AND MEMORY THEREOFApril 2023January 2025Allow2100NoNo
18191986FUSE BLOCK UNIT AND FUSE BLOCK SYSTEM AND MEMORY DEVICEMarch 2023November 2024Allow1900NoNo
18123852Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier OffsetMarch 2023July 2025Abandon2810NoNo
18122758FEATURE BASED READ THRESHOLD ESTIMATION IN NAND FLASH MEMORYMarch 2023June 2025Allow2710YesNo
18119180THREE-DIMENSIONAL NON-VOLATILE MEMORY FLOORPLAN ARCHITECTUREMarch 2023April 2025Allow2610NoNo
18180623SRAM CELL CONFIGURED TO PERFORM MULTIPLY-ACCUMULATE (MAC) OPERATION ON MULTI-BIT DATA BASED ON CHARGE SHARING AND METHOD OF OPERATING THE SAMEMarch 2023March 2025Allow2410YesNo
18168943SRAM WITH IMPROVED WRITE PERFORMANCE AND WRITE OPERATION METHOD THEREOFFebruary 2023February 2025Allow2410NoNo
18163861CIRCUIT AND METHOD FOR DATA PROCESSING, AND SEMICONDUCTOR MEMORYFebruary 2023July 2025Allow3020NoNo
18099808NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING READ OPERATION OF THE SAMEJanuary 2023September 2025Allow3220YesNo
18154937BIAS GENERATION CIRCUIT AND MEMORY CIRCUITJanuary 2023October 2024Allow2100NoNo
18093646SELECTION OF READ OFFSET VALUES IN A MEMORY SUB-SYSTEM BASED ON TEMPERATURE AND TIME TO PROGRAM LEVELSJanuary 2023October 2023Allow1010NoNo
18150155Low Power Memory System Using Dual Input-Output Voltage SuppliesJanuary 2023September 2023Allow910NoNo
18080696RESISTIVE RANDOM ACCESS MEMORY DEVICEDecember 2022October 2023Allow1010NoNo
18073751MEMORY DEVICE FOR EFFECTIVELY CHECKING PROGRAM STATE AND OPERATION METHOD THEREOFDecember 2022November 2024Allow2310NoNo
17994907SOURCE BIAS TEMPERATURE COMPENSATION FOR READ AND PROGRAM VERIFY OPERATIONS ON A MEMORY DEVICENovember 2022February 2025Allow2720NoNo
17989168MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A MEMORY SUB-SYSTEMNovember 2022August 2023Allow910NoNo
17988081SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICENovember 2022August 2023Allow910YesNo
17987435MEMORY SYSTEMNovember 2022December 2024Allow2510NoNo
17967778Superconductive Memory Cells and DevicesOctober 2022December 2023Allow1410NoNo
17964718SEMICONDUCTOR DEVICE FOR EXECUTING A SMART REFRESH OPERATION AND A SMART REFRESH METHODOctober 2022September 2024Allow2300NoNo
17937532LATCH CIRCUITS WITH IMPROVED SINGLE EVENT UPSET IMMUNITY AND RELATED SYSTEMS, APPARATUSES, AND METHODSOctober 2022January 2024Allow1510NoNo
17952248Multi-Output Look-Up Table (LUT) for Use in Coarse-Grained Field-Programmable-Gate-Array (FPGA) Integrated-Circuit (IC) ChipSeptember 2022October 2025Allow3720NoNo
17932694INTEGRATED CIRCUIT COMPRISING A NON-VOLATILE MEMORYSeptember 2022August 2024Allow2310NoNo
17941719DATA OUTPUT CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAMESeptember 2022July 2024Allow2200NoNo
17902279MEMORY SYSTEM CONTROLLING NONVOLATILE MEMORYSeptember 2022May 2024Allow2000NoNo
17902754SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEMSeptember 2022October 2024Allow2610NoNo
17896929SEMICONDUCTOR MEMORY DEVICEAugust 2022June 2024Allow2200NoNo
17896963CASCODED SENSE AMPLIFIERS FOR SELF-SELECTING MEMORYAugust 2022January 2025Allow2920NoNo
17891858SRAM POWER SWITCHING WITH REDUCED LEAKAGE, NOISE REJECTION, AND SUPPLY FAULT TOLERANCEAugust 2022April 2024Allow2000NoNo
17883607INTEGRATED CIRCUIT AND OPERATION METHOD AND INSPECTION METHOD THEREOFAugust 2022August 2024Allow2510NoNo
17878200PROGRAMMING AND READING CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORYAugust 2022August 2024Allow2410NoNo
17815358Josephson Static Random Access MemoryJuly 2022July 2024Allow2310NoNo
17814790APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAMEJuly 2022February 2024Allow1820YesNo
17870714INTELLIGENT CHARGE PUMP ARCHITECTURE FOR FLASH ARRAYJuly 2022September 2023Allow1410NoNo
17861424Data transmission apparatus and method having clock gating mechanismJuly 2022April 2024Allow2100NoNo
17861233STRATEGIC MEMORY CELL RELIABILITY MANAGEMENTJuly 2022June 2024Allow2310YesNo
17860690MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICESJuly 2022March 2024Allow2000NoNo
17860607MEMORY CIRCUIT COMPRISING A PLURALITY OF 1T1R MEMORY CELLSJuly 2022March 2024Allow2000NoNo
17857942VOLTAGE BIN BOUNDARY CALIBRATION AT MEMORY DEVICE POWER UPJuly 2022August 2023Allow1310NoNo
17843084MEMORY DEVICEJune 2022January 2025Allow3110NoNo
17840213SEMICONDUCTOR MEMORY DEVICEJune 2022February 2024Allow2000NoNo
17837744READ TECHNIQUES TO REDUCE READ ERRORS IN A MEMORY DEVICEJune 2022February 2024Allow2000NoNo
17837903STATE LOOK AHEAD QUICK PASS WRITE ALGORITHM TO TIGHTEN ONGOING NATURAL THRESHOLD VOLTAGE OF UPCOMING STATES FOR PROGRAM TIME REDUCTIONJune 2022January 2024Allow1900NoNo
17831332PRE-DECODER CIRCUITYJune 2022January 2024Allow2000NoNo
17745852MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEMMay 2022April 2023Allow1110NoNo
17738088Write Driver Boost Circuit for Memory CellsMay 2022September 2023Allow1620NoNo
17731529APPARATUSES AND METHODS FOR ACCESS BASED REFRESH OPERATIONSApril 2022June 2024Allow2610NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner DINH, MINH D.

Strategic Value of Filing an Appeal

Total Appeal Filings
1
Allowed After Appeal Filing
0
(0.0%)
Not Allowed After Appeal Filing
1
(100.0%)
Filing Benefit Percentile
6.3%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 0.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the bottom 25% across the USPTO, indicating that filing appeals is less effective here than in most other areas.

Strategic Recommendations

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner DINH, MINH D - Prosecution Strategy Guide

Executive Summary

Examiner DINH, MINH D works in Art Unit 2827 and has examined 355 patent applications in our dataset. With an allowance rate of 96.9%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 17 months.

Allowance Patterns

Examiner DINH, MINH D's allowance rate of 96.9% places them in the 87% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by DINH, MINH D receive 1.21 office actions before reaching final disposition. This places the examiner in the 15% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by DINH, MINH D is 17 months. This places the examiner in the 97% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -0.9% benefit to allowance rate for applications examined by DINH, MINH D. This interview benefit is in the 11% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 46.0% of applications are subsequently allowed. This success rate is in the 96% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 71.0% of cases where such amendments are filed. This entry rate is in the 92% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 95% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 93% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 26.7% are granted (fully or in part). This grant rate is in the 14% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.6% of allowed cases (in the 61% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.7% of allowed cases (in the 66% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.