USPTO Examiner PHAM LY D - Art Unit 2827

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19261799SYSTEMS AND METHODS FOR IMPLEMENTING A FEEDBACK-INFORMED MEMORY PROGRAMMING OF AN INTEGRATED CIRCUITJuly 2025September 2025Allow200YesNo
18815802MEMORY DEVICE AND INTERNAL VOLTAGE MEASURING METHOD THEREOFAugust 2024March 2026Allow1800NoNo
18801328READING VOLTAGE MANAGEMENT METHOD AND STORAGE DEVICEAugust 2024February 2026Allow1800NoNo
18784022ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINESJuly 2024March 2026Allow1900NoNo
18768806SECOND READ INITIALIZATION ON LATCH-LIMITED MEMORY DEVICEJuly 2024February 2026Allow1910NoNo
18758749APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGSJune 2024March 2026Allow2000NoNo
18757857SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICESJune 2024February 2026Allow2000NoNo
18757422SELECTIVE USE OF A WORD LINE MONITORING PROCEDURE FOR RELIABILITY-RISK WORD LINESJune 2024March 2026Allow2010YesNo
18749367MEMORY DEVICEJune 2024February 2026Allow2000NoNo
18747448STACKED SEMICONDUCTOR DEVICEJune 2024January 2026Allow1900NoNo
18743997RRAM CIRCUIT AND METHODJune 2024January 2025Allow700NoNo
18735522MEMORY DEVICE AND COMPUTATION METHOD THEREOFJune 2024December 2025Allow1900NoNo
18734404WORD LINE DRIVER INCLUDING WORD LINE VOLTAGE-CONTROLLED PROTECTION TRANSISTORJune 2024November 2025Allow1800NoNo
18731557IN-MEMORY COMPUTATION DEVICE FOR PERFORMING A SIGNED MAC OPERATIONJune 2024November 2025Allow1700NoNo
18680911RAPID POWER READY SIGNALING IN A MEMORY ARRAYMay 2024February 2026Allow2110NoNo
18680504MAGNETIC MEMORY IN DUAL MODE AND AI MEMORY THEREOFMay 2024November 2025Allow1700NoNo
18676044PAGE BUFFER RELATED TO PERFORMING A PROGRAM OPERATION, MEMORY DEVICE INCLUDING A PAGE BUFFER, AND METHOD OF OPERATING THE PAGE BUFFERMay 2024February 2026Allow2001NoNo
18672190MEMORY DEVICE AND OPERATING METHOD THEREOFMay 2024January 2026Allow2001NoNo
18665545MEMORY CONTROLLER AND MEMORY DATA RECEIVING METHODMay 2024March 2026Allow2210NoNo
18641605ENABLING OR DISABLING ON-DIE ERROR-CORRECTING CODE FOR A MEMORY BUILT-IN SELF-TESTApril 2024January 2026Allow2110YesNo
18634799VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTIONApril 2024February 2026Allow2310NoNo
18629445APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSESApril 2024February 2026Allow2210YesNo
18628562MEMORY WITH PROGRAMMABLE REFRESH ORDER AND STAGGER TIMEApril 2024September 2025Allow1800NoNo
18626227SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMSApril 2024March 2025Allow1210NoNo
18618460MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICEMarch 2024April 2025Allow1210NoNo
18618754CROSS-POINT ARRAY REFRESH SCHEMEMarch 2024January 2025Allow1000NoNo
18615214HOME WIRELESS DISCOVERYMarch 2024March 2025Allow1210NoNo
18605234ENCODED READ-ONLY MEMORY AND DECODERMarch 2024February 2026Allow2310NoNo
18601810STORING ONE DATA VALUE BY PROGRAMMING A FIRST MEMORY CELL AND A SECOND MEMORY CELLMarch 2024March 2025Allow1310NoNo
18598237COMMAND-TRIGGERED DATA CLOCK DISTRIBUTION MODEMarch 2024March 2025Allow1210NoNo
18598937APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAMEMarch 2024December 2025Allow2110NoNo
18595909MEMORY DEVICE AND OPERATION THEREOFMarch 2024December 2024Allow910NoNo
18582782RAPID TAG INVALIDATION CIRCUITFebruary 2024February 2026Allow2430YesNo
18443948DIFFERENTIAL STROBE FAULT IDENTIFICATIONFebruary 2024January 2026Allow2310NoNo
18438807Tri-state electrical information storageFebruary 2024January 2025Allow1110NoNo
18439612MAGNETIC MEMORYFebruary 2024September 2025Allow1900NoNo
18437038SEMICONDUCTOR STORAGE DEVICEFebruary 2024July 2025Allow1800NoNo
18436379RISING EDGE DETECTION OF A CLOSING CYCLE FOR A MULTI-CYCLE OPERATIONFebruary 2024August 2025Allow1900NoNo
18435116Memory Circuitry And Methods Used In Forming Memory CircuitryFebruary 2024August 2025Allow1800YesNo
18434752MEMORY DEVICES, CIRCUITS AND METHODS OF ADJUSTING A SENSING CURRENT FOR THE MEMORY DEVICEFebruary 2024March 2025Allow1310NoNo
18420874TERNARY CONTENT ADDRESSABLE MEMORY AND DECISION GENERATION METHOD FOR THE SAMEJanuary 2024September 2024Allow800NoNo
18415960MEMORY DEVICE AND METHOD FOR OPERATING MEMORY DEVICEJanuary 2024July 2025Allow1800NoNo
18416770READ OPERATIONS FOR A MEMORY ARRAY AND REGISTERJanuary 2024January 2026Allow2310NoNo
18414640SENSE AMPLIFIERS AS STATIC RANDOM ACCESS MEMORY CACHEJanuary 2024December 2025Allow2310YesNo
184139592-PORT SRAM COMPRISING A CFETJanuary 2024July 2025Allow1800NoNo
18412010LOW PASS THROUGH VOLTAGE ON LOWER TIER WORDLINES FOR READ DISTURB IMPROVEMENTJanuary 2024December 2025Allow2310NoNo
18410049DIGITAL DEVICE HAVING A RESET PAD CIRCUIT THAT MAY BE SUBJECT TO HACKER ATTACKJanuary 2024November 2025Allow2301NoNo
18409241MEMORY DEVICE, AND MEMORY SYSTEM AND OPERATION METHOD THEREOFJanuary 2024December 2025Allow2310NoNo
18409430MEMORY DEVICES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMSJanuary 2024August 2025Allow1900NoNo
18409481MEMORY SYSTEMJanuary 2024August 2025Allow1900NoNo
18404225OPTIMIZATION OF SOFT BIT WINDOWS BASED ON SIGNAL AND NOISE CHARACTERISTICS OF MEMORY CELLSJanuary 2024March 2026Allow2640YesNo
18404853METHOD AND CIRCUITRY FOR HANDLING DEFECTIVE MEMORY CELLS AND WORDLINES IN MEMORY MODULEJanuary 2024October 2025Allow2210NoNo
18404742ARCHITECTURE AND METHOD FOR NAND MEMORY OPERATIONJanuary 2024March 2025Allow1420YesNo
18534689LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLSDecember 2023January 2025Allow1400NoNo
18528375TRIM SETTING DETERMINATION ON A MEMORY DEVICEDecember 2023August 2025Allow2120NoNo
18521746DEVICES, CHIPS, AND ELECTRONIC EQUIPMENT FOR SENSING-MEMORY-COMPUTING SYNERGYNovember 2023July 2025Allow2000YesNo
18519201MEMORY DEVICE AND READING METHOD THEREOFNovember 2023July 2025Allow1900NoNo
18520135MEMORY DEVICE AND METHOD FOR ADJUSTING LOGIC STATES OF DATA STROBE SIGNALS USED BY MEMORY DEVICENovember 2023August 2025Allow2110NoNo
18519051MEMORY DEVICENovember 2023October 2025Allow2301NoNo
18518035SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM CAPABLE OF PERFORMING A TRAINING OPERATIONNovember 2023January 2026Allow2620NoNo
18517400INTEGRATED CIRCUIT FIN STRUCTURENovember 2023February 2025Allow1410NoNo
18507387MEMORY READ VOLTAGE THRESHOLD TRACKING BASED ON MEMORY DEVICE-ORIGINATED METRICS CHARACTERIZING VOLTAGE DISTRIBUTIONSNovember 2023May 2025Allow1800YesNo
18505113STORAGE DEVICE ENTERING LOW POWER MODE AFTER EXECUTING BACKGROUND OPERATION AND OPERATING METHOD OF THE STORAGE DEVICENovember 2023October 2025Allow2400NoNo
18500712TRACKING OPERATIONS PERFORMED AT A MEMORY DEVICENovember 2023January 2025Allow1410NoNo
184951676T-SRAM-BASED DIGITAL COMPUTING-IN-MEMORY CIRCUITS SUPPORTING FLEXIBLE INPUT DIMENSIONOctober 2023August 2025Allow2200NoNo
18494707TECHNIQUES FOR TRANSFERRING COMMANDS TO A DYNAMIC RANDOM-ACCESS MEMORYOctober 2023March 2025Allow1710NoNo
18382659MEMORY DEVICE AND METHOD FOR ADJUSTING LOGIC STATES OF DATA STROBE SIGNALS USED BY MEMORY DEVICEOctober 2023July 2025Allow2000NoNo
18490042MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLEROctober 2023June 2024Allow810NoNo
18490148NONVOLATILE SEMICONDUCTOR MEMORY DEVICEOctober 2023September 2024Allow1100NoNo
18488641SMART COMPUTE RESISTIVE MEMORYOctober 2023March 2025Allow1710NoNo
18485277METHOD AND SYSTEM FOR DETECTING MEMORY ERROR, AND DEVICEOctober 2023April 2025Allow1900NoNo
18483578STORAGE OF THRESHOLD VOLTAGE SHIFTSOctober 2023April 2025Allow1900YesNo
18378540MEMORY DEVICE THAT PERFORMS ERASE OPERATION TO PRESERVE DATA RELIABILITYOctober 2023May 2025Allow1900NoNo
18377751VOLTAGE REGULATOR, MEMORY DEVICE INCLUDING VOLTAGE REGULATOR, AND OPERATION METHOD OF MEMORY DEVICEOctober 2023March 2026Allow2911YesNo
18479953MULTI-STEP PROGRAMMING SCHEMES FOR PROGRAMMING CROSSBAR CIRCUITSOctober 2023June 2025Allow2000NoNo
18478643SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITSSeptember 2023September 2025Allow2401YesNo
18477674ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEMSeptember 2023September 2024Allow1200NoNo
18475968BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHODSeptember 2023August 2025Allow2310NoNo
18368691One Time Programmable Memory CellSeptember 2023July 2025Allow2210NoNo
18459779REFRESH AND ACCESS MODES FOR MEMORYSeptember 2023November 2024Allow1410NoNo
18240576SEMICONDUCTOR MODULEAugust 2023January 2026Allow2900NoNo
18233474CORRECTION APPARATUS FOR ANGLE SENSOR, AND ANGLE SENSORAugust 2023July 2024Allow1110NoNo
18231769METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORKAugust 2023September 2024Allow1310NoNo
18229762METHOD OF FABRICATING SEMICONDUCTOR DEVICEAugust 2023November 2025Allow2700NoNo
18226823SEMICONDUCTOR DEVICEJuly 2023September 2024Allow1410NoNo
18360306MEMORY PROGRAM-VERIFY WITH ADAPTIVE SENSE TIME BASED ON ROW LOCATIONJuly 2023August 2025Allow2410NoNo
18358940DATA INPUT/OUTPUT DEVICE FOR PERFORMING DATA INPUT/OUTPUT OPERATION USING PIPE CIRCUITJuly 2023May 2025Allow2200NoNo
18359395STATIC RANDOM-ACCESS MEMORY (SRAM) DEVICE AND RELATED SRAM-BASED COMPUTE-IN-MEMORY DEVICESJuly 2023May 2025Allow2200NoNo
18358587MEMORY SYSTEMJuly 2023September 2024Allow1410NoNo
18357769SERIES OF PARALLEL SENSING OPERATIONS FOR MULTI-LEVEL CELLSJuly 2023December 2024Allow1710NoNo
18357450NON-VOLATILE MEMORY WITH SUB-BLOCKSJuly 2023September 2025Allow2610NoNo
18225572SEMICONDUCTOR ELEMENT MEMORY DEVICEJuly 2023April 2025Allow2100NoNo
18355348APPARATUS AND METHOD FOR DETECTING NEIGHBOR PLANE ERASE FAILURESJuly 2023April 2025Allow2100NoNo
18349093SYSTEM RECOVERY DURING CGI-WL DEFECTJuly 2023April 2025Allow2200NoNo
18348716FLEXIBLE METADATA ALLOCATION AND CACHINGJuly 2023May 2025Allow2200NoNo
18342517SEMICONDUCTOR DEVICES PROVIDING TEST MODE RELATED TO RELIABILITYJune 2023November 2025Allow2811NoNo
18333756MEMORY DEVICE INCLUDING SENSE AMPLIFYING CIRCUITJune 2023March 2025Allow2100NoNo
18266610CONVOLUTION OPERATION ACCELERATOR AND CONVOLUTION OPERATION METHODJune 2023March 2025Allow2100NoNo
18208103SYSTEMS AND TECHNIQUES FOR ACCESSING MULTIPLE MEMORY CELLS CONCURRENTLYJune 2023November 2024Allow1710NoNo
18332706REFRESH ADDRESS GENERATION CIRCUIT AND METHOD, MEMORY, AND ELECTRONIC DEVICEJune 2023March 2025Allow2100NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PHAM, LY D.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
3
Examiner Affirmed
2
(66.7%)
Examiner Reversed
1
(33.3%)
Reversal Percentile
52.8%
Higher than average

What This Means

With a 33.3% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
17
Allowed After Appeal Filing
8
(47.1%)
Not Allowed After Appeal Filing
9
(52.9%)
Filing Benefit Percentile
75.9%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 47.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner PHAM, LY D - Prosecution Strategy Guide

Executive Summary

Examiner PHAM, LY D works in Art Unit 2827 and has examined 1,732 patent applications in our dataset. With an allowance rate of 95.3%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 18 months.

Allowance Patterns

Examiner PHAM, LY D's allowance rate of 95.3% places them in the 84% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by PHAM, LY D receive 0.92 office actions before reaching final disposition. This places the examiner in the 7% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PHAM, LY D is 18 months. This places the examiner in the 96% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +2.6% benefit to allowance rate for applications examined by PHAM, LY D. This interview benefit is in the 23% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 39.2% of applications are subsequently allowed. This success rate is in the 89% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 45.4% of cases where such amendments are filed. This entry rate is in the 69% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 54.5% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 47% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 83.3% of appeals filed. This is in the 76% percentile among all examiners. Of these withdrawals, 53.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 42.2% are granted (fully or in part). This grant rate is in the 34% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 14.9% of allowed cases (in the 96% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.5% of allowed cases (in the 65% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.