USPTO Examiner LAPPAS JASON - Art Unit 2827

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18824515APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKINGSeptember 2024March 2026Allow1800NoNo
18822985BITLINE SENSE AMPLIFIERS AND SEMICONDUCTOR DEVICES INCLUDING THE SAMESeptember 2024March 2026Allow1800NoNo
18796143MEMORY WITH DOUBLE REDUNDANCYAugust 2024March 2026Allow1900NoNo
18791722MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SYSTEMAugust 2024February 2026Allow1900NoNo
18789680SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CIRCUITRYJuly 2024February 2026Allow1800NoNo
18787812CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALINGJuly 2024February 2026Allow1900NoNo
18787957USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCKS IN A MEMORY DEVICEJuly 2024January 2026Allow1800NoNo
18788001CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICESJuly 2024February 2026Allow1800NoNo
18781317PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICESJuly 2024January 2026Allow1800NoNo
18771536ELECTRICAL FUSE BIT CELL IN INTEGRATED CIRCUIT HAVING BACKSIDE CONDUCTING LINESJuly 2024February 2026Allow1900NoNo
18771019SEMICONDUCTOR DEVICEJuly 2024December 2025Allow1700NoNo
18770632MANAGING PROGRAM DISTURB IN MEMORY DEVICESJuly 2024January 2026Allow1800NoNo
18768970SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING USING GATE INDUCED DRAIN LEAKAGEJuly 2024December 2025Allow1700NoNo
18765358NON-VOLATILE MEMORY WITH AUXILIARY SELECT GATE LINE DRIVERJuly 2024December 2025Allow1700NoNo
18765076WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICESJuly 2024January 2025Allow700NoNo
18755033DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICESJune 2024January 2025Allow700NoNo
18753094NON-VOLATILE MEMORY AND CORRESPONDING MANUFACTURING METHODJune 2024December 2025Allow1700NoNo
18752870NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL ARRAY AND A CONTROL CIRCUIT APPLYING A READING VOLTAGEJune 2024February 2025Allow700NoNo
18750641MEMORY, OPERATION METHOD OF MEMORY, AND MEMORY SYSTEMJune 2024January 2026Allow1900NoNo
18751094Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell ArrayJune 2024January 2026Allow1900NoNo
18741780MEMORY DEVICE AND DATA ACCESSING METHOD THEREOFJune 2024February 2026Allow2000NoNo
18680395On-Die Termination of Address and Command SignalsMay 2024January 2025Allow700NoNo
18677727MEMORY SYSTEM, CONTROL METHOD THEREOF, AND PROGRAMMay 2024December 2025Allow1800NoNo
18675257MEMORY SYSTEM AND MEMORY DEVICEMay 2024January 2025Allow700NoNo
18663879DISCHARGE CIRCUITS FOR A NAND FLASH MEMORYMay 2024July 2025Allow1400NoNo
18664199PROGRAMMING TECHNIQUES FOR POLARITY-BASED MEMORY CELLSMay 2024January 2025Allow800NoNo
18662709ONON Sidewall Structure for Memory Device and Method for Making the SameMay 2024December 2024Allow700NoNo
18662971SEMICONDUCTOR MEMORY DEVICEMay 2024December 2024Allow700NoNo
18661300AUTO-REFERENCED MEMORY CELL READ TECHNIQUESMay 2024December 2024Allow700NoNo
18653627NON-VOLATILE MEMORY DEVICES INCLUDING TWISTED BLOCK SELECT LINESMay 2024September 2025Allow1700NoNo
18651261SMART PROLOGUE FOR NONVOLATILE MEMORY PROGRAM OPERATIONApril 2024November 2024Allow700NoNo
18651510THREE-DIMENSIONAL NOR MEMORY ARRAY OF THIN-FILM FERROELECTRIC MEMORY TRANSISTORS IMPLEMENTING PARTIAL POLARIZATIONApril 2024September 2025Allow1700NoNo
18646059MEMORY COMPONENT WITH PROGRAMMABLE DATA-TO-CLOCK RATIOApril 2024November 2024Allow600NoNo
18643119DEVICE MODE TO IMPROVE DATA RETENTION FOR NAND MLC TECHNOLOGYApril 2024October 2025Allow1800NoNo
18637829MEMORY DEVICES HAVING BUILT-IN POWER SUPPORTING CONTROL CIRCUITS THAT PROVIDE INCREASED PROGRAM AND READ RELIABILITYApril 2024September 2025Allow1700NoNo
18632304MEMORY DEVICEApril 2024December 2025Allow2000NoNo
18631556SEMICONDUCTOR MEMORY DEVICEApril 2024November 2025Allow1900NoNo
18629205MEMORY ARRAY OF THREE-DIMENSIONAL NOR MEMORY STRINGS WITH WORD LINE SELECT DEVICEApril 2024September 2025Allow1700NoNo
18604411BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICEMarch 2024August 2025Allow1800NoNo
18602974SUB-BLOCK DEFINITION IN A MEMORY DEVICE USING SEGMENTED SOURCE PLATESMarch 2024August 2025Allow1800NoNo
18602709MEMORY DEVICE INCLUDING CHARGE PUMP, AND OPERATION METHOD OF THE MEMORY DEVICEMarch 2024August 2025Allow1800NoNo
18596150CELL CYCLING TO MINIMIZE RESISTIVE MEMORY RANDOM NUMBER CORRELATIONMarch 2024September 2024Allow600NoNo
18595188MEMORY AND OPERATING METHOD THEREOFMarch 2024September 2024Allow700NoNo
18593979SEMICONDUCTOR DEVICEMarch 2024November 2025Allow2000NoNo
18443500MEMORY CELLFebruary 2024September 2025Allow1900NoNo
18443992METHODS TO IMPROVE CURRENT CONSUMPTION AND READ TIME IN SUCCESSIVE READSFebruary 2024August 2025Allow1800NoNo
18443010ERASE OPERATIONS IN MEMORY DEVICESFebruary 2024August 2025Allow1800NoNo
18435089THREE-DIMENSIONAL MEMORY ARRAY, MEMORY SEARCHING ENGINE CIRCUIT AND ENCODING METHOD OF THE SAMEFebruary 2024November 2025Allow2100NoNo
18433421VOLTAGE CONTROL CIRCUIT MODULE, MEMORY STORAGE DEVICE AND VOLTAGE CONTROL METHODFebruary 2024July 2025Allow1800NoNo
18431582SUB-BLOCK SEPARATION IN NAND MEMORY THROUGH WORD LINE BASED SELECTORSFebruary 2024July 2025Allow1800NoNo
18413596SEMICONDUCTOR DEVICE INCLUDING CHARGE RETENTION NODEJanuary 2024September 2025Allow2000NoNo
18408680SEMICONDUCTOR DEVICEJanuary 2024November 2025Allow2200NoNo
18405940MEMORY DEVICES WITH DUAL-SIDE ACCESS CIRCUITS AND METHODS FOR OPERATING THE SAMEJanuary 2024July 2025Allow1800NoNo
18393067CURRENT MONITORING IN A MEMORY DEVICE TO IMPROVE SHORT DETECTIONDecember 2023October 2025Allow2200NoNo
18544032MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMSDecember 2023August 2025Allow2000NoNo
18542206MEMORY DEVICES, MEMORY SYSTEMS, AND METHODS FOR OPERATING MEMORY DEVICESDecember 2023July 2025Allow1900NoNo
18533007DOUBLE PROGRAM DEBUG METHOD FOR NAND MEMORY USING SELF-VERIFICATION BY INTERNAL FIRMWAREDecember 2023September 2024Allow900NoNo
18531588Stochastic Memristive Devices Based on Arrays of Magnetic Tunnel JunctionsDecember 2023July 2025Allow2000NoNo
18529115MULTI-WRITE READ-ONLY MEMORY ARRAYDecember 2023June 2025Allow1900NoNo
18529175REFRESH OPERATIONS IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS)December 2023June 2025Allow1900NoNo
18521063MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICENovember 2023June 2025Allow1900NoNo
18519156INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR OPERATING THE SAMENovember 2023June 2025Allow1900NoNo
18515975MEMORY CONFIGURED TO PERFORM A CHANNEL PRECHARGE OPERATION AND METHOD OF OPERATING THE MEMORYNovember 2023June 2025Allow1900NoNo
18513319METHODS FOR ROW HAMMER MITIGATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAMENovember 2023July 2024Allow800NoNo
18509708VARIABLE FOGGY VERIFY LEVELS FOR SELECTED CHECKPOINT STATES FOR NON-VOLATILE MEMORY APPARATUSESNovember 2023August 2025Allow2100NoNo
18499797SUB-BLOCK SEPARATION IN NAND MEMORY THROUGH WORD LINE BASED SELECTORSNovember 2023September 2025Allow2300NoNo
18496660SINGLE-LEVEL CELL PROGRAMMING WITH ADAPTIVE WORDLINE RAMP RATEOctober 2023May 2025Allow1900NoNo
18494769MEMORY DEVICE PERMITTING OVERWRITE PROGRAM OPERATION AND OPERATION METHOD THEREOFOctober 2023May 2025Allow1900NoNo
18491452MEMORY, OPERATION METHODS THEREOF AND MEMORY SYSTEMSOctober 2023February 2026Allow2810YesNo
18489394MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICEOctober 2023August 2025Allow2200NoNo
18489674ELECTRICAL FUSE BIT CELL IN INTEGRATED CIRCUIT HAVING BACKSIDE CONDUCTING LINESOctober 2023May 2024Allow600NoNo
18488040INTEGRATED CIRCUIT AND MEMORY DEVICE INCLUDING SAMPLING CIRCUITOctober 2023June 2024Allow800NoNo
18479330TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTRATE AND PACKAGE SUBSTRATEOctober 2023May 2024Allow700NoNo
18477456METHOD OF PROGRAMMING FLASH MEMORYSeptember 2023May 2025Allow1900NoNo
18474619MEMORY DEVICE AND OPERATING METHOD FOR MEMORY DEVICESeptember 2023August 2025Allow2200NoNo
18467793NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL ARRAY AND A CONTROL CIRCUIT APPLYING A READING VOLTAGESeptember 2023April 2024Allow700NoNo
18468078SEMICONDUCTOR INTEGRATED CIRCUITSeptember 2023April 2024Allow700NoNo
18368446MEMORY DEVICE AND PRECHARGING METHOD THEREOFSeptember 2023June 2025Allow2100NoNo
18464383METHOD OF PROGRAMMING DATA IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAMESeptember 2023April 2025Allow1900NoNo
18462433MEMORY DEVICE FOR PERFORMING ERASE VERIFY OPERATION ON CELL STRING GROUP BASIS AND METHOD OF OPERATING THE SAMESeptember 2023June 2025Allow2100NoNo
18242232MEMORY DEVICE AND OPERATING METHOD THEREOFSeptember 2023April 2025Allow1900NoNo
18459501MEMORY SYSTEMSeptember 2023March 2024Allow700NoNo
18460496SEMICONDUCTOR STORAGE DEVICESeptember 2023October 2025Allow2500NoNo
18237815DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAYAugust 2023May 2025Allow2000NoNo
18452563METHOD OF PROGRAMMING MEMORYAugust 2023May 2025Allow2000NoNo
18451182MEMORY SYSTEM AND MEMORY DEVICEAugust 2023February 2024Allow600NoNo
18450413MEMORY DEVICE FOR STORING PLURALITY OF DATA BITS AND METHOD OF OPERATING THE SAMEAugust 2023September 2025Allow2501NoNo
18234356VOLTAGE REGULATION FOR MULTIPLE VOLTAGE LEVELSAugust 2023April 2024Allow800NoNo
18234289LOW STRESS REFRESH ERASE IN A MEMORY DEVICEAugust 2023April 2025Allow2000NoNo
18365929MEMORY SYSTEM, CONTROL METHOD THEREOF, AND PROGRAMAugust 2023February 2024Allow700NoNo
18229978SMART EARLY PROGRAM TERMINATION ALGORITHM FOR NEIGHBOR PLANE DISTURB COUNTERMEASUREAugust 2023March 2025Allow2000NoNo
18359764SEMICONDUCTOR MEMORY DEVICEJuly 2023February 2024Allow700NoNo
18225253ON-CHIP PERFORMANCE THROTTLINGJuly 2023March 2025Allow2000NoNo
18355343APPARATUS AND METHODS FOR SMART VERIFY WITH ADAPTIVE VOLTAGE OFFSETJuly 2023March 2025Allow2000NoNo
18353290MEMORY CELL WITH UNIPOLAR SELECTORSJuly 2023September 2024Allow1400NoNo
18351992THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAMEJuly 2023May 2025Allow2210NoNo
18352025THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAMEJuly 2023May 2025Allow2210NoNo
18346867HIGH VOLTAGE SWITCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAMEJuly 2023October 2024Abandon1510NoNo
18216513LOW POWER MEMORY CONTROL WITH ON-DEMAND BANDWIDTH BOOSTJune 2023January 2024Allow700NoNo
18214466On-Die Termination of Address and Command SignalsJune 2023January 2024Allow700NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner LAPPAS, JASON.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
4
Examiner Affirmed
3
(75.0%)
Examiner Reversed
1
(25.0%)
Reversal Percentile
40.0%
Lower than average

What This Means

With a 25.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
29
Allowed After Appeal Filing
12
(41.4%)
Not Allowed After Appeal Filing
17
(58.6%)
Filing Benefit Percentile
68.9%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 41.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner LAPPAS, JASON - Prosecution Strategy Guide

Executive Summary

Examiner LAPPAS, JASON works in Art Unit 2827 and has examined 1,142 patent applications in our dataset. With an allowance rate of 95.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.

Allowance Patterns

Examiner LAPPAS, JASON's allowance rate of 95.1% places them in the 84% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by LAPPAS, JASON receive 0.69 office actions before reaching final disposition. This places the examiner in the 4% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by LAPPAS, JASON is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +3.4% benefit to allowance rate for applications examined by LAPPAS, JASON. This interview benefit is in the 26% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 37.4% of applications are subsequently allowed. This success rate is in the 85% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 29.7% of cases where such amendments are filed. This entry rate is in the 43% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 120.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 82% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 85.7% of appeals filed. This is in the 79% percentile among all examiners. Of these withdrawals, 66.7% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 19.8% are granted (fully or in part). This grant rate is in the 10% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 6.1% of allowed cases (in the 88% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.2% of allowed cases (in the 52% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.