USPTO Art Unit 2892 Prosecution Statistics

Art Unit Information

Art Unit: 2892
Group: 2890
Tech Center: 2800
Total Cases: 15,388
Last Active: January 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19022335MICROCHANNEL HEAT SINK WITH TPMS FINNED STRUCTURES FOR ENHANCED THERMAL EFFICIENCYJanuary 2025October 2025Allow910NoNo
18923340SEMICONDUCTOR DEVICEOctober 2024February 2025Allow400NoNo
18886547HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUITSeptember 2024February 2025Allow510YesNo
18884507DISPLAY APPARATUS HAVING A PIXEL DEFINING LAYER WITH OVERHANG STRUCTURESeptember 2024October 2025Allow1320YesNo
18826732OLED SUB-PIXEL CIRCUIT ARCHITECTURE AND RELATED METHODSSeptember 2024August 2025Allow1120YesNo
18789496SEMICONDUCTOR PACKAGE WITH STIFFENER STRUCTURE AND METHOD OF MANUFACTURING THE SAMEJuly 2024October 2025Allow1400NoNo
18783980PACKAGE ASSEMBLY INCLUDING LIQUID ALLOY THERMAL INTERFACE MATERIAL (TIM) AND SEAL RING AROUND THE LIQUID ALLOY TIM AND METHODS OF FORMING THE SAMEJuly 2024October 2025Allow1510NoNo
18771543SEMICONDUCTOR DEVICEJuly 2024January 2026Allow1810NoNo
18770232POWER MODULE WITH IMPROVED CONDUCTIVE PATHSJuly 2024October 2025Allow1500YesNo
18768963SEMICONDUCTOR DEVICE INCLUDING LOWER SEMICONDUCTOR PACKAGE HAVING HEAT SINCE PATTERNJuly 2024January 2026Allow1810NoNo
18767481SEAL RING STRUCTURE IN THE PERIPHERAL OF DEVICE DIES AND WITH ZIGZAG PATTERNS AND METHOD FORMING SAMEJuly 2024September 2025Allow1510NoNo
18762979DISPLAY SUBSTRATE OF EVEN-DISTRIBUTED LIGHT EMITTING DEVICES, DISPLAY PANEL AND DISPLAY DEVICEJuly 2024February 2026Allow1910NoNo
18763447LIGHT EMITTING DEVICE HAVING A STACKED STRUCTUREJuly 2024October 2025Allow1500NoNo
18762511DISPLAY PANEL WITH IMPROVED LUMINANCE OR EFFICIENCY AND DISPLAY DEVICE COMPRISING THE SAMEJuly 2024February 2026Allow1910NoNo
18750305OLED PIXEL STRUCTURESJune 2024November 2025Allow1731YesNo
18750067DISPLAY DEVICE INCLUDING CONNECTION WIRING PART LATERALLY ADJACENT TO DRIVING VOLTAGE WIRINGJune 2024February 2025Allow800YesNo
18750096DISPLAY DEVICE WITH SECOND INITIALIZATION VOLTAGE LINE FORMING OPENINGSJune 2024May 2025Allow1000NoNo
18746509ARRAY SUBSTRATE WITH OVERLAPPING ACTIVE LAYERS HAVING CHANNEL WIDTH GREATER THAN GATE WIDTH, METHOD FOR PREPARING THE SAME, AND DISPLAY PANELJune 2024March 2025Allow820NoNo
18746747HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHODJune 2024October 2024Allow410YesNo
18744244CONDUCTIVE OXIDE OVERHANG STRUCTURES FOR OLED DEVICESJune 2024March 2025Allow900NoNo
18743155METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING AN AIR GAP BETWEEN A CONTACT PAD AND A SIDEWALL OF CONTACT HOLEJune 2024May 2025Allow1100NoNo
18742204DIE SIDEWALL COATINGS AND RELATED METHODSJune 2024April 2025Allow1000YesNo
18741771DISPLAY DEVICE HAVING A CONDUCTIVE METAL LAYER DISPOSED ON A SURFACE OF AN ANTIREFLECTION LAYERJune 2024April 2025Allow1000NoNo
18741440DISPLAY DEVICE CONFIGURED TO PREVENT PROPAGATION OF CRACKS, AND METHOD OF REPAIRING SAMEJune 2024January 2025Allow800YesNo
18739366THREE DIMENSIONAL MIM CAPACITOR HAVING A COMB STRUCTURE AND METHODS OF MAKING THE SAMEJune 2024November 2025Allow1710NoNo
18736777Semiconductor Device and Method for Manufacturing the SameJune 2024April 2025Allow1000NoNo
18735194PACKAGE STRUCTURE WITH BRIDGE DIE AND METHOD OF FORMING THE PACKAGE STRUCTUREJune 2024January 2026Allow1920NoNo
18735864INTEGRATED ASSEMBLIES WHICH INCLUDE STACKED MEMORY DECKS, AND METHODS OF FORMING INTEGRATED ASSEMBLIESJune 2024May 2025Allow1100NoNo
18732345METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYSJune 2024December 2024Allow600YesNo
18677617DISPLAY SUBSTRATE WITH PIXEL OPENING AREAS, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICEMay 2024April 2025Allow1100NoNo
18673615FIN FIELD-EFFECT TRANSISTOR DEVICE HAVING HYBRID WORK FUNCTION LAYER STACKMay 2024December 2024Allow700NoNo
18673596FET WITH WRAP-AROUND SILICIDE AND FABRICATION METHODS THEREOFMay 2024June 2025Allow1210NoNo
18672109LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICEMay 2024April 2025Allow1010NoNo
18672001METHOD OF FABRICATING PACKAGE STRUCTURE INCLUDING A PLURALITY OF ANTENNA PATTERNSMay 2024May 2025Allow1210NoNo
18672877SOLDERABLE AND WIRE BONDABLE PART MARKINGMay 2024January 2026Allow2010NoNo
18668400DISPLAY DEVICE HAVING ADHESIVE MEMBER AT FOLDING AREAMay 2024January 2025Allow700NoNo
18669033DEVICE CHIP SCALE PACKAGE INCLUDING A PROTECTIVE LAYER AND METHOD OF MANUFACTURING A DEVICE CHIP SCALE PACKAGEMay 2024April 2025Allow1110NoNo
18667449METHOD OF FORMING TOP SELECT GATE TRENCHESMay 2024September 2025Allow1610YesNo
18665836METHOD OF MAKING A DISPLAY APPARATUS USING A SELECTIVE MASK STRUCTUREMay 2024August 2025Allow1520YesNo
18665846MANUFACTURING METHOD FOR DISPLAY DEVICE INCLUDING PAD ELECTRODEMay 2024September 2025Allow1600NoNo
18666787OPTOELECTRONIC DEVICE INCLUDING PHOTODIODE HAVING BURIED LAYER WITH DIFFERENT THICKNESSESMay 2024October 2024Allow510NoNo
18663697SEMICONDUCTOR PACKAGE INCLUDING AN INTEGRATED CIRCUIT DIE AND AN INDUCTOR OR A TRANSFORMERMay 2024November 2025Allow1811NoNo
18655640SEMICONDUCTOR NANOSTRUCTURES DEVICE STRUCTURE WITH BACKSIDE CONTACTMay 2024December 2024Allow700YesNo
18655596PACKAGE STRUCTUREMay 2024June 2025Allow1310NoNo
18654125PACKAGED SEMICONDUCTOR DEVICES WITH LEADFRAMES HAVING TIE BAR WITH RECESSED CAVITYMay 2024August 2025Allow1510NoNo
18655016DISPLAY DEVICE HAVING AUXILIARY LINESMay 2024March 2025Allow1010NoNo
18654383Microfluidic Chip Having Grounding Trace and Manufacturing Method Thereof, and Microfluidic DeviceMay 2024March 2025Allow1110NoNo
18653289Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated AssembliesMay 2024June 2025Allow1310NoNo
18652779PACKAGE STRUCTURE INCLUDING A DIE HAVING A TAPER-SHAPED DIE CONNECTORMay 2024July 2025Allow1410NoNo
18651194DRIVE CIRCUIT ARRAY SUBSTRATE INCLUDING WELL TAPS PROVIDED IN SUBSET THEREOF, DISPLAY DEVICE, AND ELECTRONIC APPARATUSApril 2024November 2024Allow700YesNo
18650143PACKAGE STRUCTURE HAVING A DEVICE INSIDE A MOLDING MEMBER AND METHOD OF FORMING THE PACKAGE STRUCTUREApril 2024August 2025Allow1520NoNo
18648758DEVICE WITH A MULTIZONE REFLECTOR HAVING A DISCREET OPENING FOR A SENSORApril 2024July 2025Allow1410NoNo
18648513METHOD FOR FORMING SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE AND RECYCLE SUBSTRATEApril 2024October 2025Allow1820NoNo
18645403DISPLAY SUBSTRATE INCLUDING CONNECTION LINE AND POWER LINE SURROUNDING DISPLAY AREA, PREPARATION METHOD THEREOF, AND DISPLAY DEVICEApril 2024August 2025Allow1610NoNo
18643322SEMICONDUCTOR DEVICE INCLUDING A MEMORY STACK AND A CONTACT STRUCTURE IN A SPACER STRUCTUREApril 2024September 2025Allow1730YesNo
18642214Semiconductor Package With EMI Shield and Fabricating Method ThereofApril 2024November 2024Allow700NoNo
18637063DISPLAY APPARATUS WITH PENETRATING PORTION AND METHOD OF MANUFACTURING SAMEApril 2024March 2025Allow1100YesNo
18636446SEMICONDUCTOR DEVICE INCLUDING DETECTION ELECTRODES APPLICABLE FOR A TOUCH SENSORApril 2024July 2025Allow1510NoNo
18635186INTEGRATION OF SEMICONDUCTOR DEVICE ASSEMBLIES WITH THERMAL DISSIPATION MECHANISMSApril 2024March 2025Allow1100NoNo
18635613Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery NetworkApril 2024November 2025Allow1920YesNo
18635592SEMICONDUCTOR DEVICE STRUCTURE HAVING A METAL LAYER POSITIONED UNDER THE SEMICONDUCTOR SUBSTRATEApril 2024January 2026Allow2100NoNo
18633183SEMICONDUCTOR APPARATUS INCLUDING COOLER FOR COOLING SEMICONDUCTOR ELEMENTApril 2024June 2025Allow1410NoNo
18632642WARPAGE CONTROL OF PACKAGES USING EMBEDDED CORE FRAMEApril 2024July 2025Allow1520NoNo
18631532DISPLAY PANEL AND DISPLAY DEVICE WITH SYMMETRICALLY ARRANGED STRUCTURES CORRESPONDING TO SAME-COLOR LIGHT-EMITTING UNITSApril 2024March 2025Allow1110YesNo
18630503ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING REDUCED COMPENSATED STEP FROM ELECTRODE LINES TO PREVENT CRACKING OF ENCAPSULATION LAYERApril 2024February 2025Allow1110NoNo
18630530SUPERCONDUCTING DEVICE INDLUDING SET OF CIRCUITS HAVING DIFFERENT OPERATIONAL TEMPERATURE REQUIREMENTS WITH MULTIPLE THERMAL SINKS AND MULTIPLE GROUND PLANESApril 2024January 2025Allow900NoNo
18628629DISPLAY PANEL WITH PARTITION WALL AND METAL LAYERS IN NON-DISPLAY AREAApril 2024March 2025Allow1110NoNo
18628242MANUFACTURING METHOD FOR REDUCING SURFACE STEP OF A PASSIVATION LAYERApril 2024February 2026Allow2310NoNo
18628233SEMICONDUCTOR DEVICE WITH VERTICAL PATTERNS AND DATA STORAGE SYSTEM INCLUDING THE SAMEApril 2024April 2025Allow1210NoNo
18626348DISPLAY APPARATUS WITH LOAD MATCHING DEVICE NEAR OPENINGS IN NON-DISPLAY AREAApril 2024March 2025Allow1110NoNo
18623992SEMICONDUCTOR DEVICE INCLUDING THROUGH DIE VIAApril 2024March 2025Allow1200YesNo
18620993ENCAPSULATION WARPAGE REDUCTION FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMSMarch 2024August 2025Allow1710NoNo
18618420DISPLAY SUBSTRATE INCLUDING CONFIGURATION OF INSULATION LAYERS COVERING CONTACT PADS IN BONDING REGION, AND MANUFACTURING METHOD THEREOFMarch 2024February 2025Allow1110NoNo
18618109ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF INCLUDING VIA HOLE TO FACILITATE DEHYDROGENATION, DISPLAY PANEL, AND DISPLAY DEVICEMarch 2024April 2025Allow1311YesNo
18617547DISPLAY DEVICE WITH HOLE SURROUNDED BY DATA LINES IN DIFFERENT LAYERSMarch 2024April 2025Allow1310NoNo
18615851DISPLAY DEVICE INCLUDING AUXILIARY SUB-PIXELS HAVING CONNECTED INTERMEDIATE LAYERSMarch 2024January 2025Allow1010NoNo
18615338SEMICONDUCTOR DEVICE WITH TRANSMISSIVE LAYER AND MANUFACTURING METHOD THEREOFMarch 2024November 2025Allow2010NoNo
18615067PACKAGE STRUCTURE WITH CAVITY SUBSTRATEMarch 2024September 2025Allow1810NoNo
18610634IMAGING DEVICE COMPRISING CAPACITORMarch 2024January 2026Allow2210NoNo
18606246DISPLAY PANEL AND DISPLAY DEVICE HAVING IMPROVED ELECTROSTATIC DISCHARGE CAPABILITYMarch 2024October 2025Allow1930NoNo
18604310STRUCTURE AND METHOD FOR INTERLEVEL DIELECTRIC LAYER WITH REGIONS OF DIFFERING DIELECTRIC CONSTANTMarch 2024June 2025Allow1510NoNo
18603099STRESS RELIEF STRUCTURE FOR FLIP-CHIP PACKAGED DEVICESMarch 2024October 2025Allow2020NoNo
18597212DISPLAY DEVICE HAVING AN OPENING BETWEEN PIXELSMarch 2024July 2025Allow1620YesNo
18597695Method Used In Forming A Memory Array Comprising Strings Of Memory Cells Using PillarsMarch 2024June 2025Allow1511NoNo
18595486INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND METHODS OF FORMING THE SAMEMarch 2024October 2025Allow2031YesNo
18594365METHOD OF FABRICATING THE SEMICONDUCTOR MEMORY DEVICE INCLUDING CHANNEL PILLARMarch 2024September 2025Allow1920YesNo
18591755METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING AN EMBEDDED SEMICONDUCTOR DIEFebruary 2024July 2025Allow1611NoNo
18591681ESD PROTECTION DEVICE WITH REDUCED HARMONIC DISTORTIONFebruary 2024February 2026Allow2301NoNo
18590204SUB-POWER LINES IN NON-DISPLAY AREA, DISPLAY DEVICE INCLUDING THE SAME AND METHOD FOR PROVIDING THE SAMEFebruary 2024February 2025Allow1110NoNo
18588573SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIP HAVING POWER TRANSISTOR AND TEMPERATURE SENSING DIODEFebruary 2024February 2025Allow1111NoNo
18583157METHOD OF FORMING LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATEFebruary 2024October 2024Allow800NoNo
18581727SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE INCLUDING COUPLING STRUCTURES FOR ELECTRICALLY INTERCONNECTING STACKED SEMICONDUCTOR SUBSTRATESFebruary 2024February 2025Allow1210NoNo
18581826INTERCONNECTION STRUCTURE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAMEFebruary 2024February 2025Allow1220NoNo
18581104Method Of Making a FINFET Device Including a Step of Removing a Portion of a FinFebruary 2024July 2025Allow1710YesNo
18444951ELECTRONIC DEVICES WITH A REDISTRIBUTION LAYER AND METHODS OF MANUFACTURING ELECTRONIC DEVICES WITH A REDISTRIBUTION LAYERFebruary 2024February 2026Allow2320YesNo
18581165METHOD OF FORMING SEMICONDUCTOR DEVICE COMPRISING CONDUCTIVE FEATURE, DIELECTRIC LAYER ADJACENT CONDUCTIVE FEATURE, AND ETCH STOP LAYER ON TOP SURFACE OF DIELECTRIC LAYERFebruary 2024August 2025Allow1810NoNo
18444790MEMORY STRUCTURE HAVING POLYGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGIONFebruary 2024November 2024Allow901NoNo
18444180FLEXIBLE CLIP WITH ALIGNER STRUCTUREFebruary 2024August 2025Allow1810YesNo
18443338SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE DISPOSED IN A CAVITY AND METHOD FOR MANUFACTURING THEREOFFebruary 2024June 2025Allow1610NoNo
18442357STACKED STRUCTURE FOR CMOS IMAGE SENSORSFebruary 2024August 2025Allow1820NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2892.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
157
Examiner Affirmed
97
(61.8%)
Examiner Reversed
60
(38.2%)
Reversal Percentile
75.1%
Higher than average

What This Means

With a 38.2% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
593
Allowed After Appeal Filing
199
(33.6%)
Not Allowed After Appeal Filing
394
(66.4%)
Filing Benefit Percentile
56.7%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2892 - Prosecution Statistics Summary

Executive Summary

Art Unit 2892 is part of Group 2890 in Technology Center 2800. This art unit has examined 15,388 patent applications in our dataset, with an overall allowance rate of 80.7%. Applications typically reach final disposition in approximately 25 months.

Comparative Analysis

Art Unit 2892's allowance rate of 80.7% places it in the 66% percentile among all USPTO art units. This art unit has an above-average allowance rate compared to other art units.

Prosecution Patterns

Applications in Art Unit 2892 receive an average of 1.78 office actions before reaching final disposition (in the 41% percentile). The median prosecution time is 25 months (in the 80% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.