USPTO Art Unit 2892 Prosecution Statistics

Art Unit Information

Art Unit: 2892
Group: 2890
Tech Center: 2800
Total Cases: 15,503
Last Active: October 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18923340SEMICONDUCTOR DEVICEOctober 2024February 2025Allow400NoNo
18750067DISPLAY DEVICE INCLUDING CONNECTION WIRING PART LATERALLY ADJACENT TO DRIVING VOLTAGE WIRINGJune 2024February 2025Allow800YesNo
18750096DISPLAY DEVICE WITH SECOND INITIALIZATION VOLTAGE LINE FORMING OPENINGSJune 2024May 2025Allow1000NoNo
18746509ARRAY SUBSTRATE WITH OVERLAPPING ACTIVE LAYERS HAVING CHANNEL WIDTH GREATER THAN GATE WIDTH, METHOD FOR PREPARING THE SAME, AND DISPLAY PANELJune 2024March 2025Allow820NoNo
18746747HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHODJune 2024October 2024Allow410YesNo
18744244CONDUCTIVE OXIDE OVERHANG STRUCTURES FOR OLED DEVICESJune 2024March 2025Allow900NoNo
18743155METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING AN AIR GAP BETWEEN A CONTACT PAD AND A SIDEWALL OF CONTACT HOLEJune 2024May 2025Allow1100NoNo
18742204DIE SIDEWALL COATINGS AND RELATED METHODSJune 2024April 2025Allow1000YesNo
18741771DISPLAY DEVICE HAVING A CONDUCTIVE METAL LAYER DISPOSED ON A SURFACE OF AN ANTIREFLECTION LAYERJune 2024April 2025Allow1000NoNo
18741440DISPLAY DEVICE CONFIGURED TO PREVENT PROPAGATION OF CRACKS, AND METHOD OF REPAIRING SAMEJune 2024January 2025Allow800YesNo
18736777Semiconductor Device and Method for Manufacturing the SameJune 2024April 2025Allow1000NoNo
18735864INTEGRATED ASSEMBLIES WHICH INCLUDE STACKED MEMORY DECKS, AND METHODS OF FORMING INTEGRATED ASSEMBLIESJune 2024May 2025Allow1100NoNo
18732345METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYSJune 2024December 2024Allow600YesNo
18677617DISPLAY SUBSTRATE WITH PIXEL OPENING AREAS, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICEMay 2024April 2025Allow1100NoNo
18673615FIN FIELD-EFFECT TRANSISTOR DEVICE HAVING HYBRID WORK FUNCTION LAYER STACKMay 2024December 2024Allow700NoNo
18673596FET WITH WRAP-AROUND SILICIDE AND FABRICATION METHODS THEREOFMay 2024June 2025Allow1210NoNo
18672109LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICEMay 2024April 2025Allow1010NoNo
18672001METHOD OF FABRICATING PACKAGE STRUCTURE INCLUDING A PLURALITY OF ANTENNA PATTERNSMay 2024May 2025Allow1210NoNo
18668400DISPLAY DEVICE HAVING ADHESIVE MEMBER AT FOLDING AREAMay 2024January 2025Allow700NoNo
18669033DEVICE CHIP SCALE PACKAGE INCLUDING A PROTECTIVE LAYER AND METHOD OF MANUFACTURING A DEVICE CHIP SCALE PACKAGEMay 2024April 2025Allow1110NoNo
18666787OPTOELECTRONIC DEVICE INCLUDING PHOTODIODE HAVING BURIED LAYER WITH DIFFERENT THICKNESSESMay 2024October 2024Allow510NoNo
18655640SEMICONDUCTOR NANOSTRUCTURES DEVICE STRUCTURE WITH BACKSIDE CONTACTMay 2024December 2024Allow700YesNo
18655596PACKAGE STRUCTUREMay 2024June 2025Allow1310NoNo
18655016DISPLAY DEVICE HAVING AUXILIARY LINESMay 2024March 2025Allow1010NoNo
18654383Microfluidic Chip Having Grounding Trace and Manufacturing Method Thereof, and Microfluidic DeviceMay 2024March 2025Allow1110NoNo
18653289Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated AssembliesMay 2024June 2025Allow1310NoNo
18651194DRIVE CIRCUIT ARRAY SUBSTRATE INCLUDING WELL TAPS PROVIDED IN SUBSET THEREOF, DISPLAY DEVICE, AND ELECTRONIC APPARATUSApril 2024November 2024Allow700YesNo
18648758DEVICE WITH A MULTIZONE REFLECTOR HAVING A DISCREET OPENING FOR A SENSORApril 2024July 2025Allow1410NoNo
18642214Semiconductor Package With EMI Shield and Fabricating Method ThereofApril 2024November 2024Allow700NoNo
18637063DISPLAY APPARATUS WITH PENETRATING PORTION AND METHOD OF MANUFACTURING SAMEApril 2024March 2025Allow1100YesNo
18635186INTEGRATION OF SEMICONDUCTOR DEVICE ASSEMBLIES WITH THERMAL DISSIPATION MECHANISMSApril 2024March 2025Allow1100NoNo
18633183SEMICONDUCTOR APPARATUS INCLUDING COOLER FOR COOLING SEMICONDUCTOR ELEMENTApril 2024June 2025Allow1410NoNo
18631532DISPLAY PANEL AND DISPLAY DEVICE WITH SYMMETRICALLY ARRANGED STRUCTURES CORRESPONDING TO SAME-COLOR LIGHT-EMITTING UNITSApril 2024March 2025Allow1110YesNo
18630503ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING REDUCED COMPENSATED STEP FROM ELECTRODE LINES TO PREVENT CRACKING OF ENCAPSULATION LAYERApril 2024February 2025Allow1110NoNo
18630530SUPERCONDUCTING DEVICE INDLUDING SET OF CIRCUITS HAVING DIFFERENT OPERATIONAL TEMPERATURE REQUIREMENTS WITH MULTIPLE THERMAL SINKS AND MULTIPLE GROUND PLANESApril 2024January 2025Allow900NoNo
18628629DISPLAY PANEL WITH PARTITION WALL AND METAL LAYERS IN NON-DISPLAY AREAApril 2024March 2025Allow1110NoNo
18628233SEMICONDUCTOR DEVICE WITH VERTICAL PATTERNS AND DATA STORAGE SYSTEM INCLUDING THE SAMEApril 2024April 2025Allow1210NoNo
18626348DISPLAY APPARATUS WITH LOAD MATCHING DEVICE NEAR OPENINGS IN NON-DISPLAY AREAApril 2024March 2025Allow1110NoNo
18623992SEMICONDUCTOR DEVICE INCLUDING THROUGH DIE VIAApril 2024March 2025Allow1200YesNo
18618109ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF INCLUDING VIA HOLE TO FACILITATE DEHYDROGENATION, DISPLAY PANEL, AND DISPLAY DEVICEMarch 2024April 2025Allow1311YesNo
18618420DISPLAY SUBSTRATE INCLUDING CONFIGURATION OF INSULATION LAYERS COVERING CONTACT PADS IN BONDING REGION, AND MANUFACTURING METHOD THEREOFMarch 2024February 2025Allow1110NoNo
18617547DISPLAY DEVICE WITH HOLE SURROUNDED BY DATA LINES IN DIFFERENT LAYERSMarch 2024April 2025Allow1310NoNo
18615851DISPLAY DEVICE INCLUDING AUXILIARY SUB-PIXELS HAVING CONNECTED INTERMEDIATE LAYERSMarch 2024January 2025Allow1010NoNo
18604310STRUCTURE AND METHOD FOR INTERLEVEL DIELECTRIC LAYER WITH REGIONS OF DIFFERING DIELECTRIC CONSTANTMarch 2024June 2025Allow1510NoNo
18597695Method Used In Forming A Memory Array Comprising Strings Of Memory Cells Using PillarsMarch 2024June 2025Allow1511NoNo
18590204SUB-POWER LINES IN NON-DISPLAY AREA, DISPLAY DEVICE INCLUDING THE SAME AND METHOD FOR PROVIDING THE SAMEFebruary 2024February 2025Allow1110NoNo
18588573SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIP HAVING POWER TRANSISTOR AND TEMPERATURE SENSING DIODEFebruary 2024February 2025Allow1111NoNo
18583157METHOD OF FORMING LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATEFebruary 2024October 2024Allow800NoNo
18581727SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE INCLUDING COUPLING STRUCTURES FOR ELECTRICALLY INTERCONNECTING STACKED SEMICONDUCTOR SUBSTRATESFebruary 2024February 2025Allow1210NoNo
18581826INTERCONNECTION STRUCTURE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAMEFebruary 2024February 2025Allow1220NoNo
18444790MEMORY STRUCTURE HAVING POLYGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGIONFebruary 2024November 2024Allow901NoNo
18443338SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE DISPOSED IN A CAVITY AND METHOD FOR MANUFACTURING THEREOFFebruary 2024June 2025Allow1610NoNo
18441694DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICEFebruary 2024December 2024Allow1000NoNo
18441533BACKSIDE CONDUCTIVE SEGMENTS COVER A FIRST ACTIVE REGION AND DEFINE AN OPENING ABOVE A SECOND ACTIVE REGIONFebruary 2024April 2025Allow1410NoNo
18440347VERTICAL DEVICE HAVING A PROTRUSION SOURCEFebruary 2024March 2025Allow1310NoNo
18438638SEMICONDUCTOR PACKAGE WITH ROUTING PATCH AND METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGEFebruary 2024June 2025Allow1620NoNo
18434812METHOD FOR MANUFACTURING DISPLAY DEVICE INCLUDING SECOND INTERLAYER INSULATING LAYER OVERLAPPING ACTIVE LAYER OF DRIVING TRANSISTOR AND NOT OVERLAPPING ACTIVE LAYER OF SWITCHING TRANSISTORFebruary 2024January 2025Allow1210NoNo
18434914EPITAXIAL STRUCTURES EXPOSED IN AIRGAPS FOR SEMICONDUCTOR DEVICESFebruary 2024January 2025Allow1110NoNo
18433436METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING LID STRUCTUREFebruary 2024April 2025Allow1410NoNo
18429873CONDUCTIVE LINE STRUCTURES AND METHOD OF FORMING SAMEFebruary 2024October 2024Allow800NoNo
18428245SEMICONDUCTOR DEVICE PACKAGE WITH STRESS REDUCTION DESIGNJanuary 2024April 2025Allow1410NoNo
18424535DISPLAY DEVICE WITH OVERLAP LAYERJanuary 2024April 2025Allow1410YesNo
18423463SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING A COPPER PILLAR AND AN INTERMEDIATE LAYERJanuary 2024February 2025Allow1310NoNo
18423648DIELECTRIC PROTECTION LAYER IN MIDDLE-OF-LINE INTERCONNECT STRUCTURE MANUFACTURING METHODJanuary 2024January 2025Allow1201NoNo
18418795VERTICAL FIELD-EFFECT TRANSISTOR DEVICES HAVING GATE LINERJanuary 2024September 2024Allow800NoNo
18418180DISPLAY APPARATUS, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE DISPLAY APPARATUSJanuary 2024April 2025Allow1500NoNo
18417474LIGHT-EMITTING DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING A FIRST PIXEL AND A SECOND PIXEL AND AN OXIDE SEMICONDUCTOR REGION OVERLAPPING A LIGHT-EMITTING REGIONJanuary 2024November 2024Allow1000NoNo
18416760SEMICONDUCTOR PACKAGES WITH DIE INCLUDING CAVITIES AND RELATED METHODSJanuary 2024April 2025Allow1510NoNo
18416598DISPLAY DEVICE INCLUDING A PLURALITY OF LAYERS EACH INCLUDING A LIGHT EMITTING LAYERJanuary 2024January 2025Allow1210NoNo
18415702MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE HAVING A PLURALITY OF FINSJanuary 2024September 2024Allow800NoNo
18415587PACKAGE STRUCTURE COMPRISING A SEMICONDUCTOR DIE WITH THERMOELECTRIC ELEMENTS AND MANUFACTURING METHOD THEREOFJanuary 2024April 2025Allow1510NoNo
18413153SEMICONDUCTOR DEVICE COMPRISING FIRST AND SECOND CONDUCTIVE LAYERSJanuary 2024April 2025Allow1510NoNo
18411302DISPLAY DEVICEJanuary 2024January 2025Allow1200NoNo
18409808METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE WITH HEATING ELEMENTJanuary 2024January 2025Allow1200NoNo
18409337DISPLAY DEVICE WITH METAL LAYER HAVING A SLOPEJanuary 2024December 2024Allow1100YesNo
18407084DISPLAY DEVICE WITH TOUCH UNIT HAVING REFLECTION PREVENTION UNIT OVERLAPPING VALLEYJanuary 2024March 2025Allow1410NoNo
18400335ELECTRONIC DEVICE HAVING A SUBSTRATE-TO-SUBSTRATE INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOFDecember 2023April 2025Allow1620NoNo
18398981BACK SIDE ILLUMINATION IMAGE SENSORS AND ELECTRONIC DEVICE INCLUDING THE SAMEDecember 2023September 2024Allow900NoNo
18397915HETEROGENEOUS NESTED INTERPOSER PACKAGE FOR IC CHIPSDecember 2023September 2024Allow900NoNo
18397830SEMICONDUCTOR DEVICES HAVING EXPOSED CLIP TOP SIDES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESDecember 2023April 2025Allow1510NoNo
18394985EMBEDDED COOLING SYSTEMS WITH COOLANT CHANNEL FOR DEVICE PACKAGINGDecember 2023December 2024Allow1220YesNo
18395414DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME INCLUDING CUTTING SUBSTRATE AND BLACK MATRIX AT TIP END OF BLOCKING LAYERDecember 2023September 2024Allow900YesNo
18393016INTEGRATED COOLING ASSEMBLIES FOR ADVANCED DEVICE PACKAGING AND METHODS OF MANUFACTURING THE SAMEDecember 2023December 2024Allow1210NoNo
18544771SEMICONDUCTOR DEVICE COMPRISING PN JUNCTION DIODE AND SCHOTTKY BARRIER DIODEDecember 2023February 2025Allow1410NoNo
18544577DISPLAY DEVICE INCLUDING A PROTRUDING SUPPORTDecember 2023April 2025Allow1610NoNo
18545709HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHODDecember 2023May 2024Allow510YesNo
18542781HIGH ELECTRON MOBILITY TRANSISTOR WITH IMPROVED BARRIER LAYERDecember 2023January 2025Allow1300NoNo
18538358METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A SINGLE CRYSTAL STORAGE CONTACTDecember 2023September 2024Allow900NoNo
18537739DISPLAY DEVICE INCLUDING A BENT CONTROL LINEDecember 2023December 2024Allow1210NoNo
18534821SUBSTRATE PAD AND DIE PILLAR DESIGN MODIFICATIONS TO ENABLE EXTREME FINE PITCH FLIP CHIP (FC) JOINTSDecember 2023September 2024Allow900YesNo
18536131METHODS AND APPARATUS INCLUDING ARRAY OF REACTION CHAMBERS OVER ARRAY OF CHEMFET SENSORS FOR MEASURING ANALYTESDecember 2023August 2024Allow900YesNo
18533291METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES COMPRISING ISOLATION STRUCTURES WITH DIFFERENT DEPTHSDecember 2023December 2024Allow1200NoNo
18528888HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHODDecember 2023May 2024Allow510YesNo
18528906HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHODDecember 2023May 2024Allow510YesNo
18528545TRANSISTOR STRUCTURES WITH A METAL OXIDE CONTACT BUFFER AND A METHOD OF FABRICATING THE TRANSISTOR STRUCTURESDecember 2023March 2025Allow1520NoNo
18528707MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGIONDecember 2023December 2024Allow1210NoNo
18526014DISPLAY APPARATUS HAVING INORGANIC LAYER WITH GROOVESDecember 2023December 2024Allow1300NoNo
18526395SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACKDecember 2023February 2025Allow1511NoNo
18524839LIGHT-EMITTING DEVICE HAVING FLEXIBILITYNovember 2023November 2024Allow1210NoNo
18524934INTEGRATED CIRCUITS WITH FINFET GATE STRUCTURESNovember 2023June 2025Allow1920NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2892.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
143
Examiner Affirmed
87
(60.8%)
Examiner Reversed
56
(39.2%)
Reversal Percentile
77.5%
Higher than average

What This Means

With a 39.2% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
520
Allowed After Appeal Filing
185
(35.6%)
Not Allowed After Appeal Filing
335
(64.4%)
Filing Benefit Percentile
63.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 35.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2892 - Prosecution Statistics Summary

Executive Summary

Art Unit 2892 is part of Group 2890 in Technology Center 2800. This art unit has examined 15,503 patent applications in our dataset, with an overall allowance rate of 82.2%. Applications typically reach final disposition in approximately 24 months.

Comparative Analysis

Art Unit 2892's allowance rate of 82.2% places it in the 69% percentile among all USPTO art units. This art unit has an above-average allowance rate compared to other art units.

Prosecution Patterns

Applications in Art Unit 2892 receive an average of 1.68 office actions before reaching final disposition (in the 37% percentile). The median prosecution time is 24 months (in the 79% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.