Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18923340 | SEMICONDUCTOR DEVICE | October 2024 | February 2025 | Allow | 4 | 0 | 0 | No | No |
| 18735194 | PACKAGE STRUCTURE WITH BRIDGE DIE AND METHOD OF FORMING THE PACKAGE STRUCTURE | June 2024 | January 2026 | Allow | 19 | 2 | 0 | No | No |
| 18672001 | METHOD OF FABRICATING PACKAGE STRUCTURE INCLUDING A PLURALITY OF ANTENNA PATTERNS | May 2024 | May 2025 | Allow | 12 | 1 | 0 | No | No |
| 18663697 | SEMICONDUCTOR PACKAGE INCLUDING AN INTEGRATED CIRCUIT DIE AND AN INDUCTOR OR A TRANSFORMER | May 2024 | November 2025 | Allow | 18 | 1 | 1 | No | No |
| 18652779 | PACKAGE STRUCTURE INCLUDING A DIE HAVING A TAPER-SHAPED DIE CONNECTOR | May 2024 | July 2025 | Allow | 14 | 1 | 0 | No | No |
| 18650143 | PACKAGE STRUCTURE HAVING A DEVICE INSIDE A MOLDING MEMBER AND METHOD OF FORMING THE PACKAGE STRUCTURE | April 2024 | August 2025 | Allow | 15 | 2 | 0 | No | No |
| 18643322 | SEMICONDUCTOR DEVICE INCLUDING A MEMORY STACK AND A CONTACT STRUCTURE IN A SPACER STRUCTURE | April 2024 | September 2025 | Allow | 17 | 3 | 0 | Yes | No |
| 18635613 | Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network | April 2024 | November 2025 | Allow | 19 | 2 | 0 | Yes | No |
| 18630530 | SUPERCONDUCTING DEVICE INDLUDING SET OF CIRCUITS HAVING DIFFERENT OPERATIONAL TEMPERATURE REQUIREMENTS WITH MULTIPLE THERMAL SINKS AND MULTIPLE GROUND PLANES | April 2024 | January 2025 | Allow | 9 | 0 | 0 | No | No |
| 18443338 | SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE DISPOSED IN A CAVITY AND METHOD FOR MANUFACTURING THEREOF | February 2024 | June 2025 | Allow | 16 | 1 | 0 | No | No |
| 18438638 | SEMICONDUCTOR PACKAGE WITH ROUTING PATCH AND METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE | February 2024 | June 2025 | Allow | 16 | 2 | 0 | No | No |
| 18423463 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING A COPPER PILLAR AND AN INTERMEDIATE LAYER | January 2024 | February 2025 | Allow | 13 | 1 | 0 | No | No |
| 18417474 | LIGHT-EMITTING DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING A FIRST PIXEL AND A SECOND PIXEL AND AN OXIDE SEMICONDUCTOR REGION OVERLAPPING A LIGHT-EMITTING REGION | January 2024 | November 2024 | Allow | 10 | 0 | 0 | No | No |
| 18403686 | SEMICONDUCTOR DEVICE HAVING FIRST HEAT SPREADER AND SECOND HEAT SPREADER AND MANUFACTURING METHOD THEREOF | January 2024 | December 2025 | Allow | 23 | 3 | 0 | Yes | No |
| 18400335 | ELECTRONIC DEVICE HAVING A SUBSTRATE-TO-SUBSTRATE INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF | December 2023 | April 2025 | Allow | 16 | 2 | 0 | No | No |
| 18528545 | TRANSISTOR STRUCTURES WITH A METAL OXIDE CONTACT BUFFER AND A METHOD OF FABRICATING THE TRANSISTOR STRUCTURES | December 2023 | March 2025 | Allow | 15 | 2 | 0 | No | No |
| 18514716 | METHOD OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE INCLUDING AN EXTENSION GATE CUTTING REGION | November 2023 | September 2024 | Allow | 10 | 1 | 0 | No | No |
| 18511711 | EPITAXIAL FIN STRUCTURES OF FINFET HAVING AN EPITAXIAL BUFFER REGION AND AN EPITAXIAL CAPPING REGION | November 2023 | September 2025 | Allow | 22 | 3 | 0 | Yes | No |
| 18499964 | SEMICONDUCTOR PACKAGE HAVING AN ENCAPULANT COMPRISING CONDUCTIVE FILLERS AND METHOD OF MANUFACTURE | November 2023 | November 2024 | Allow | 13 | 1 | 0 | No | No |
| 18499242 | METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE INCLUDING A BARRIER STRUCTURE IN BETWEEN A PLURALITY OF SURFACE MOUNT COMPONENTS AND A WAFER | November 2023 | December 2024 | Allow | 13 | 1 | 0 | No | No |
| 18286268 | DISPLAY SUBSTRATE AND DISPLAY DEVICE | October 2023 | February 2026 | Allow | 28 | 0 | 0 | No | No |
| 18242919 | METHOD OF FABRICATING TRANSISTORS WITH IMPLANTING DOPANTS AT FIRST AND SECOND DOSAGES IN THE COLLECTOR REGION TO FORM THE BASE REGION | September 2023 | June 2025 | Allow | 22 | 2 | 0 | No | No |
| 18450146 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A STANDARD CELL WHICH INCLUDES A FIN AND A DUMMY TRANSISTOR | August 2023 | July 2024 | Allow | 11 | 1 | 0 | No | No |
| 18447560 | PACKAGED DEVICE INCLUDING AN OPTICAL PATH STRUCTURE ALIGNED TO AN OPTICAL FEATURE | August 2023 | November 2024 | Allow | 15 | 1 | 0 | No | No |
| 18446571 | AN INTEGRATED CHIP INCLUDING AN UPPER CONDUCTIVE STRUCTURE HAVING MULTILAYER STACK TO DECREASE FABRICATION COSTS AND INCREASE PERFORMANCE | August 2023 | May 2025 | Allow | 22 | 3 | 0 | No | No |
| 18365243 | STRUCTURE OF MEMORY DEVICE HAVING FLOATING GATE WITH PROTRUDING STRUCTURE | August 2023 | October 2024 | Allow | 14 | 2 | 0 | No | No |
| 18363742 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE INCLUDING FORMING CAVITY IN CIRCUIT SUBSTRATE WITHOUT EXPOSING FLOOR PLATE | August 2023 | September 2024 | Allow | 13 | 1 | 0 | No | No |
| 18226119 | METHOD AND STRUCTURE TO CONTROL THE SOLDER THICKNESS FOR DOUBLE SIDED COOLING POWER MODULE | July 2023 | December 2024 | Allow | 17 | 2 | 0 | No | No |
| 18358657 | LIGHT EMITTING DEVICE INCLUDING FIRST REFLECTING LAYER AND SECOND REFLECTING LAYER | July 2023 | August 2024 | Allow | 12 | 1 | 0 | No | No |
| 18358594 | SEMICONDUCTOR DEVICES HAVING FINS AND MULTIPLE ISOLATION REGIONS | July 2023 | January 2025 | Allow | 18 | 2 | 0 | No | No |
| 18357987 | STACKED VIA STRUCTURE DISPOSED ON A CONDUCTIVE PILLAR OF A SEMICONDUCTOR DIE | July 2023 | August 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18356721 | SEMICONDUCTOR PACKAGES HAVING A COUPLING MEMBER INCLUDING A VERTICAL WIRE AND A METAL PORTION EXTENDING AROUND THE VERTICAL WIRE | July 2023 | March 2026 | Allow | 32 | 1 | 1 | Yes | No |
| 18352271 | SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER | July 2023 | August 2024 | Allow | 13 | 1 | 0 | No | No |
| 18349696 | SEMICONDUCTOR STRUCTURE HAVING A CONDUCTIVE FEATURE COMPRISING AN ADHESION LAYER AND A METAL REGION OVER AND CONTACTING THE ADHESION LAYER | July 2023 | April 2025 | Allow | 21 | 3 | 0 | No | No |
| 18210958 | SEMICONDUCTOR PACKAGE | June 2023 | October 2025 | Allow | 28 | 0 | 0 | No | No |
| 18334280 | INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING A PLURALITY OF INTEGRATED CIRCUITS ELECTRICALLY COUPLED THROUGH A SYNCHRONIZATION SIGNAL | June 2023 | May 2025 | Allow | 24 | 3 | 0 | Yes | No |
| 18329128 | Semiconductor Device Having a Metal Pad and a Protective Layer for Corrosion Prevention Due to Exposure to Halogen | June 2023 | August 2024 | Allow | 15 | 2 | 0 | No | No |
| 18203668 | STACKED PACKAGE STRUCTURE INCLUDING A CHIP DISPOSED ON A REDISTRIBUTION LAYER AND A MOLDING LAYER COMPRISES A RECESS | May 2023 | January 2026 | Allow | 32 | 1 | 1 | No | No |
| 18201466 | SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF HEAT DISSIPATION REINFORCEMENTS AND METHOD FOR FABRICATING SAME | May 2023 | January 2026 | Allow | 32 | 1 | 0 | Yes | No |
| 18200130 | FLIP CHIP SELF-ALIGNMENT FEATURES FOR SUBSTRATE AND LEADFRAME APPLICATIONS AND METHOD OF MANUFACTURING THE FLIP CHIP SELF-ALIGNMENT FEATURES | May 2023 | June 2025 | Allow | 25 | 3 | 0 | No | No |
| 18319765 | METHOD OF MANUFACTURING A THREE DIMENSIONAL INTEGRATED SEMICONDUCTOR ARCHITECTURE HAVING ALIGNMENT MARKS PROVIDED IN A CARRIER SUBSTRATE | May 2023 | April 2024 | Allow | 11 | 1 | 0 | Yes | No |
| 18308883 | SEMICONDUCTOR STRUCTURE HAVING DIELECTRIC PLUGS PENETRATING THROUGH A POLYMER LAYER | April 2023 | July 2025 | Allow | 26 | 3 | 0 | No | No |
| 18140206 | METHOD FOR MANUFACTURING COMPOSITE STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | April 2023 | March 2026 | Abandon | 35 | 1 | 0 | No | No |
| 18121429 | SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR CHIP ON A REDISTRIBUTION SUBSTRATE AND CONDUCTIVE STRUCTURE SPACED APART FROM THE SEMICONDUCTOR CHIP | March 2023 | January 2026 | Allow | 34 | 1 | 0 | Yes | No |
| 18182369 | METHOD FOR FORMING CONDUCTIVE BUMPS BY PERFORMING A REFLOW PROCESS | March 2023 | March 2026 | Allow | 36 | 1 | 1 | Yes | No |
| 18119909 | METHOD OF BONDING SUBSTRATES UTILIZING A SUBSTRATE HOLDER WITH HOLDING FINGERS | March 2023 | March 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18173883 | ELECTRONIC PACKAGE INCLUDING AN INTERPOSER STACKED ON AN ELECTRONIC ELEMENT AND MANUFACTURING METHOD THEREOF | February 2023 | September 2025 | Allow | 31 | 1 | 0 | No | No |
| 18173418 | METHOD FOR PACKAGING AN INTEGRATED CIRCUIT (IC) PACKAGE WITH EMBEDDED HEAT SPREADER IN A REDISTRIBUTION LAYER (RDL) | February 2023 | November 2023 | Allow | 9 | 1 | 0 | No | No |
| 18171020 | THERMAL MANAGEMENT DEVICE FOR HIGH HEAT FLUX APPLICATIONS INCLUDING A MICROCHANNEL HEAT SINK ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME | February 2023 | April 2024 | Allow | 14 | 2 | 0 | No | No |
| 18169337 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING BONDING A PLURALITY OF FIRST SEMICONDUCTOR DIES TO A PLURALITY OF SECOND SEMICONDUCTOR DIES | February 2023 | January 2026 | Allow | 35 | 1 | 1 | No | No |
| 18162071 | SEMICONDUCTOR DEVICE HAVING AN INDUCTOR DISPOSED WITHIN A FIRST BONDING LAYER AND A SECOND BONDING LAYER | January 2023 | February 2026 | Allow | 36 | 1 | 1 | No | No |
| 18104278 | SEMICONDUCTOR PACKAGE SUBSTRATE WITH A SMOOTH GROOVE STRADDLING TOPSIDE AND SIDEWALL | January 2023 | August 2025 | Allow | 30 | 0 | 1 | No | No |
| 18096341 | Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material | January 2023 | February 2024 | Allow | 13 | 1 | 0 | Yes | No |
| 18154033 | SELF-DENSIFYING INTERCONNECTION BETWEEN A HIGH-TEMPERATURE SEMICONDUCTOR DEVICE SELECTED FROM GaN OR SiC AND A SUBSTRATE | January 2023 | February 2026 | Allow | 37 | 1 | 1 | No | No |
| 18090918 | SEMICONDUCTOR PACKAGE HAVING A SEMICONDUCTOR ELEMENT AND A WIRING STRUCTURE | December 2022 | April 2024 | Allow | 15 | 1 | 0 | No | No |
| 18087705 | BONDED STRUCTURE INCLUDING AN OBSTRUCTIVE ELEMENT DIRECTLY BONDED TO A SEMICONDUCTOR ELEMENT WITHOUT AN ADHESIVE | December 2022 | March 2025 | Allow | 27 | 3 | 0 | No | No |
| 18087377 | FLIP CHIP BONDING FOR SEMICONDUCTOR PACKAGES USING METAL STRIP | December 2022 | October 2025 | Allow | 34 | 1 | 0 | No | No |
| 18069485 | A BONDED STRUCTURE INCLUDING A FIRST MICROELECTRONIC DEVICE DIRECT HYBRID BONDED TO A SECOND MICROELECTRONIC DEVICE | December 2022 | January 2026 | Allow | 37 | 3 | 0 | Yes | No |
| 18083339 | SEMICONDUCTOR DEVICES HAVING A CONDUCTIVE LAYER STACKING WITH AN INSULATING LAYER AND A SPACER STRUCTURE THROUGH THE CONDUCTIVE LAYER | December 2022 | July 2024 | Allow | 19 | 2 | 0 | No | No |
| 18079039 | INTEGRATED CHIP INCLUDING A TUNNEL DIELECTRIC LAYER WHICH HAS DIFFERENT THICKNESSES OVER A PROTRUSION REGION OF A SUBSTRATE | December 2022 | June 2024 | Allow | 18 | 2 | 0 | No | No |
| 18064241 | SEMICONDUCTOR PACKAGE INCLUDING A BARRIER STRUCTURE COVERING CONNECTION PADS AND CONTACTING A PROTRUDING PORTION OF AN ADHESIVE LAYER | December 2022 | October 2025 | Allow | 34 | 1 | 0 | Yes | No |
| 18075288 | WIRE BOND DAMAGE DETECTOR INCLUDING A DETECTION BOND PAD OVER A FIRST AND A SECOND CONNECTED STRUCTURES | December 2022 | July 2024 | Allow | 20 | 2 | 0 | No | No |
| 18059165 | MICROELECTRONIC DEVICES HAVING A MEMORY ARRAY REGION, A CONTROL LOGIC REGION, AND SIGNAL ROUTING STRUCTURES | November 2022 | April 2024 | Allow | 16 | 2 | 0 | No | No |
| 18058795 | MEMORY DEVICE HAVING VERTICAL STRUCTURE INCLUDING A FIRST WAFER AND A SECOND WAFER STACKED ON THE FIRST WAFER | November 2022 | December 2023 | Allow | 12 | 1 | 0 | No | No |
| 18054229 | SEMICONDUCTOR DEVICE PACKAGE ASSEMBLIES HAVING A PRE-APPLIED THERMALLY CONDUCTIVE ADHESIVE | November 2022 | February 2026 | Allow | 39 | 2 | 0 | Yes | No |
| 17979713 | PACKAGE STRUCTURE HAVING AT LEAST ONE DIE WITH A PLURALITY OF TAPER-SHAPED DIE CONNECTORS | November 2022 | January 2024 | Allow | 14 | 1 | 0 | No | No |
| 17977167 | SEMICONDUCTOR PACKAGE INCLUDING UNDER-BUMP PROTECTION PATTERNS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | October 2022 | October 2025 | Allow | 36 | 1 | 0 | Yes | No |
| 17960767 | PACKAGE STRUCTURE WITH BRIDGE DIE LATERALLY WRAPPED BY INSULATING ENCAPSULANT AND SURROUNDED BY THROUGH VIAS AND METHOD OF FORMING THE PACKAGE STRUCTURE | October 2022 | February 2024 | Allow | 17 | 1 | 0 | No | No |
| 17959580 | PACKAGE STRUCTURE INCLUDING A SIDE HEAT DISSIPATOR AND METHOD FOR MANUFACTURING THE PACKAGE STRUCTURE | October 2022 | September 2025 | Allow | 35 | 1 | 0 | Yes | No |
| 17957060 | SYSTEM-ON-CHIP INTEGRATED PACKAGING STRUCTURE, HAVING A CHIP EMBEDDED IN A RECESS, MANUFACTURING METHOD THEREFOR AND THREE-DIMENSIONAL STACKED DEVICE | September 2022 | August 2025 | Allow | 35 | 1 | 0 | No | No |
| 17953941 | ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE HAVING AN ANODE LAYER COMPRISES A COMMON POWER LINE PROVIDED WITH VENT HOLES | September 2022 | May 2024 | Allow | 20 | 1 | 0 | No | No |
| 17953272 | PACKAGE STRUCTURE INCLUDING A FIRST NON-CONDUCTIVE LAYER HAVING A GREATER MELT VISCOSITY THAN A SECOND NON-CONDUCTIVE LAYER AND METHOD FOR FABRICATING THE PACKAGE STRUCTURE | September 2022 | August 2025 | Allow | 35 | 1 | 0 | No | No |
| 17946605 | METHOD FOR ESTABLISHING A BUILDING AUTOMATION SYSTEM INCLUDING INSTALLING A PLURALITY OF CONTROLLABLE DEVICES IN A PLURALITY OF ROOMS IN A BUILDING | September 2022 | January 2025 | Allow | 28 | 2 | 0 | No | No |
| 17930942 | MEMORY MODULE HAVING FIRST CONNECTION BUMPS AND SECOND CONNECTION BUMPS | September 2022 | October 2025 | Allow | 38 | 2 | 0 | Yes | No |
| 17892788 | FLIP CHIP LED WITH SIDE REFLECTORS ENCASING SIDE SURFACES OF A SEMICONDUCTOR STRUCTURE AND PHOSPHOR | August 2022 | February 2024 | Allow | 18 | 2 | 0 | No | No |
| 17886872 | SEMICONDUCTOR PACKAGE INCLUDING A REDISTRIBUTION SUBSTRATE AND A PAIR OF SIGNAL PATTERNS | August 2022 | October 2025 | Allow | 39 | 1 | 0 | Yes | No |
| 17818742 | Packages Including Multiple Encapsulated Substrate Blocks and Overlapping Redistribution Structures | August 2022 | February 2024 | Allow | 19 | 1 | 0 | Yes | No |
| 17759808 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING A CATHODE LAYER HAVING A PLURALITY OF CATHODE UNITS | July 2022 | October 2025 | Allow | 38 | 2 | 0 | No | No |
| 17874400 | ELECTRODE STRUCTURE INCLUDING METAL AND HEAT DISSIPATION LAYER AND SEMICONDUCTOR INCLUDING THE ELECTRODE STRUCTURE | July 2022 | August 2025 | Allow | 37 | 1 | 0 | Yes | No |
| 17874898 | ELECTRONIC COMPONENT APPARATUS HAVING A FIRST LEAD FRAME AND A SECOND LEAD FRAME AND AN ELECTRONIC COMPONENT PROVIDED BETWEEN THE FIRST LEAD FRAME AND THE SECOND LEAD FRAME | July 2022 | January 2024 | Allow | 18 | 2 | 0 | Yes | No |
| 17874741 | Semiconductor Device and Method having a Through Substrate Via and an Interconnect Structure | July 2022 | July 2024 | Allow | 24 | 2 | 0 | No | No |
| 17870798 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR DIE AND A PLURALITY OF ANTENNA PATTERNS | July 2022 | February 2024 | Allow | 19 | 2 | 0 | No | No |
| 17869196 | Method of Manufacturing a Semiconductor Device Including a Plurality of Circuit Components and Array of Conductive Contacts | July 2022 | September 2024 | Allow | 26 | 0 | 0 | No | No |
| 17864617 | METHOD FOR INDUCED QUANTUM DOTS FOR MATERIAL CHARACTERIZATION, QUBITS, AND QUANTUM COMPUTERS | July 2022 | August 2023 | Allow | 14 | 1 | 0 | No | No |
| 17860291 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING A COPPER PILLAR AND AN INTERMEDIATE LAYER AND A CONCAVE PORTION FORMED AT ONE END SURFACE OF THE COPPER PILLAR | July 2022 | October 2023 | Allow | 15 | 1 | 0 | No | No |
| 17857035 | SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR WAFER AND A SURFACE MOUNT COMPONENT OVERHANGING A PERIPHERY OF THE SEMICONDUCTOR WAFER | July 2022 | August 2023 | Allow | 13 | 1 | 0 | No | No |
| 17850857 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR FIN COMPRISING A SILICON GERMANIUM PORTION AND AN ISOLATION STRUCTURE AT A SIDEWALL OF THE SILICON GERMANIUM PORTION | June 2022 | January 2024 | Allow | 18 | 2 | 0 | Yes | No |
| 17850867 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING ANNEALING A GERMANIUM LAYER TO DIFFUSE GERMANIUM ATOMS INTO A SILICON SUBSTRATE | June 2022 | January 2024 | Allow | 19 | 2 | 0 | Yes | No |
| 17850221 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING CUTTING A MOLDING MEMBER AND A REDISTRIBUTION WIRING LAYER AND A CUTTING REGION OF A BASE SUBSTRATE | June 2022 | September 2023 | Allow | 15 | 1 | 0 | Yes | No |
| 17845929 | ELECTRONIC DEVICE INCLUDING AN UNDERFILL LAYER AND A PROTECTIVE STRUCTURE ADJACENT TO THE UNDERFILL LAYER | June 2022 | January 2026 | Allow | 42 | 1 | 1 | No | No |
| 17843835 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING FORMING A SIDEWALL SPACER ON A SIDEWALL OF A CHANNEL STRUCTURE | June 2022 | July 2025 | Allow | 37 | 1 | 1 | No | No |
| 17842726 | COLOR CONVERSION SUBSTRATE INCLUDING FIRST BANK STRUCTURE SURROUNDING SECOND BANK STRUCTURE AND DISPLAY DEVICE INCLUDING THE SAME | June 2022 | March 2025 | Allow | 33 | 1 | 0 | No | No |
| 17757218 | LIGHT-EMITTING DIODE INCLUDING AN ACTIVE LAYER DISPOSED BETWEEN A FIRST SEMICONDUCTOR LAYER AND A SECOND SEMICONDUCTOR LAYER AND DISPLAY DEVICE COMPRISING SAME | June 2022 | January 2026 | Allow | 43 | 2 | 0 | No | No |
| 17833223 | METHOD OF MANUFACTURING AN INTERCONNECTION STRUCTURE FOR A SEMICONDUCTOR DEVICE HAVING A SPACER SEPARATING FIRST AND SECOND CONDUCTIVE LINES | June 2022 | May 2025 | Allow | 35 | 1 | 0 | No | No |
| 17826756 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING BONDING LAYER AND ADSORPTION LAYER | May 2022 | July 2023 | Allow | 14 | 1 | 0 | Yes | No |
| 17824952 | METHOD FOR FABRICATING AN IMAGE SENSING DEVICE HAVING A PRIMARY GRID AND A SECOND GRID SURROUNDING THE PRIMARY GRID | May 2022 | September 2023 | Allow | 16 | 1 | 0 | No | No |
| 17780151 | DISPLAY DEVICE HAVING SEMICONDUCTOR LIGHT EMITTING DIODES SEATED IN A PLURALITY OF CELLS, AND METHOD FOR MANUFACTURING THE DISPLAY DEVICE | May 2022 | July 2025 | Allow | 38 | 2 | 0 | No | No |
| 17751758 | LIGHT-EMITTING DISPLAY DEVICE HAVING A FIRST PIXEL AND A SECOND PIXEL AND AN OXIDE SEMICONDUCTOR LAYER HAVING A REGION OVERLAPPING A LIGHT-EMITTING REGION OF THE SECOND PIXEL | May 2022 | September 2023 | Allow | 16 | 1 | 0 | No | No |
| 17664863 | IMAGE SENSOR HAVING INCREASED INTEGRATION INCLUDING ACTIVE PATTERNS OVERLAPPING A PORTION OF A PIXEL ISOLATION STRUCTURE | May 2022 | June 2025 | Allow | 37 | 2 | 0 | Yes | No |
| 17779385 | FLEXIBLE DISPLAY PANEL HAVING A BENDING AREA LOCATED BETWEEN A DISPLAY AREA AND A BONDING AREA AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE | May 2022 | March 2025 | Allow | 34 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner NGUYEN, KHIEM D.
With a 66.7% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 53.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner NGUYEN, KHIEM D works in Art Unit 2892 and has examined 507 patent applications in our dataset. With an allowance rate of 92.7%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 25 months.
Examiner NGUYEN, KHIEM D's allowance rate of 92.7% places them in the 79% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by NGUYEN, KHIEM D receive 2.20 office actions before reaching final disposition. This places the examiner in the 60% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.
The median time to disposition (half-life) for applications examined by NGUYEN, KHIEM D is 25 months. This places the examiner in the 80% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +7.4% benefit to allowance rate for applications examined by NGUYEN, KHIEM D. This interview benefit is in the 36% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.
When applicants file an RCE with this examiner, 32.1% of applications are subsequently allowed. This success rate is in the 67% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.
This examiner enters after-final amendments leading to allowance in 44.8% of cases where such amendments are filed. This entry rate is in the 68% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 133.3% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 86% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.
This examiner withdraws rejections or reopens prosecution in 88.9% of appeals filed. This is in the 82% percentile among all examiners. Of these withdrawals, 37.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.
When applicants file petitions regarding this examiner's actions, 46.4% are granted (fully or in part). This grant rate is in the 41% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.
Examiner's Amendments: This examiner makes examiner's amendments in 6.7% of allowed cases (in the 89% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 10.6% of allowed cases (in the 89% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.