USPTO Examiner JONES ERIC W - Art Unit 2892

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18736777Semiconductor Device and Method for Manufacturing the SameJune 2024April 2025Allow1000NoNo
18665836METHOD OF MAKING A DISPLAY APPARATUS USING A SELECTIVE MASK STRUCTUREMay 2024August 2025Allow1520YesNo
18665846MANUFACTURING METHOD FOR DISPLAY DEVICE INCLUDING PAD ELECTRODEMay 2024September 2025Allow1600NoNo
18633183SEMICONDUCTOR APPARATUS INCLUDING COOLER FOR COOLING SEMICONDUCTOR ELEMENTApril 2024June 2025Allow1410NoNo
18630503ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING REDUCED COMPENSATED STEP FROM ELECTRODE LINES TO PREVENT CRACKING OF ENCAPSULATION LAYERApril 2024February 2025Allow1110NoNo
18524934INTEGRATED CIRCUITS WITH FINFET GATE STRUCTURESNovember 2023June 2025Allow1920NoNo
18489939INORGANIC LAYER STRUCTURE IN BENDING AREA OF DISPLAY DEVICE AND METHOD OF PROVIDING THE SAMEOctober 2023January 2025Allow1510YesNo
18377781ORGANIC ELECTROLUMINESCENT DEVICE INCLUDING THIN FILM ENCAPSULATION STRUCTURE AND METHOD FOR PRODUCING SAMEOctober 2023February 2025Allow1720NoNo
18465136DISPLAY APPARATUS HAVING TRANSMISSION AREASeptember 2023December 2024Allow1510NoNo
18281393DISPLAY DEVICE TEST PORTION AND PRODUCTION METHOD FOR SAMESeptember 2023February 2026Allow2900NoNo
18242231DISPLAY DEVICE INCLUDING SUPPORT STRUCTURE TO REDUCE BREAKAGE OF SIGNAL LINESSeptember 2023July 2024Allow1010NoNo
18364286Selective Deposition of Metal Barrier in Damascene ProcessesAugust 2023April 2024Allow800NoNo
18355309SEMICONDUCTOR DEVICEWITH SELECTIVELY ETCHED DIELECTRIC FINSJuly 2023January 2026Allow3010YesNo
18269956DISPLAY SUBSTRATE COMPRISING CONDUCTIVE LAYERS, MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS COMPRISING THE DISPLAY SUBSTRATEJune 2023March 2026Allow3310NoNo
18336668METHOD OF REDUCING SPLICING SPACING OF OLED DISPLAY PANEL SPLICING UNITJune 2023November 2025Allow2900NoNo
18317579DISPLAY DEVICE INCLUDING DAM AND CRACK DETECTORMay 2023June 2025Allow2530YesNo
18140758ORGANIC ELECTRONIC COMPONENT WITH ELECTRON INJECTION LAYERApril 2023February 2024Allow1030YesNo
18141300NOVEL THIN FILM RESISTORApril 2023March 2024Allow1010NoNo
18306599RF DEVICE WITHOUT SILICON HANDLE SUBSTRATE FOR ENHANCED THERMAL AND ELECTRICAL PERFORMANCE AND METHODS OF FORMING THE SAMEApril 2023April 2024Allow1110NoNo
18302216DISPLAY PANEL AND DISPLAY DEVICEApril 2023April 2024Allow1200NoNo
18128449METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGEMarch 2023August 2023Allow400NoNo
18191769MOTHER GLASS PROTECTIVE FILM AND METHOD FOR MANUFACTURING DISPLAY DEVICEMarch 2023March 2026Allow3510NoNo
18190811DISPLAY APPARATUS INCLUDING A SUBSTRATE HAVING A HOLEMarch 2023December 2023Allow810NoNo
18245142DISPLAY SUBSTRATE, METHOD FOR FORMING THE SAME AND DISPLAY DEVICEMarch 2023September 2025Allow3000NoNo
17605022DISPLAY PANEL ENCAPULATION STRUCTURE AND METHOD OF MANUFACTURING THE SAMEMarch 2023January 2026Allow5120NoNo
18166087DISPLAY SUBSTRATE HAVING ADDITIONAL PAD LAYERFebruary 2023April 2024Allow1410NoNo
18162762DISPLAY DEVICE WITH CONNECTED BASE UNITSFebruary 2023December 2025Allow3510YesNo
18040161METAL OVERHANG FOR ADVANCED PATTERNINGFebruary 2023December 2025Allow3520YesNo
18017642DISPLAY SUBSTRATE WITH STACKED ACTIVE DEVICES, METHOD FOR MANUFACTURING THE DISPLAY SUBSTRATE, AND DISPLAY APPARATUS COMPRISING THE DISPLAY SUBSTRATEJanuary 2023September 2025Allow3210NoNo
18098769Semiconductor Device Including Transistors and Method for Manufacturing the SameJanuary 2023October 2023Allow910NoNo
18016456DISPLAY SUBSTRATE COMPRISING CIRCUIT AND DAM ISOLATION REGIONS, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS INCLUDING THE DISPLAY SUBSTRATEJanuary 2023December 2025Allow3510NoNo
18094920DISPLAY DEVICE INCLUDING PROTECTIVE MEMBER AND METHOD OF MANUFACTURING THE SAMEJanuary 2023December 2025Allow3511YesNo
18084453DISPLAY DEVICE WITH OVERLAPPING FANOUTSDecember 2022October 2025Allow3410NoNo
18056414ENHANCED OLED OUTCOUPLING BY SUPPRESSING SURFACE PLASMON MODESNovember 2022December 2024Abandon2530NoNo
17968146DISPLAY DEVICE AND MANUFACTURING METHOD FOR THE SAMEOctober 2022August 2025Allow3401NoNo
17965798DISPLAY APPARATUS HAVING DAM STRUCTURES AND AN INSULATING MATERIAL AND METHOD OF MANUFACTURING THE SAMEOctober 2022December 2025Allow3811NoNo
17960453DISPLAY APPARATUS HAVING PIXEL DEFINING LAYER COVERING PIXEL ELECTRODE EDGE PORTIONSOctober 2022January 2025Allow2850YesNo
17944983REDISTRIBUTION LAYER AND INTEGRATED CIRCUIT INCLUDING REDISTRIBUTION LAYERSeptember 2022November 2023Allow1411YesNo
17802440DISPLAY DEVICE AND ELECTRONIC DEVICE WITH MULTILAYER CATHODE ELECTRODEAugust 2022October 2025Allow3820NoNo
17884576DISPLAY DEVICE HAVING REFLOW PREVENTION STRUCTURESAugust 2022August 2025Allow3610YesNo
17818402METHOD OF MAKING A SILICON CARBIDE INTEGRATED CIRCUITAugust 2022February 2023Allow600NoNo
17883406Method of Forming An Integrated Circuit Using a Patterned Mask LayerAugust 2022January 2024Allow1710NoNo
17877738ARRAY SUBSTRATE WITH CONCAVO-CONVEX STRUCTURE, DISPLAY PANEL, DISPLAY DEVICE AND MANUFACTURING METHOD OF ARRAY SUBSTRATEJuly 2022February 2026Allow4221NoNo
17796490DISPLAY SUBSTRATE AND DISPLAY DEVICE HAVING LIGHT-TRANSMITTING OPENINGS AND LIGHT-TRANSMITTING PORTIONSJuly 2022August 2025Allow3610NoNo
17815242METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEJuly 2022April 2024Allow2100NoNo
17872904DISPLAY DEVICE WITH ALIGNED OPENINGS IN A POLARIZING FILM AND CONDUCTIVE LAYERS AND METHOD OF MANUFACTURING THE SAMEJuly 2022November 2025Allow3920YesNo
17871726DISPLAY DEVICE WITH A SELECTIVELY MODIFIED SURFACE AREA AND METHOD OF MANUFACTURING THE SAMEJuly 2022October 2025Allow3930NoNo
17870467Via for Component Electrode ConnectionJuly 2022July 2024Allow2430YesNo
17866858ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING REDUCED COMPENSATED STEP FROM ELECTRODE LINES TO PREVENT CRACKING OF ENCAPSULATION LAVERJuly 2022January 2024Allow1810YesNo
17864253DISPLAY DEVICE WITH AUXILIARY SOURCE AND DRAIN ELECTRODES AND MANUFACTURING METHOD THEREOFJuly 2022August 2025Allow3710NoNo
17863042SEMICONDUCTOR DEVICE WITH A CONTACT PLUG ADJACENT A GATE STRUCTUREJuly 2022July 2024Allow2411YesNo
17860032DISPLAY APPARATUS WITH PIXEL CIRCUITS CONNECTED TO LIGHT-EMITTING ELEMENTS AND METHOD OF MANUFACTURING THE SAMEJuly 2022August 2025Allow3710YesNo
17856471Integrated Circuits with FinFET Gate StructuresJuly 2022August 2023Allow1410NoNo
17809919Selective Deposition of Metal Barrier in Damascene Processes and the Structures Formed ThereofJune 2022July 2023Allow1310NoNo
17808797GEOMETRIC SEMICONDUCTOR MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2022March 2025Allow3310NoNo
17846948MULTILAYER GATE ISOLATION STRUCTUREJune 2022November 2025Allow4111YesNo
17787566HEMT TRANSISTOR WITH GATE EXTENSIONJune 2022March 2025Allow3310NoNo
17785975PROTECTIVE LAYER FOR DISPLAY MODULE AND MANUFACTURING METHOD THEREFORJune 2022September 2025Allow3920YesNo
17832589EPITAXIAL FEATURES IN SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAMEJune 2022August 2025Allow3810NoNo
17782471DISPLAY PANEL WITH CVD ENCAPSULATION LAYERS, DISPLAY APPARATUS COMPRISING THE ENCAPSULATION LAYERS, AND METHOD FOR MANUFACTURING THE DISPLAY PANELJune 2022March 2025Allow3410NoNo
17831394INTER-PIXEL SUBSTRATE ISOLATIONJune 2022June 2025Abandon3610NoNo
17664612DISPLAY DEVICE INCLUDING A SEALANT AND A FILLER BETWEEN SUBSTRATES AND AN ELECTRONIC DEVICE INCLUDING THE SAMEMay 2022October 2025Allow4131NoNo
17778853DISPLAY PANEL HAVING REDUCED SIGNAL LOADMay 2022April 2025Allow3510NoNo
17745251MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING FRONTSIDE AND BACKSIDE CONTACTSMay 2022June 2025Allow3711NoNo
17738498MODULAR POWER OVERLAY DEVICE AND METHODMay 2022June 2025Allow3811YesNo
17772425LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE, AND PRODUCTION METHOD FOR LIGHT-EMITTING ELEMENTApril 2022March 2025Allow3511NoNo
17660758GATE SPACER STRUCTURES FOR THREE-DIMENSIONAL SEMICONDUCTOR DEVICESApril 2022June 2025Allow3830YesNo
17717127MRAM STRUCTURE WITH CONTACT PLUG PROTRUDING OUT OF CONTACT HOLE AND METHOD OF FABRICATING THE SAMEApril 2022November 2024Allow3151NoNo
17704422DIODE TRIGGERED SILICON CONTROLLED RECTIFIERMarch 2022June 2023Allow1510NoNo
17763212DISPLAY SUBSTRATE HAVING SPACING GROOVE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE HAVING SPACING GROOVEMarch 2022May 2025Allow3820NoNo
17655649Integrated Circuits With Finfet Gate StructuresMarch 2022August 2023Allow1610NoNo
17699042SINGLE-PHOTON DETECTION DEVICE, SINGLE-PHOTON DETECTOR, AND SINGLE-PHOTON DETECTOR ARRAYMarch 2022January 2025Allow3410NoNo
17655423GATE COUPLED NON-LINEAR POLAR MATERIAL BASED CAPACITORS FOR MEMORY AND LOGICMarch 2022May 2025Allow3811NoNo
17642417DISPLAY DEVICE WITH CHARGE TRANSPORT LAYERS HAVING NANOFIBERS AND NANOPARTICLESMarch 2022June 2025Abandon4020NoNo
17680870DISPLAY DEVICE INCLUDING PADS WITH HOLESFebruary 2022August 2025Allow4130NoNo
17677223ORGANIC ELECTRONIC COMPONENT WITH ELECTRON INJECTION LAYERFebruary 2022January 2023Allow1100NoNo
17629019THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREFOR, DISPLAY PANEL, AND DISPLAY DEVICEJanuary 2022September 2025Abandon4421NoNo
17628829DISPLAY PANEL HAVING LIGHT-EMITTING DEVICES AND LIGHT DETECTION LAYER AND MANUFACTURING METHOD THEREFORE, AND DISPLAY APPARATUSJanuary 2022August 2025Allow4330NoNo
17628885DEVICE INCLUDING SEMICONDUCTOR AND STRESSOR LAYERS WITHIN A CAVITY, AND FABRICATION METHOD THEREFORJanuary 2022May 2025Abandon3920NoNo
17648101Active / Passive Control of Micro LED Performance Through Sidewall GatingJanuary 2022June 2025Allow4121YesNo
17569795INTEGRATED CIRCUIT DEVICE HAVING INCLINED STRUCTURESJanuary 2022July 2025Allow4231YesNo
17568428SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR SELECTIVELY ETCHING DUMMY FINSJanuary 2022May 2023Allow1610YesNo
17623188ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND ELECTRONIC DEVICE HAVING ORGANIC PACKAGING LAYERDecember 2021September 2024Allow3210NoNo
17621680OLED DISPLAY PANEL INCLUDING FILLING LAYER AND OLED DISPLAY DEVICE INCLUDING THE SAMEDecember 2021March 2025Abandon3920NoNo
17551464DISPLAY APPARATUS HAVING IRREVERSIBLE DISCOLORATION MATERIAL LAYERDecember 2021October 2025Allow4641YesNo
17541442BURIED GATE STRUCTURES FOR SEMICONDUCTOR DEVICESDecember 2021July 2025Allow4332YesNo
17454775DISPLAY DEVICE INCLUDING A TWO-DIMENSIONAL MATERIAL IN AN ENCAPSULATION LAYER AND METHOD OF MANUFACTURING THE SAMENovember 2021June 2025Allow4431YesNo
17525156METHOD FOR MANUFACTURING AN ISOLATION AREA WITHIN A HOLING AREA AND A DISPLAY AREA OF A DISPLAY PANELNovember 2021October 2024Allow3610NoNo
17453228SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING A DUMMY ELEMENTNovember 2021June 2025Allow4441YesNo
17505592DISPLAY APPARATUS INCLUDING TANDEM ORGANIC LIGHT-EMITTING DIODEOctober 2021December 2025Allow5050YesNo
17502829DISPLAY DEVICE CONNECTING LIGHT EMITTING ELEMENTS TO FIRST AND SECOND CONTACT ELECTRODES VIA THIRD CONTACT ELECTRODEOctober 2021March 2025Allow4130YesNo
17502804OVERHANGING SOURCE/DRAIN CONTACTOctober 2021August 2025Allow4642NoNo
17502798SEMICONDUCTOR DEVICE HAVING A PLURALITY OF NON-VOLATILE MEMORY CELLSOctober 2021June 2025Abandon4430NoNo
17498482METHODS OF FABRICATING OLED PANEL WITH INORGANIC PIXEL ENCAPSULATING BARRIEROctober 2021August 2022Allow1020YesNo
17601870NITRIDE FLUORESCENT MATERIAL AND LIGHT EMISSION DEVICEOctober 2021May 2025Abandon4320NoNo
17482797SEMICONDUCTOR DEVICE WITH IMPROVED CELL DENSITY AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICESeptember 2021November 2024Allow3820YesNo
17473361DISPLAY PANEL FOR REDUCING COUPLING CAPACITANCE BETWEEN GATE OF DRIVING TRANSISTOR AND DATA LINE AND DISPLAY DEVICESeptember 2021February 2023Allow1710NoNo
17436142DISPLAY PANEL INCLUDING LIGHT-ABSORBING LAYERSeptember 2021August 2024Abandon3511NoNo
17436436DISPLAY DEVICE HAVING A THIN ELECTRODE THAT HAS A UNIFORM FILM THICKNESSSeptember 2021September 2024Allow3620YesNo
17465042ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING TRANSPARENT REGION AND MANUFACTURING METHOD THREOFSeptember 2021October 2024Allow3850YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner JONES, ERIC W.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
22
Examiner Affirmed
15
(68.2%)
Examiner Reversed
7
(31.8%)
Reversal Percentile
48.4%
Lower than average

What This Means

With a 31.8% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
54
Allowed After Appeal Filing
17
(31.5%)
Not Allowed After Appeal Filing
37
(68.5%)
Filing Benefit Percentile
48.2%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 31.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner JONES, ERIC W - Prosecution Strategy Guide

Executive Summary

Examiner JONES, ERIC W works in Art Unit 2892 and has examined 648 patent applications in our dataset. With an allowance rate of 58.8%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 35 months.

Allowance Patterns

Examiner JONES, ERIC W's allowance rate of 58.8% places them in the 19% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by JONES, ERIC W receive 2.96 office actions before reaching final disposition. This places the examiner in the 85% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by JONES, ERIC W is 35 months. This places the examiner in the 40% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +15.6% benefit to allowance rate for applications examined by JONES, ERIC W. This interview benefit is in the 55% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 17.9% of applications are subsequently allowed. This success rate is in the 16% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 15.3% of cases where such amendments are filed. This entry rate is in the 16% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 47.6% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 42% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 56.0% of appeals filed. This is in the 28% percentile among all examiners. Of these withdrawals, 39.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 47.9% are granted (fully or in part). This grant rate is in the 43% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 3.1% of allowed cases (in the 80% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.0% of allowed cases (in the 61% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Prepare for rigorous examination: With a below-average allowance rate, ensure your application has strong written description and enablement support. Consider filing a continuation if you need to add new matter.
  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.
  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.