USPTO Examiner HOANG QUOC DINH - Art Unit 2892

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18783980PACKAGE ASSEMBLY INCLUDING LIQUID ALLOY THERMAL INTERFACE MATERIAL (TIM) AND SEAL RING AROUND THE LIQUID ALLOY TIM AND METHODS OF FORMING THE SAMEJuly 2024October 2025Allow1510NoNo
18768963SEMICONDUCTOR DEVICE INCLUDING LOWER SEMICONDUCTOR PACKAGE HAVING HEAT SINCE PATTERNJuly 2024January 2026Allow1810NoNo
18767481SEAL RING STRUCTURE IN THE PERIPHERAL OF DEVICE DIES AND WITH ZIGZAG PATTERNS AND METHOD FORMING SAMEJuly 2024September 2025Allow1510NoNo
18739366THREE DIMENSIONAL MIM CAPACITOR HAVING A COMB STRUCTURE AND METHODS OF MAKING THE SAMEJune 2024November 2025Allow1710NoNo
18673596FET WITH WRAP-AROUND SILICIDE AND FABRICATION METHODS THEREOFMay 2024June 2025Allow1210NoNo
18667449METHOD OF FORMING TOP SELECT GATE TRENCHESMay 2024September 2025Allow1610YesNo
18636446SEMICONDUCTOR DEVICE INCLUDING DETECTION ELECTRODES APPLICABLE FOR A TOUCH SENSORApril 2024July 2025Allow1510NoNo
18620993ENCAPSULATION WARPAGE REDUCTION FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMSMarch 2024August 2025Allow1710NoNo
18615338SEMICONDUCTOR DEVICE WITH TRANSMISSIVE LAYER AND MANUFACTURING METHOD THEREOFMarch 2024November 2025Allow2010NoNo
18615067PACKAGE STRUCTURE WITH CAVITY SUBSTRATEMarch 2024September 2025Allow1810NoNo
18604310STRUCTURE AND METHOD FOR INTERLEVEL DIELECTRIC LAYER WITH REGIONS OF DIFFERING DIELECTRIC CONSTANTMarch 2024June 2025Allow1510NoNo
18603099STRESS RELIEF STRUCTURE FOR FLIP-CHIP PACKAGED DEVICESMarch 2024October 2025Allow2020NoNo
18591755METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING AN EMBEDDED SEMICONDUCTOR DIEFebruary 2024July 2025Allow1611NoNo
18441533BACKSIDE CONDUCTIVE SEGMENTS COVER A FIRST ACTIVE REGION AND DEFINE AN OPENING ABOVE A SECOND ACTIVE REGIONFebruary 2024April 2025Allow1410NoNo
18433436METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING LID STRUCTUREFebruary 2024April 2025Allow1410NoNo
18428245SEMICONDUCTOR DEVICE PACKAGE WITH STRESS REDUCTION DESIGNJanuary 2024April 2025Allow1410NoNo
18413153SEMICONDUCTOR DEVICE COMPRISING FIRST AND SECOND CONDUCTIVE LAYERSJanuary 2024April 2025Allow1510NoNo
18397830SEMICONDUCTOR DEVICES HAVING EXPOSED CLIP TOP SIDES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESDecember 2023April 2025Allow1510NoNo
18508801METHODS OF TSV FORMATION FOR ADVANCED PACKAGINGNovember 2023April 2025Allow1710YesNo
18498042DISPLAY DEVICE HAVING POWER LINEOctober 2023February 2025Allow1610NoNo
18488981SEMICONDUCTOR PACKAGE SUBSTRATE WITH GROOVE ON DIE PADOctober 2023July 2025Allow2120NoNo
18482006SEMICONDUCTOR PACKAGE HAVING COMPOSITE SEED-BARRIER LAYER AND METHOD OF FORMING THE SAMEOctober 2023February 2025Allow1610YesNo
18447769DUAL-SIDED ROUTING IN 3D SEMICONDUCTOR SYSTEM-IN-PACKAGE STRUCTURE AND METHODS OF FORMING THE SAMEAugust 2023January 2025Allow1710NoNo
18363311POWER ELECTRONICS MODULEAugust 2023October 2025Allow2700NoNo
18360974MULTI-GATE DEVICE WITH AIR GAP SPACER AND FABRICATION METHODS THEREOFJuly 2023January 2025Allow1810NoNo
18361769DISPLAY APPARATUS INCLUDING A HEAT-DISSIPATION MEMBER AND ELECTRONIC DEVICE INCLUDING THE SAMEJuly 2023July 2024Allow1210NoNo
18351733ELECTRONIC MODULEJuly 2023October 2025Allow2700NoNo
18216005SOLDERED METALLIC RESERVOIRS FOR ENHANCED TRANSIENT AND STEADY-STATE THERMAL PERFORMANCEJune 2023February 2025Allow2020NoNo
18338372METHOD OF FABRICATING SEMICONDUCTOR PACKAGE INCLUDING SUB-INTERPOSER SUBSTRATESJune 2023December 2024Allow1810YesNo
18212160SEMICONDUCTOR DEVICE PACKAGEJune 2023September 2024Allow1510NoNo
18337767FINFET AND GATE-ALL-AROUND FET WITH SELECTIVE HIGH-K OXIDE DEPOSITIONJune 2023December 2024Allow1810NoNo
18335294Integrated Fan Out Device with a Filler-Free Insulating MaterialJune 2023August 2024Allow1410NoNo
18203849SEMICONDUCTOR DEVICE IN A CONTAINMENT STRUCTURE INCLUDING A BURIED LAYERMay 2023July 2024Allow1410NoNo
18325205SEMICONDUCTOR DEVICE PACKAGE HAVING WARPAGE CONTROL AND METHOD OF FORMING THE SAMEMay 2023March 2025Allow2220YesNo
18322481FUSIBLE STRUCTURESMay 2023October 2024Allow1710NoNo
18196833METHOD OF FORMING A MEOL CONTACT STRUCTUREMay 2023September 2025Allow2900NoNo
18196590SEMICONDUCTOR PACKAGE WITH FRONT SIDE AND BACK SIDE REDISTRIBUTION STRUCTURES AND FABRICATING METHOD THEREOFMay 2023July 2024Allow1510NoNo
18314984SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOFMay 2023November 2024Allow1810NoNo
18143170CONNECTOR FOR IMPLEMENTING MULTI-FACETED INTERCONNECTIONMay 2023May 2024Allow1300NoNo
18306765SEMICONDUCTOR DEVICE COMPRISING SUBMODULE HAVING AT LEAST AN UPPER SURFACE EXPOSED AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICEApril 2023December 2025Allow3210YesNo
18135828ELECTRICAL CONNECTION ELEMENT AND CORRESPOND METHOD AND APPARATUS WITH OUTGASSING GROOVES THAT REMOVE TRAPPED GASSESApril 2023December 2025Allow3200NoNo
18134437DOUBLE-SIDED COOLING POWER MODULE INCLUDING REVERSE-MOUNTED CHIPSApril 2023October 2025Allow3010NoNo
18029330OPTICAL DEVICE PACKAGE PREPARATION METHOD AND OPTICAL DEVICE PACKAGEMarch 2023October 2025Allow3110NoNo
18191092SEMICONDUCTOR DEVICE WITH BRIDGE DIE ELECTRICALLY CONNECTING TWO CHIPS AND MANUFACTURING METHOD THEREOFMarch 2023November 2025Allow3110NoNo
18188360MEMRISTOR DEVICE, METHOD OF FABRICATING THE SAME, SYNAPTIC DEVICE INCLUDING THE SAME, AND NEUROMORPHIC DEVICE INCLUDING THE SYNAPTIC DEVICEMarch 2023December 2025Allow3310NoNo
18185514FULL AG SINTER DISCRETE PREMIUM PACKAGEMarch 2023January 2026Allow3410YesNo
18185865SEMICONDUCTOR DEVICE COMPRISING AN ELECTRODE TERMINAL AND AN ELECTRODE EXPOSED IN AN OPENING PROVIDED IN A MOLD RESIN, SEMICONDUCTOR DEVICE GROUP COMPRISING AN ELECTRODE TERMINAL AND AN ELECTRODE EXPOSED IN AN OPENING PROVIDED IN A MOLD RESIN, AND POWER CONVERSION APPARATUS COMPRISING AN ELECTRODE TERMINAL AND AN ELECTRODE EXPOSED IN AN OPENING PROVIDED IN A MOLD RESINMarch 2023September 2025Allow3010YesNo
18181618SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULEMarch 2023June 2025Allow2700NoNo
18178170SEMICONDUCTOR DEVICES INCLUDING A LOWER SEMICONDUCTOR PACKAGE, AN UPPER SEMICONDUCTOR PACKAGE ON THE LOWER SEMICONDUCTOR PACKAGE, AND A CONNECTION PATTERN BETWEEN THE LOWER SEMICONDUCTOR PACKAGE AND THE UPPER SEMICONDUCTOR PACKAGEMarch 2023April 2024Allow1310NoNo
18115743SEMICONDUCTOR PACKAGE INCLUDING PROCESSING ELEMENT AND I/O ELEMENTFebruary 2023May 2024Allow1510NoNo
18112616SEMICONDUCTOR DEVICE INCLUDING THROUGH-INSULATOR VIA STRUCTUREFebruary 2023July 2025Allow2910NoNo
18022153LIGHT-EMITTING DEVICE WITH ELECTRON TRANSPORT LAYER AND INTERVENING LAYER, MANUFACTURING METHOD THEREOF, DISPLAY SUBSTRATE AND DISPLAY APPARATUSFebruary 2023October 2025Allow3200NoNo
18170672METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING DIFFERENT TYPES OF PLATING FILMSFebruary 2023August 2025Allow3000NoNo
18168633WAFER WARPAGE ADJUSTMENT STRUCTURE AND METHOD FOR MANUFACTURING THE SAMEFebruary 2023July 2025Allow2900NoNo
18109108THREE DIMENSIONAL MIM CAPACITOR HAVING A COMB STRUCTURE AND METHODS OF MAKING THE SAMEFebruary 2023March 2024Allow1310NoNo
18108590SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICESFebruary 2023August 2023Allow600NoNo
18165825LED WITH SMALL MESA WIDTHFebruary 2023June 2024Allow1610NoNo
18150831ELECTRONICALLY PROGRAMMABLE FUSE WITH HEATING TRANSISTORSJanuary 2023September 2025Allow3310NoNo
18084144BUS BAR, POWER SEMICONDUCTOR MODULE ARRANGEMENT INCLUDING A BUS BAR, AND METHOD FOR PRODUCING A BUS BARDecember 2022July 2025Allow3110NoNo
18066141FET WITH WRAP-AROUND SILICIDE AND FABRICATION METHODS THEREOFDecember 2022January 2024Allow1310NoNo
17928724SEMICONDUCTOR DEVICE WITH FIRST AND SECOND CONDUCTORS AND PLATED LAYER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICENovember 2022September 2025Allow3310NoNo
18057326SEMICONDUCTOR DEVICE WITH PROTECTIVE FILM FOR REDUCING ALUMINUM SLIDE IN ALUMINUM WIRING AND MANUFACTURING METHOD THEREOFNovember 2022April 2025Allow2910NoNo
17998999ARRAY SUBSTRATE HAVING AN ACTIVE LAYER STRUCTURE WITH TWO LAYERS IN PARALLEL AND DISPLAY PANEL HAVING AN ACTIVE LAYER STRUCTURE WITH TWO LAYERS IN PARALLELNovember 2022June 2025Allow3110NoNo
18054965SEMICONDUCTOR DEVICENovember 2022August 2023Allow910NoNo
17980044LIGHT EMITTING DISPLAY APPARATUS INCLUDING AN UNDERCUT ALONG AN OUTER PERIPHERY OF AN ANODENovember 2022December 2025Allow3711NoNo
17978269METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICENovember 2022September 2023Allow1110NoNo
18051670SEMICONDUCTOR DEVICE HAVING CONTACT PLUGNovember 2022December 2025Allow3711NoNo
17976228PACKAGE SUBSTRATEOctober 2022July 2023Allow910NoNo
17967015POWER DISTRIBUTION NETWORK WITH BACKSIDE POWER RAILOctober 2022September 2025Allow3510NoNo
18046927Heat dissipation optimization method of silicon-based SU-8 thin film packageOctober 2022July 2025Allow3310NoNo
17936959METHOD FOR FORMING PACKAGE STRUCTURE WITH CAVITY SUBSTRATESeptember 2022December 2023Allow1520NoNo
17955572DISPLAY PANEL INCLUDING BLACK MATRIX OPENING AND LIGHT EXTRACTION OPENING, AND DISPLAY DEVICESeptember 2022July 2025Allow3410NoNo
17956082DISPLAY APPARATUSSeptember 2022April 2025Allow3100NoNo
17915819PEROVSKITE DISPLAYS AND METHODS OF FORMATIONSeptember 2022September 2025Allow3620YesNo
17951739STACKED FET CONTACT FORMATIONSeptember 2022April 2025Allow3101NoNo
17947948LED ASSEMBLYSeptember 2022November 2023Allow1420NoNo
17902035SEMICONDUCTOR DEVICE WITH TRANSMISSIVE LAYER AND MANUFACTURING METHOD THEREOFSeptember 2022November 2023Allow1410NoNo
17821679SEMICONDUCTOR DEVICE WITH BENT TERMINALSAugust 2022July 2025Allow3410YesNo
17891921RECESSED METAL ETCHING METHODSAugust 2022March 2025Allow3100NoNo
17888523HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE FOR INCREASING THE SCHOTTKY DIODE CURRENT AND METHOD OF FORMING THE SAMEAugust 2022July 2025Allow3511NoNo
17887926SEMICONDUCTOR DEVICE WITH CONDUCTORS DISPOSED IN INSULATING FILMS AND METHOD FOR MANUFACTURING THE SAMEAugust 2022April 2025Allow3211NoNo
17885321METHODS OF MANUFACTURING FUSIBLE STRUCTURESAugust 2022September 2024Allow2510NoNo
17885184SEMICONDUCTOR PACKAGE HAVING A METAL CLIP AND RELATED METHODS OF MANUFACTURINGAugust 2022December 2024Allow2800NoNo
17883153SEMICONDUCTOR DEVICES WITH FLEXIBLE SPACER INCLUDING A SUPPORT STRUCTURE AND METHODS OF MAKING THE SAMEAugust 2022March 2025Allow3110NoNo
17879638Fin Shape ModificationAugust 2022May 2025Allow3411YesNo
17873369METHODS FOR SELECTIVELY FORMING A TARGET FILM ON A SUBSTRATE COMPRISING A FIRST DIELECTRIC SURFACE AND A SECOND METALIC SURFACEJuly 2022October 2023Allow1510NoNo
17874234OPTICAL ELEMENT, INFRARED SENSOR, SOLID-STATE IMAGING ELEMENT, AND MANUFACTURING METHOD FOR OPTICAL ELEMENTJuly 2022February 2025Allow3100NoNo
17865846SEMICONDUCTOR DEVICE WITH TUNABLE THRESHOLD VOLTAGE AND METHOD FOR MANUFACTURING THE SAMEJuly 2022June 2025Allow3511NoNo
17862926SEMICONDUCTOR DEVICE INCLUDING DETECTION ELECTRODES APPLICABLE FOR A TOUCH SENSORJuly 2022January 2024Allow1810NoNo
17811080SEMICONDUCTOR STRUCTURE HAVING RELIABLE LINE PATTERN DESIGNS AND METHOD OF MANUFACTURING THE SAMEJuly 2022September 2025Allow3811NoNo
17790101DISPLAY DEVICE INCLUDING AN INORGANIC-INSULATING-FILM-FREE REGION PROVIDED ALONG A NOTCH TO STRENGTHEN THE STRUCTURE OF THE DISPLAY DEVICEJune 2022April 2025Allow3300NoNo
17808997SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOFJune 2022February 2023Allow800NoNo
17847419METHODS OF TSV FORMATION FOR ADVANCED PACKAGINGJune 2022August 2023Allow1410NoNo
17845835SECONDARY DIE WITH A GROUND PLANE FOR STRIP LINE ROUTINGJune 2022November 2025Allow4110NoNo
17843319SEMICONDUCTOR DEVICE FOR SUPPRESSING EXCESSIVE WETTING AND SPREADING OF BONDING LAYERJune 2022April 2025Allow3420NoNo
17786655TWO-DIMENSIONAL SEMICONDUCTOR TRANSISTOR WITH REDUCED HYSTERESIS AND METHOD OF MANUFACTURING THE SAMEJune 2022August 2025Allow3820NoNo
17787050ENCAPSULATION FILM HAVING EXCELLENT RELIABILITY, ORGANIC ELECTRONIC DEVICE COMPRISING THE SAME, AND METHOD FOR MANUFACTURING ORGANIC ELECTRONIC DEVICEJune 2022March 2025Allow3310NoNo
17838485ENHANCED CASCADE FIELD EFFECT TRANSISTORJune 2022July 2024Allow2510NoNo
17806570HIGH ASPECT RATIO BURIED POWER RAIL METALLIZATIONJune 2022October 2024Allow2811YesNo
17835768METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGESJune 2022June 2023Allow1310NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner HOANG, QUOC DINH.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
9
Examiner Affirmed
8
(88.9%)
Examiner Reversed
1
(11.1%)
Reversal Percentile
24.1%
Lower than average

What This Means

With a 11.1% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
34
Allowed After Appeal Filing
8
(23.5%)
Not Allowed After Appeal Filing
26
(76.5%)
Filing Benefit Percentile
31.9%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 23.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner HOANG, QUOC DINH - Prosecution Strategy Guide

Executive Summary

Examiner HOANG, QUOC DINH works in Art Unit 2892 and has examined 1,398 patent applications in our dataset. With an allowance rate of 93.1%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 20 months.

Allowance Patterns

Examiner HOANG, QUOC DINH's allowance rate of 93.1% places them in the 80% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by HOANG, QUOC DINH receive 1.19 office actions before reaching final disposition. This places the examiner in the 14% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by HOANG, QUOC DINH is 20 months. This places the examiner in the 93% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +3.0% benefit to allowance rate for applications examined by HOANG, QUOC DINH. This interview benefit is in the 24% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 30.3% of applications are subsequently allowed. This success rate is in the 60% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 38.3% of cases where such amendments are filed. This entry rate is in the 58% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 94.1% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 68% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 71.0% of appeals filed. This is in the 58% percentile among all examiners. Of these withdrawals, 59.1% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 27.2% are granted (fully or in part). This grant rate is in the 15% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 6.7% of allowed cases (in the 89% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 4.3% of allowed cases (in the 78% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.