Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18743155 | METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING AN AIR GAP BETWEEN A CONTACT PAD AND A SIDEWALL OF CONTACT HOLE | June 2024 | May 2025 | Allow | 11 | 0 | 0 | No | No |
| 18741771 | DISPLAY DEVICE HAVING A CONDUCTIVE METAL LAYER DISPOSED ON A SURFACE OF AN ANTIREFLECTION LAYER | June 2024 | April 2025 | Allow | 10 | 0 | 0 | No | No |
| 18735864 | INTEGRATED ASSEMBLIES WHICH INCLUDE STACKED MEMORY DECKS, AND METHODS OF FORMING INTEGRATED ASSEMBLIES | June 2024 | May 2025 | Allow | 11 | 0 | 0 | No | No |
| 18677617 | DISPLAY SUBSTRATE WITH PIXEL OPENING AREAS, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE | May 2024 | April 2025 | Allow | 11 | 0 | 0 | No | No |
| 18653289 | Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies | May 2024 | June 2025 | Allow | 13 | 1 | 0 | No | No |
| 18635592 | SEMICONDUCTOR DEVICE STRUCTURE HAVING A METAL LAYER POSITIONED UNDER THE SEMICONDUCTOR SUBSTRATE | April 2024 | January 2026 | Allow | 21 | 0 | 0 | No | No |
| 18591681 | ESD PROTECTION DEVICE WITH REDUCED HARMONIC DISTORTION | February 2024 | February 2026 | Allow | 23 | 0 | 1 | No | No |
| 18583157 | METHOD OF FORMING LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE | February 2024 | October 2024 | Allow | 8 | 0 | 0 | No | No |
| 18581826 | INTERCONNECTION STRUCTURE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME | February 2024 | February 2025 | Allow | 12 | 2 | 0 | No | No |
| 18444790 | MEMORY STRUCTURE HAVING POLYGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGION | February 2024 | November 2024 | Allow | 9 | 0 | 1 | No | No |
| 18440347 | VERTICAL DEVICE HAVING A PROTRUSION SOURCE | February 2024 | March 2025 | Allow | 13 | 1 | 0 | No | No |
| 18423648 | DIELECTRIC PROTECTION LAYER IN MIDDLE-OF-LINE INTERCONNECT STRUCTURE MANUFACTURING METHOD | January 2024 | January 2025 | Allow | 12 | 0 | 1 | No | No |
| 18418795 | VERTICAL FIELD-EFFECT TRANSISTOR DEVICES HAVING GATE LINER | January 2024 | September 2024 | Allow | 8 | 0 | 0 | No | No |
| 18416598 | DISPLAY DEVICE INCLUDING A PLURALITY OF LAYERS EACH INCLUDING A LIGHT EMITTING LAYER | January 2024 | January 2025 | Allow | 12 | 1 | 0 | No | No |
| 18415702 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE HAVING A PLURALITY OF FINS | January 2024 | September 2024 | Allow | 8 | 0 | 0 | No | No |
| 18538358 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A SINGLE CRYSTAL STORAGE CONTACT | December 2023 | September 2024 | Allow | 9 | 0 | 0 | No | No |
| 18528707 | MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION | December 2023 | December 2024 | Allow | 12 | 1 | 0 | No | No |
| 18525187 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES | November 2023 | September 2024 | Allow | 10 | 0 | 0 | No | No |
| 18524794 | METHOD OF FORMING CONTACT INCLUDED IN SEMICONDUCTOR DEVICE | November 2023 | November 2024 | Allow | 11 | 1 | 0 | No | No |
| 18521584 | FINFET STRUCTURE WITH A COMPOSITE STRESS LAYER AND REDUCED FIN BUCKLING | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18515181 | LIGHT EMITTING DISPLAY PANEL INCLUDING PLURALITY OF ORGANIC AND INORGANIC LAYERS AND METHOD OF MANUFACTURING THE SAME | November 2023 | January 2025 | Allow | 14 | 2 | 0 | No | No |
| 18504567 | ORGANIC LIGHT-EMITTING COMPONENT HAVING A LIGHT-EMITTING LAYER AS PART OF A CHARGE GENERATION LAYER | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18498718 | METHOD OF DIRECT-BONDED OPTOELECTRONIC DEVICES | October 2023 | September 2024 | Allow | 11 | 0 | 0 | Yes | No |
| 18383086 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF INSULATORS | October 2023 | July 2024 | Allow | 9 | 0 | 0 | No | No |
| 18286760 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT | October 2023 | February 2026 | Allow | 28 | 0 | 0 | No | No |
| 18370927 | LIGHT-EMITTING DEVICE WITH CIRCULAR POLARIZING PLATE OVER BONDING LAYER | September 2023 | October 2024 | Allow | 13 | 1 | 0 | No | No |
| 18470446 | SEMICONDUCTOR DEVICE WITH DIELECTRIC STRUCTURE HAVING ENLARGEMANT PORTION SURROUNDING WORD LINE | September 2023 | December 2024 | Allow | 15 | 1 | 0 | No | No |
| 18470410 | SEMICONDUCTOR DEVICE WITH POROUS SPACER MADE OF LOW-K MATERIAL AND MANUFACTURING METHOD THEREOF | September 2023 | March 2025 | Allow | 18 | 2 | 0 | No | No |
| 18368669 | MEMORY DEVICE HAVING ULTRA-LIGHTLY DOPED REGION AND MANUFACTURING METHOD THEREOF | September 2023 | February 2026 | Allow | 29 | 0 | 1 | No | No |
| 18464475 | INTEGRATED CIRCUIT DEVICE | September 2023 | November 2025 | Allow | 27 | 0 | 0 | No | No |
| 18244242 | MEMORY DEVICE HAVING A BARRIER LAYER BETWEEN A BIT LINE CONTACT AND A TOP ELECTRODE | September 2023 | March 2026 | Allow | 30 | 0 | 1 | No | No |
| 18456741 | LIGHT-EMITTING DIODE FOR GENERATING A MULTI-PEAK BROADBAND BLUE-VIOLET LIGHT SPECTRUM | August 2023 | February 2026 | Allow | 29 | 0 | 0 | No | No |
| 18236579 | MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK | August 2023 | March 2026 | Allow | 30 | 0 | 1 | No | No |
| 18453555 | BONDED MEMORY MRAM ARRAYS SHARING A COMMON DRIVER CIRCUIT AND METHODS OF MAKING THE SAME | August 2023 | February 2026 | Allow | 29 | 0 | 1 | No | No |
| 18547320 | A SEMICONDUCTOR STRUCTURE HAVING A LADDER CONTACT STRUCTURE | August 2023 | March 2026 | Allow | 30 | 0 | 1 | No | No |
| 18362770 | PHASE CHANGE MEMORY DEVICE HAVING TAPERED PORTION OF THE BOTTOM MEMORY LAYER | July 2023 | June 2024 | Allow | 11 | 0 | 0 | No | No |
| 18227361 | SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR LAYER CONTAINING A C-AXIS ALIGNED CRYSTAL | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18224691 | SOLID-STATE IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS HAVING A DIVIDED PIXEL SEPARATION WALL | July 2023 | May 2024 | Allow | 10 | 0 | 0 | No | No |
| 18354844 | A DUMMY FIN BETWEEN FIRST AND SECOND SEMICONDUCTOR FINS | July 2023 | July 2024 | Allow | 12 | 0 | 0 | No | No |
| 18354648 | SEMICONDUCTOR DEVICE | July 2023 | November 2025 | Allow | 28 | 0 | 0 | No | No |
| 18354035 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR | July 2023 | March 2026 | Allow | 32 | 0 | 1 | No | No |
| 18220845 | MEMORY STRUCTURE HAVING A BURIED WORD LINE | July 2023 | October 2025 | Allow | 28 | 0 | 0 | Yes | No |
| 18350838 | Doping for Semiconductor Device with Conductive Feature | July 2023 | February 2024 | Allow | 7 | 0 | 0 | No | No |
| 18219229 | SEMICONDUCTOR DEVICE | July 2023 | November 2025 | Allow | 28 | 0 | 0 | No | No |
| 18218762 | Integrated Assemblies Which Include Stacked Memory Decks, and Methods of Forming Integrated Assemblies | July 2023 | February 2024 | Allow | 7 | 0 | 0 | No | No |
| 18213310 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | June 2023 | October 2025 | Allow | 28 | 0 | 0 | No | No |
| 18338726 | METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES HAVING ALIGNMENT MARKS ON A CARRIER SUBSTRATE | June 2023 | February 2024 | Allow | 8 | 0 | 0 | No | No |
| 18336340 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PATTERN ON CHANNEL | June 2023 | March 2026 | Allow | 33 | 1 | 0 | Yes | No |
| 18207689 | SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE HAVING FIRST PORTION AND SECOND PORTION AND METHOD FOR MANUFACTURING THE SAME | June 2023 | May 2024 | Allow | 11 | 1 | 0 | Yes | No |
| 18329615 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING GROWTH RATE ON CONDUCTIVE LAYER GREATER THAN ON DIELECTRIC LAYER | June 2023 | September 2025 | Allow | 28 | 0 | 1 | No | No |
| 18206512 | DIRECT-BONDED LED ARRAYS AND DRIVERS | June 2023 | July 2024 | Allow | 14 | 1 | 0 | Yes | No |
| 18204819 | MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND FABRICATING METHODS THEREOF | June 2023 | February 2026 | Allow | 33 | 1 | 0 | No | No |
| 18327224 | SEMICONDUCTOR STRUCTURE HAVING VOID IN A BIT LINE CONTACT STRUCTURE | June 2023 | September 2025 | Allow | 28 | 0 | 1 | No | No |
| 18326988 | SEMICONDUCTOR DEVICE INCLUDING A SEPERATION LAYER | May 2023 | January 2026 | Allow | 32 | 1 | 0 | Yes | No |
| 18203820 | SEMICONDUCTOR MEMORY DEVICE HAVING DIELECTRIC SPACER CONTAINING AIR GAP FORMED THERMAL DECOMPOSABLE LAYER | May 2023 | November 2025 | Allow | 30 | 1 | 0 | No | No |
| 18324152 | METHOD FOR FABRICATING THREE DIMENSIONAL MEMORY DEVICES | May 2023 | September 2025 | Allow | 28 | 0 | 0 | No | No |
| 18324157 | SEMICONDUCTOR DEVICE HAVING LOW-K SPACERS INCLUDE A CARBON-DOPED SILICON-BASED MATERIAL | May 2023 | February 2026 | Allow | 33 | 1 | 0 | No | No |
| 18323458 | ARRAY BOUNDARY STRUCTURE TO REDUCE DISHING | May 2023 | June 2024 | Allow | 13 | 0 | 0 | No | No |
| 18301572 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING MULTI-WORK FUNCTION GATE ELECTRODE | April 2023 | January 2024 | Allow | 9 | 0 | 0 | No | No |
| 18193965 | RESISTIVE MEMORY CELL HAVING AN OVONIC THRESHOLD SWITCH | March 2023 | May 2024 | Allow | 14 | 0 | 1 | No | No |
| 18193544 | SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT | March 2023 | April 2024 | Allow | 13 | 1 | 0 | No | No |
| 18186935 | METHOD OF MANUFACTURING MEMORY STRUCTURE HAVING A HEXAGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGION | March 2023 | December 2023 | Allow | 9 | 0 | 0 | No | No |
| 18185372 | SEMICONDUCTOR DEVICE HAVING A PERPENDICULAR DISCRETE CONTACT NODE COUPLED TO THE END OF A FIRST IMPURITY HORIZONTAL LAYER | March 2023 | August 2025 | Allow | 29 | 0 | 0 | No | No |
| 18116537 | SEMICONDUCTOR DEVICES INCLUDING A CONTACT PLUG STRUCTURE ON A METAL SILICIDE LAYER | March 2023 | January 2026 | Allow | 35 | 1 | 0 | Yes | No |
| 18174902 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE HAVING A CONTACT CAPPING LAYER | February 2023 | December 2023 | Allow | 9 | 0 | 0 | No | No |
| 18110999 | Light-Emitting Element Having An Organic Compound And A Transition Metal | February 2023 | December 2023 | Allow | 10 | 0 | 0 | No | No |
| 18109442 | SEMICONDUCTOR DEVICE HAVING A CELL SEPARATION PATTERN IN CONTACT WITH THE BIT LINE CONTACT | February 2023 | August 2025 | Allow | 30 | 0 | 0 | No | No |
| 18168542 | TRANSISTOR, SEMICONDUCTOR STRUCTURE, MEMORY, AND METHOD FOR FORMING SAME | February 2023 | November 2025 | Allow | 33 | 0 | 1 | No | No |
| 18108666 | SEMICONDUCTOR MEMORY DEVICE HAVING BIT LINES AND ISOLATION FINS DISPOSED ON THE SUBSTRATE | February 2023 | August 2024 | Allow | 18 | 2 | 0 | No | No |
| 18108669 | SEMICONDUCTOR MEMORY DEVICE COMPRISES A BIT LINE HAVING A PLURALITY OF PINS EXTENDING TOWARD A SUBSTRATE | February 2023 | September 2025 | Allow | 31 | 0 | 1 | No | No |
| 18107853 | DISPLAY PANEL | February 2023 | April 2024 | Abandon | 14 | 1 | 0 | No | No |
| 18108003 | MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION | February 2023 | September 2023 | Allow | 7 | 0 | 0 | No | No |
| 18164082 | METHOD OF FORMING A 4F2 DRAM INCLUDING BURIED BITLINE | February 2023 | September 2025 | Allow | 32 | 0 | 1 | No | No |
| 18161836 | LIFT-OFF PROCESS FOR MANUFACTURING AN ORGANIC LIGHT-EMITTING DISPLAY APPARATUS | January 2023 | October 2023 | Allow | 9 | 0 | 0 | No | No |
| 18157073 | SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SAME, AND MEMORY | January 2023 | August 2025 | Allow | 31 | 0 | 0 | No | No |
| 18095973 | STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS FOR FORMING SUCH | January 2023 | October 2023 | Allow | 9 | 0 | 0 | No | No |
| 18093561 | SEMICONDUCTOR MEMORY DEVICE HAVING AN OHMIC CONTACT ON THE IMPURITY REGIONS | January 2023 | June 2025 | Allow | 29 | 0 | 0 | Yes | No |
| 18093568 | SEMICONDUCTOR MEMORY DEVICE HAVING CONNECTION PATTERN BETWEEN THE BIT LINE CONTACT AND THE SEPARATION INSULATING PATTERN | January 2023 | August 2025 | Allow | 31 | 0 | 0 | No | No |
| 18149178 | METHOD OF FORMING BIT LINE CONTACT STRUCTURE USING SERIES OF PICKLING PROCESSES TO REMOVE NATIVE OXIDE ON SURFACE OF THE ACTIVE AREAS | January 2023 | March 2025 | Allow | 26 | 0 | 1 | No | No |
| 18090108 | SEMICONDUCTOR DEVICE, MEMORY AND STORAGE SYSTEM | December 2022 | July 2025 | Allow | 31 | 0 | 0 | No | No |
| 18146962 | STRAINED-CHANNEL FIN FETS | December 2022 | September 2024 | Allow | 21 | 1 | 1 | No | No |
| 18087579 | ELECTRONIC COMPONENT COMPRISING A 3D CAPACITIVE STRUCTURE | December 2022 | May 2025 | Allow | 29 | 0 | 0 | No | No |
| 18083921 | MEMORY CELL WITH IMPROVED INSULATING STRUCTURE | December 2022 | October 2025 | Allow | 34 | 1 | 1 | No | No |
| 18083118 | LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE | December 2022 | December 2023 | Allow | 12 | 1 | 0 | No | No |
| 18080740 | SEMICONDUCTOR PACKAGES HAVING THERMAL CONDUCTIVE PATTERN | December 2022 | May 2024 | Allow | 17 | 1 | 0 | No | No |
| 18064341 | Interconnect Structure Having a Carbon-Containing Barrier Layer | December 2022 | October 2023 | Allow | 10 | 1 | 0 | No | No |
| 18078349 | MEMORY DEVICE HAVING ULTRA-LIGHTLY DOPED REGION | December 2022 | September 2025 | Allow | 33 | 1 | 1 | No | No |
| 18062811 | SEMICONDUCTOR DEVICE HAVING AN UPPER END OF A LOWER SPACER STRUCTURE ON A LEVEL SAME AS OR LOWER THAN A LOWER END OF A STORAGE NODE CONTACT | December 2022 | July 2025 | Allow | 32 | 0 | 1 | No | No |
| 18072348 | DYNAMIC RANDOM ACCESS MEMORY STRUCTURE AND A METHOD FOR FORMING THE SAME | November 2022 | August 2025 | Allow | 32 | 2 | 1 | No | No |
| 17993902 | SEMICONDUCTOR MEMORY DEVICE HAVING A BIT LINE CONTACT DISPOSED IN THE SUBSTRATE | November 2022 | June 2025 | Allow | 31 | 0 | 1 | No | No |
| 17989791 | A PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD | November 2022 | November 2024 | Allow | 24 | 2 | 1 | Yes | No |
| 17988071 | SEMICONDUCTOR DEVICE HAVING A LATERAL CONDUCTIVE LINE INCLUDED LOW AND HIGH WORK FUNCTION ELECTRODES | November 2022 | July 2025 | Allow | 32 | 0 | 1 | No | No |
| 17983402 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR LAYERS DISPOSED BETWEEN UPPER PORTIONS OF THE ISOLATION STRUCTURES AND THE ACTIVE REGIONS | November 2022 | November 2024 | Allow | 25 | 0 | 1 | No | No |
| 17981719 | SEMICONDUCTOR MEMORY DEVICE HAVING SHIELD LAYER BETWEEN PERIPHERAL CIRCUIT AND CELL ARRAY STRUCTURES | November 2022 | May 2025 | Allow | 30 | 0 | 1 | No | No |
| 17980897 | DISPLAY DEVICE INCLUDING A PLURALITY OF LAYERS EACH INCLUDING A LIGHT EMITTING LAYER | November 2022 | October 2023 | Allow | 11 | 1 | 0 | No | No |
| 17980345 | Multi-Transistor Stack Architecture In A Single Vertical Stack | November 2022 | March 2024 | Allow | 16 | 0 | 1 | No | No |
| 17973219 | INTEGRATED POWER SWITCHING DEVICE HEAT SINK | October 2022 | April 2025 | Allow | 30 | 0 | 0 | No | No |
| 18047704 | SEMICONDUCTOR MEMORY DEVICE HAVING BIT LINES WITH DIFFERENT HEIGHT | October 2022 | July 2025 | Allow | 33 | 0 | 0 | No | No |
| 17969663 | PHOTOSENSOR HAVING A SCATTERING STRUCTURE COMPRISES CIRCULAR RING AND PERIPHERAL PATTERNS | October 2022 | April 2025 | Allow | 29 | 0 | 0 | No | No |
| 17961806 | A TOUCH PANEL HAVING A PHOTOELECTRIC CONVERSION ELEMENT BETWEEN THE FIRST AND SECOND FLEXIBLE SUBSTRATES | October 2022 | May 2023 | Allow | 7 | 0 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PHAM, HOAI V.
With a 28.6% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 35.3% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner PHAM, HOAI V works in Art Unit 2892 and has examined 1,398 patent applications in our dataset. With an allowance rate of 93.3%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.
Examiner PHAM, HOAI V's allowance rate of 93.3% places them in the 80% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by PHAM, HOAI V receive 0.71 office actions before reaching final disposition. This places the examiner in the 4% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by PHAM, HOAI V is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a -9.5% benefit to allowance rate for applications examined by PHAM, HOAI V. This interview benefit is in the 3% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 38.0% of applications are subsequently allowed. This success rate is in the 87% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 36.0% of cases where such amendments are filed. This entry rate is in the 54% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 100.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 74% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.
This examiner withdraws rejections or reopens prosecution in 50.0% of appeals filed. This is in the 18% percentile among all examiners. Of these withdrawals, 42.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 63.6% are granted (fully or in part). This grant rate is in the 68% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 9.7% of allowed cases (in the 93% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.8% of allowed cases (in the 67% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.