Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18743155 | METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING AN AIR GAP BETWEEN A CONTACT PAD AND A SIDEWALL OF CONTACT HOLE | June 2024 | May 2025 | Allow | 11 | 0 | 0 | No | No |
| 18741771 | DISPLAY DEVICE HAVING A CONDUCTIVE METAL LAYER DISPOSED ON A SURFACE OF AN ANTIREFLECTION LAYER | June 2024 | April 2025 | Allow | 10 | 0 | 0 | No | No |
| 18735864 | INTEGRATED ASSEMBLIES WHICH INCLUDE STACKED MEMORY DECKS, AND METHODS OF FORMING INTEGRATED ASSEMBLIES | June 2024 | May 2025 | Allow | 11 | 0 | 0 | No | No |
| 18677617 | DISPLAY SUBSTRATE WITH PIXEL OPENING AREAS, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE | May 2024 | April 2025 | Allow | 11 | 0 | 0 | No | No |
| 18653289 | Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies | May 2024 | June 2025 | Allow | 13 | 1 | 0 | No | No |
| 18583157 | METHOD OF FORMING LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE | February 2024 | October 2024 | Allow | 8 | 0 | 0 | No | No |
| 18581826 | INTERCONNECTION STRUCTURE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME | February 2024 | February 2025 | Allow | 12 | 2 | 0 | No | No |
| 18444790 | MEMORY STRUCTURE HAVING POLYGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGION | February 2024 | November 2024 | Allow | 9 | 0 | 1 | No | No |
| 18440347 | VERTICAL DEVICE HAVING A PROTRUSION SOURCE | February 2024 | March 2025 | Allow | 13 | 1 | 0 | No | No |
| 18423648 | DIELECTRIC PROTECTION LAYER IN MIDDLE-OF-LINE INTERCONNECT STRUCTURE MANUFACTURING METHOD | January 2024 | January 2025 | Allow | 12 | 0 | 1 | No | No |
| 18418795 | VERTICAL FIELD-EFFECT TRANSISTOR DEVICES HAVING GATE LINER | January 2024 | September 2024 | Allow | 8 | 0 | 0 | No | No |
| 18416598 | DISPLAY DEVICE INCLUDING A PLURALITY OF LAYERS EACH INCLUDING A LIGHT EMITTING LAYER | January 2024 | January 2025 | Allow | 12 | 1 | 0 | No | No |
| 18415702 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE HAVING A PLURALITY OF FINS | January 2024 | September 2024 | Allow | 8 | 0 | 0 | No | No |
| 18538358 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A SINGLE CRYSTAL STORAGE CONTACT | December 2023 | September 2024 | Allow | 9 | 0 | 0 | No | No |
| 18528707 | MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION | December 2023 | December 2024 | Allow | 12 | 1 | 0 | No | No |
| 18524794 | METHOD OF FORMING CONTACT INCLUDED IN SEMICONDUCTOR DEVICE | November 2023 | November 2024 | Allow | 11 | 1 | 0 | No | No |
| 18525187 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES | November 2023 | September 2024 | Allow | 10 | 0 | 0 | No | No |
| 18521584 | FINFET STRUCTURE WITH A COMPOSITE STRESS LAYER AND REDUCED FIN BUCKLING | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18515181 | LIGHT EMITTING DISPLAY PANEL INCLUDING PLURALITY OF ORGANIC AND INORGANIC LAYERS AND METHOD OF MANUFACTURING THE SAME | November 2023 | January 2025 | Allow | 14 | 2 | 0 | No | No |
| 18504567 | ORGANIC LIGHT-EMITTING COMPONENT HAVING A LIGHT-EMITTING LAYER AS PART OF A CHARGE GENERATION LAYER | November 2023 | January 2025 | Allow | 14 | 1 | 0 | No | No |
| 18498718 | METHOD OF DIRECT-BONDED OPTOELECTRONIC DEVICES | October 2023 | September 2024 | Allow | 11 | 0 | 0 | Yes | No |
| 18383086 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF INSULATORS | October 2023 | July 2024 | Allow | 9 | 0 | 0 | No | No |
| 18370927 | LIGHT-EMITTING DEVICE WITH CIRCULAR POLARIZING PLATE OVER BONDING LAYER | September 2023 | October 2024 | Allow | 13 | 1 | 0 | No | No |
| 18470446 | SEMICONDUCTOR DEVICE WITH DIELECTRIC STRUCTURE HAVING ENLARGEMANT PORTION SURROUNDING WORD LINE | September 2023 | December 2024 | Allow | 15 | 1 | 0 | No | No |
| 18470410 | SEMICONDUCTOR DEVICE WITH POROUS SPACER MADE OF LOW-K MATERIAL AND MANUFACTURING METHOD THEREOF | September 2023 | March 2025 | Allow | 18 | 2 | 0 | No | No |
| 18362770 | PHASE CHANGE MEMORY DEVICE HAVING TAPERED PORTION OF THE BOTTOM MEMORY LAYER | July 2023 | June 2024 | Allow | 11 | 0 | 0 | No | No |
| 18227361 | SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR LAYER CONTAINING A C-AXIS ALIGNED CRYSTAL | July 2023 | September 2024 | Allow | 14 | 1 | 0 | No | No |
| 18224691 | SOLID-STATE IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS HAVING A DIVIDED PIXEL SEPARATION WALL | July 2023 | May 2024 | Allow | 10 | 0 | 0 | No | No |
| 18354844 | A DUMMY FIN BETWEEN FIRST AND SECOND SEMICONDUCTOR FINS | July 2023 | July 2024 | Allow | 12 | 0 | 0 | No | No |
| 18350838 | Doping for Semiconductor Device with Conductive Feature | July 2023 | February 2024 | Allow | 7 | 0 | 0 | No | No |
| 18218762 | Integrated Assemblies Which Include Stacked Memory Decks, and Methods of Forming Integrated Assemblies | July 2023 | February 2024 | Allow | 7 | 0 | 0 | No | No |
| 18338726 | METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES HAVING ALIGNMENT MARKS ON A CARRIER SUBSTRATE | June 2023 | February 2024 | Allow | 8 | 0 | 0 | No | No |
| 18207689 | SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE HAVING FIRST PORTION AND SECOND PORTION AND METHOD FOR MANUFACTURING THE SAME | June 2023 | May 2024 | Allow | 11 | 1 | 0 | Yes | No |
| 18206512 | DIRECT-BONDED LED ARRAYS AND DRIVERS | June 2023 | July 2024 | Allow | 14 | 1 | 0 | Yes | No |
| 18323458 | ARRAY BOUNDARY STRUCTURE TO REDUCE DISHING | May 2023 | June 2024 | Allow | 13 | 0 | 0 | No | No |
| 18301572 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING MULTI-WORK FUNCTION GATE ELECTRODE | April 2023 | January 2024 | Allow | 9 | 0 | 0 | No | No |
| 18193965 | RESISTIVE MEMORY CELL HAVING AN OVONIC THRESHOLD SWITCH | March 2023 | May 2024 | Allow | 14 | 0 | 1 | No | No |
| 18193544 | SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT | March 2023 | April 2024 | Allow | 13 | 1 | 0 | No | No |
| 18186935 | METHOD OF MANUFACTURING MEMORY STRUCTURE HAVING A HEXAGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGION | March 2023 | December 2023 | Allow | 9 | 0 | 0 | No | No |
| 18174902 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE HAVING A CONTACT CAPPING LAYER | February 2023 | December 2023 | Allow | 9 | 0 | 0 | No | No |
| 18110999 | Light-Emitting Element Having An Organic Compound And A Transition Metal | February 2023 | December 2023 | Allow | 10 | 0 | 0 | No | No |
| 18108666 | SEMICONDUCTOR MEMORY DEVICE HAVING BIT LINES AND ISOLATION FINS DISPOSED ON THE SUBSTRATE | February 2023 | August 2024 | Allow | 18 | 2 | 0 | No | No |
| 18108003 | MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION | February 2023 | September 2023 | Allow | 7 | 0 | 0 | No | No |
| 18107853 | DISPLAY PANEL | February 2023 | April 2024 | Abandon | 14 | 1 | 0 | No | No |
| 18161836 | LIFT-OFF PROCESS FOR MANUFACTURING AN ORGANIC LIGHT-EMITTING DISPLAY APPARATUS | January 2023 | October 2023 | Allow | 9 | 0 | 0 | No | No |
| 18095973 | STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS FOR FORMING SUCH | January 2023 | October 2023 | Allow | 9 | 0 | 0 | No | No |
| 18093561 | SEMICONDUCTOR MEMORY DEVICE HAVING AN OHMIC CONTACT ON THE IMPURITY REGIONS | January 2023 | June 2025 | Allow | 29 | 0 | 0 | No | No |
| 18149178 | METHOD OF FORMING BIT LINE CONTACT STRUCTURE USING SERIES OF PICKLING PROCESSES TO REMOVE NATIVE OXIDE ON SURFACE OF THE ACTIVE AREAS | January 2023 | March 2025 | Allow | 26 | 0 | 1 | No | No |
| 18146962 | STRAINED-CHANNEL FIN FETS | December 2022 | September 2024 | Allow | 21 | 1 | 1 | No | No |
| 18087579 | ELECTRONIC COMPONENT COMPRISING A 3D CAPACITIVE STRUCTURE | December 2022 | May 2025 | Allow | 29 | 0 | 0 | No | No |
| 18083118 | LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE | December 2022 | December 2023 | Allow | 12 | 1 | 0 | No | No |
| 18080740 | SEMICONDUCTOR PACKAGES HAVING THERMAL CONDUCTIVE PATTERN | December 2022 | May 2024 | Allow | 17 | 1 | 0 | No | No |
| 18064341 | Interconnect Structure Having a Carbon-Containing Barrier Layer | December 2022 | October 2023 | Allow | 10 | 1 | 0 | No | No |
| 17993902 | SEMICONDUCTOR MEMORY DEVICE HAVING A BIT LINE CONTACT DISPOSED IN THE SUBSTRATE | November 2022 | June 2025 | Allow | 31 | 0 | 1 | No | No |
| 17989791 | A PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD | November 2022 | November 2024 | Allow | 24 | 2 | 1 | Yes | No |
| 17983402 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR LAYERS DISPOSED BETWEEN UPPER PORTIONS OF THE ISOLATION STRUCTURES AND THE ACTIVE REGIONS | November 2022 | November 2024 | Allow | 25 | 0 | 1 | No | No |
| 17981719 | SEMICONDUCTOR MEMORY DEVICE HAVING SHIELD LAYER BETWEEN PERIPHERAL CIRCUIT AND CELL ARRAY STRUCTURES | November 2022 | May 2025 | Allow | 30 | 0 | 1 | No | No |
| 17980897 | DISPLAY DEVICE INCLUDING A PLURALITY OF LAYERS EACH INCLUDING A LIGHT EMITTING LAYER | November 2022 | October 2023 | Allow | 11 | 1 | 0 | No | No |
| 17980345 | Multi-Transistor Stack Architecture In A Single Vertical Stack | November 2022 | March 2024 | Allow | 16 | 0 | 1 | No | No |
| 17973219 | INTEGRATED POWER SWITCHING DEVICE HEAT SINK | October 2022 | April 2025 | Allow | 30 | 0 | 0 | No | No |
| 17969663 | PHOTOSENSOR HAVING A SCATTERING STRUCTURE COMPRISES CIRCULAR RING AND PERIPHERAL PATTERNS | October 2022 | April 2025 | Allow | 29 | 0 | 0 | No | No |
| 17961806 | A TOUCH PANEL HAVING A PHOTOELECTRIC CONVERSION ELEMENT BETWEEN THE FIRST AND SECOND FLEXIBLE SUBSTRATES | October 2022 | May 2023 | Allow | 7 | 0 | 0 | No | No |
| 17915991 | METHOD OF FORMING A BIT LINE STRUCTURE | September 2022 | June 2025 | Allow | 33 | 1 | 1 | No | No |
| 17954676 | DISPLAY APPARATUS HAVING A LIGHT EMITTING LAYER DISPOSED IN A PORTION OF THE OPENING PERIPHERAL AREA | September 2022 | June 2023 | Allow | 8 | 0 | 0 | No | No |
| 17954221 | SEMICONDUCTOR STRUCTURE HAVING ISOLATION STRUCTURE EMBEDDED IN THE GROOVE OF THE BIT LINE | September 2022 | February 2025 | Allow | 28 | 0 | 1 | No | No |
| 17953054 | SEMICONDUCTOR DEVICE HAVING AN AIR GAP SURROUNDING A PORTION OF A CONDUCTIVE CONTACT LAYER | September 2022 | May 2025 | Allow | 32 | 0 | 0 | No | No |
| 17952265 | SEMICONDUCTOR STRUCTURE HAVING TWO WORD LINES COVERING PART OF OPPOSITE SIDE SURFACES OF THE PLURALITY OF SEMICONDUCTOR CHANNELS | September 2022 | March 2025 | Allow | 30 | 0 | 1 | No | No |
| 17951077 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF TRENCHES WITH DIFFERENT DEPTH | September 2022 | February 2025 | Allow | 29 | 0 | 1 | No | No |
| 17946063 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING A DEVICE HAVING SOURCE REGION WITH DIFFERENT DOPING TYPES IN HORIZONTAL DIRECTION | September 2022 | March 2025 | Allow | 30 | 0 | 0 | No | No |
| 17932276 | SEMICONDUCTOR STRUCTURE HAVING A PLURALITY OF BIT LINES SPACED APART FROM EACH OTHER IN A FIRST DIRECTION AND EXTEND IN A SECOND DIRECTION | September 2022 | April 2025 | Allow | 31 | 0 | 1 | No | No |
| 17939414 | SEMICONDUCTOR DEVICE HAVING METAL NITRIDE GATE DOPED WITH A LOW WORK FUNCTION | September 2022 | July 2025 | Allow | 34 | 0 | 1 | No | No |
| 17901853 | SEMICONDUCTOR STRUCTURE FOR DRAM HAVING A PILLAR LOWER ELECTRODE AND FORMATION METHOD THEREOF | September 2022 | May 2025 | Allow | 32 | 1 | 1 | No | No |
| 17897556 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR DIE EMBEDDED BETWEEN AN EXTENDED SUBSTRATE AND A BOTTOM SUBSTRATE | August 2022 | June 2024 | Allow | 21 | 1 | 1 | No | No |
| 17892275 | SEMICONDUCTOR DEVICES HAVING A GRAPHENE PATTERN BETWEEN THE FIRST CONDUCTIVE PATTERN AND THE BIT LINE CAPPING | August 2022 | January 2025 | Allow | 29 | 0 | 0 | No | No |
| 17886546 | DISPLAY PANEL HAVING LIGHT SHIELDING MEMBER WITH DIFFERENT THICKNESS | August 2022 | March 2025 | Allow | 31 | 0 | 0 | No | No |
| 17879779 | METHOD FOR FORMING A FIRST AND A SECOND TRANSISTORS ARRAY HAVING PLURALITY OF FIRST AND SEMICONDUCTOR PILLARS | August 2022 | February 2025 | Allow | 31 | 0 | 1 | No | No |
| 17876330 | FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING | July 2022 | September 2023 | Allow | 14 | 1 | 0 | No | No |
| 17815623 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD USING DIFFERENT ION IMPLANTATION ENERGY | July 2022 | September 2024 | Allow | 25 | 0 | 0 | No | No |
| 17795121 | Semiconductor Structure Having Silicide Layer Disposed On Sidewalls Of The Bitline | July 2022 | June 2025 | Allow | 35 | 0 | 1 | No | No |
| 17872452 | Doping for Semiconductor Device with Conductive Feature | July 2022 | April 2023 | Allow | 9 | 0 | 0 | No | No |
| 17868683 | Method of Forming Integrated Assemblies having Transistors Configured for High-Voltage Applications | July 2022 | February 2024 | Allow | 19 | 3 | 0 | No | No |
| 17867432 | METHOD FOR FORMING BURIED BIT LINES IN THE BIT LINE TRENCHS | July 2022 | January 2025 | Allow | 30 | 0 | 1 | No | No |
| 17866066 | METHOD OF FORMING AN ARRAY OF MULTI-STACK NANOSHEET STRUCTURES HAVING A DAM STRUCTURE ISOLATING MULTI-STACK TRANSISTORS | July 2022 | April 2023 | Allow | 9 | 0 | 0 | No | No |
| 17863468 | SOLID-STATE IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS HAVING A SEPARATION WALL BETWEEN THE FIRST PHOTODIODE AND THE SECOND PHOTODIODE | July 2022 | April 2023 | Allow | 9 | 0 | 0 | No | No |
| 17860721 | SEMICONDUCTOR DEVICE HAVING TRENCH POSITIONED IN A SUBSTRATE AND ALIGNED WITH A SIDE WALL OF A BIT LINE CONTACT PLUG | July 2022 | September 2023 | Allow | 14 | 1 | 0 | No | No |
| 17858986 | METHOD FORMING A SEMICONDUCTOR DEVICE STRUCTURE HAVING AN UNDERGROUND INTERCONNECTION EMBEDDED INTO A SILICON SUBSTRATE | July 2022 | September 2024 | Allow | 26 | 1 | 1 | No | No |
| 17858055 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY HAVING A SECOND ACTIVE REGION DISPOSED AT AN OUTER SIDE OF A FIRST ACTIVE REGION | July 2022 | March 2023 | Allow | 9 | 0 | 0 | No | No |
| 17851865 | Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells | June 2022 | December 2024 | Allow | 30 | 0 | 0 | No | No |
| 17807837 | METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE USING A FIRST MASK COMPRISES A GFROOVE | June 2022 | May 2024 | Allow | 23 | 0 | 0 | No | No |
| 17844573 | SEMICONDUCTOR APPARATUS HAVING A SILICIDE BETWEEN TWO DEVICES | June 2022 | August 2023 | Allow | 14 | 1 | 0 | No | No |
| 17784857 | ELECTRONIC COMPONENT WITH DIELECTRIC FILM AND MANUFACTURING METHOD | June 2022 | April 2025 | Allow | 34 | 1 | 1 | No | No |
| 17837718 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE | June 2022 | November 2023 | Allow | 17 | 0 | 0 | No | No |
| 17837052 | SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE | June 2022 | November 2023 | Allow | 17 | 0 | 0 | No | No |
| 17834982 | FLASH MEMORY DEVICES WITH THICKENED SOURCE/DRAIN SILICIDE | June 2022 | December 2024 | Allow | 30 | 0 | 1 | No | No |
| 17834869 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE HAVING A SEED LAYER ON A SUBSTRATE | June 2022 | April 2023 | Allow | 10 | 0 | 0 | No | No |
| 17805738 | METHOD FOR MANUFACTURING SEMICONDUCTOR BIT LINE CONTACT REGION WITH DIFFERENT DOPED IMPURITY CONCENTRATIONS | June 2022 | August 2024 | Allow | 26 | 0 | 1 | No | No |
| 17805036 | 3D Stacking Architecture Through TSV and Methods Forming Same | June 2022 | June 2025 | Allow | 37 | 1 | 1 | No | No |
| 17824905 | MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, SEMICONDUCTOR STRUCTURE HAVING A CAPACITOR STRUCTURE SURROUNDED ON THE OUTER SIDE OF THE WORD LINE | May 2022 | December 2024 | Allow | 31 | 0 | 1 | No | No |
| 17752869 | METHOD FOR MAKING SEMICONDUCTOR DEVICE USING A STRESS MEMORIZATION TECHNIQUE | May 2022 | October 2024 | Allow | 29 | 0 | 0 | No | No |
| 17664853 | DISPLAY DEVICE INCLUDING AN EMISSION DEFINING LAYER AND METHOD FOR FABRICATION THEREOF | May 2022 | February 2025 | Allow | 33 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PHAM, HOAI V.
With a 33.3% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 37.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner PHAM, HOAI V works in Art Unit 2892 and has examined 1,487 patent applications in our dataset. With an allowance rate of 94.4%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 16 months.
Examiner PHAM, HOAI V's allowance rate of 94.4% places them in the 84% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.
On average, applications examined by PHAM, HOAI V receive 0.66 office actions before reaching final disposition. This places the examiner in the 5% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.
The median time to disposition (half-life) for applications examined by PHAM, HOAI V is 16 months. This places the examiner in the 98% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a -7.6% benefit to allowance rate for applications examined by PHAM, HOAI V. This interview benefit is in the 2% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 38.8% of applications are subsequently allowed. This success rate is in the 86% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.
This examiner enters after-final amendments leading to allowance in 37.7% of cases where such amendments are filed. This entry rate is in the 50% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.
When applicants request a pre-appeal conference (PAC) with this examiner, 100.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 73% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.
This examiner withdraws rejections or reopens prosecution in 53.8% of appeals filed. This is in the 20% percentile among all examiners. Of these withdrawals, 42.9% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner rarely withdraws rejections during the appeal process compared to other examiners. If you file an appeal, be prepared to fully prosecute it to a PTAB decision. Per MPEP § 1207, the examiner will prepare an Examiner's Answer maintaining the rejections.
When applicants file petitions regarding this examiner's actions, 56.3% are granted (fully or in part). This grant rate is in the 71% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 8.3% of allowed cases (in the 94% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.7% of allowed cases (in the 63% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.