USPTO Art Unit 2183 Prosecution Statistics

Art Unit Information

Art Unit: 2183
Group: 2180
Tech Center: 2100
Total Cases: 9,670
Last Active: July 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19273567SYSTEMS AND METHODS FOR IMPLEMENTING DIRECTIONAL OPERAND BROADCAST AND MULTIPLY-ACCUMULATE EXECUTION USING A CONFIGURABLE PATCH MESH IN A MULTI-CORE PROCESSING ARRAY OF AN INTEGRATED CIRCUITJuly 2025November 2025Allow410YesNo
19017416Translating Between CXL.mem and CXL.cache Read TransactionsJanuary 2025March 2025Allow200NoNo
19002787Illegal Address Mask Method and Device for Cores of DSPDecember 2024March 2025Allow200NoNo
18979402PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSINGDecember 2024July 2025Allow710NoNo
18956439DMA CONTROLLER AND LSU TO TRANSPOSE DATA ARRAYS STORED IN MAIN MEMORY FOR STORAGE IN PROCESSOR REGISTERSNovember 2024December 2025Allow1300NoNo
18930522STORAGE DEVICE PROVIDING DIRECT MEMORY ACCESS, COMPUTING SYSTEM INCLUDING THE STORAGE DEVICE AND OPERATING METHOD OF THE STORAGE DEVICEOctober 2024March 2026Allow1700NoNo
18929778SEMICONDUCTOR DEVICEOctober 2024January 2026Allow1500NoNo
18926607METHODS AND SYSTEMS TO MONITOR A MEDIA DEVICE VIA A USB PORTOctober 2024January 2026Allow1500NoNo
18925482SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMATOctober 2024October 2025Allow1100NoNo
18922873Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing GridOctober 2024October 2025Allow1200NoNo
18920691SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSEOctober 2024January 2026Allow1500NoNo
18919332MULTI-CARD PROCESSOR ACCESS FRAMEWORKOctober 2024February 2026Allow1610YesNo
18915445SYSTEMS AND METHODS FOR OPERATING A SERIAL PERIPHERAL INTERFACE (SPI) NETWORKOctober 2024January 2026Allow1500NoNo
18908532APPARATUSES AND METHODS FOR GENERATING A UNIQUE IDENTIFIER IN A MEMORY FOR I3C PROTOCOLOctober 2024January 2026Allow1600NoNo
18906205MIXED-SOURCED DEPENDENCY CONTROL FOR VECTOR INSTRUCTIONSOctober 2024September 2025Allow1200NoNo
18906697ADAPTIVE BUFFER SHARING IN MULTI-CORE RECONFIGURABLE STREAMING-BASED ARCHITECTURESOctober 2024September 2025Allow1100NoNo
18903484LOW-PRECISION COMPUTATIONOctober 2024October 2025Allow1300NoNo
18900528CIRCUITRY AND METHODS FOR A CONDITIONAL FENCE INSTRUCTIONSeptember 2024October 2025Allow1300NoNo
18898309INSTRUCTION TRANSLATION METHOD AND RELATED DEVICE THEREOFSeptember 2024February 2026Allow1601NoNo
18896226PREDICTION UNIT WITH FIRST PREDICTOR THAT PROVIDES A HASHED FETCH ADDRESS OF A CURRENT FETCH BLOCK TO ITS OWN INPUT AND TO A SECOND PREDICTOR THAT USES IT TO PREDICT THE FETCH ADDRESS OF A NEXT FETCH BLOCKSeptember 2024September 2025Allow1200NoNo
18896789IMPROVING COMPUTING EFFICIENCY OF A PROCESSOR BY OPTIMIZING A COMPUTATIONAL SIZE OF EACH COMPUTING CORE IN THE PROCESSORSeptember 2024March 2025Allow610NoNo
18891841I/O CARRIER AND BACKPLANE FOR INDUSTRIAL PROCESS CONTROL SYSTEMSSeptember 2024October 2025Allow1300NoNo
18888365ENABLING HIGH-PERFORMANCE SCALABLE MATRIX EXTENSION (SME) INSTRUCTION ISSUE IN PROCESSOR DEVICESSeptember 2024August 2025Allow1100YesNo
18889148SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONSSeptember 2024January 2026Allow1610NoNo
18887237I/O MODULE ARRANGEMENTSeptember 2024March 2026Allow1810NoNo
18886319POWER EFFICIENT MULTI-BIT STORAGE SYSTEMSeptember 2024September 2025Allow1210NoNo
18886639SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTSSeptember 2024November 2025Allow1400NoNo
18884533ACCELERATION DEVICE ARCHITECTURE FOR NEAR I/O PIPELINE COMPUTING AND AI ACCELERATION SYSTEMSeptember 2024October 2025Allow1300NoNo
18884854Mechanisms For Arbitrating Among Packets In Hierarchical Arbitration ArchitectureSeptember 2024January 2026Allow1600NoNo
18830458VECTOR COMPUTATIONAL UNITSeptember 2024October 2025Allow1300YesNo
18830123COMPUTATIONAL MEMORYSeptember 2024December 2025Allow1500NoNo
18830104WRITE BUFFER CIRCUIT SUPPORTING STORE RELEASE COMBINING OF STORE OPERATIONS FROM A MEMORY ACCESS STAGE OF A PROCESSOR INSTRUCTION PIPELINE FOR EFFICIENT PROCESSING OF STORE RELEASE INSTRUCTIONS, AND RELATED METHODSSeptember 2024September 2025Allow1200NoNo
18828069VISION PROCESSING ACCELERATOR WITH LOW LATENCY IMAGE DISTORTION PROCESSING PIPELINESSeptember 2024February 2026Allow1710NoNo
18827415PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONSSeptember 2024October 2025Allow1300NoNo
18817355SELECTING A CANDIDATE CONSUMER INSTRUCTION BASED ON AN OBSERVED INSTRUCTION HAVING A DEPENDENCY MARKED SOURCE OPERAND FROM PRODUCER DATA OF A PRODUCER INSTRUCTIONAugust 2024January 2026Allow1710NoNo
18818134Operand Selection CircuitryAugust 2024March 2026Allow1810NoNo
18817548SHARING LOOP CACHE INSTANCES AMONG MULTIPLE THREADS IN PROCESSOR DEVICESAugust 2024August 2025Allow1100NoNo
18816339APPARATUS AND METHODS FOR ESTABLISHING LINK BANDWIDTHS WITHIN DIE INTERCONNECT ARCHITECTURESAugust 2024March 2026Allow6010NoNo
18815382SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADDAugust 2024March 2026Allow1910NoNo
18814641MEMORY DEVICE AND METHOD WITH PROCESSING-IN-MEMORY BLOCKAugust 2024January 2026Allow1710YesNo
18813657DYNAMIC RECONFIGURATION OF A MULTI-CORE PROCESSOR TO A UNIFIED COREAugust 2024July 2025Allow1100YesNo
18841082LOOPING INSTRUCTIONAugust 2024January 2026Allow1610NoNo
18812627PCIE RETIMER WITH REDUCED POWER LOW LATENCY MODEAugust 2024September 2025Allow1300NoNo
18811392PROCESSOR AND COMPILER FOR SECURE MULTIPARTY COMPUTATIONAugust 2024March 2026Allow1911NoNo
18805711LOOK-UP TABLE READAugust 2024February 2026Allow1810NoNo
18800423Thread Creation on Local or Remote Compute Elements by a Multi-Threaded, Self-Scheduling ProcessorAugust 2024January 2026Allow1710NoNo
18798035PROCESSOR, METHOD, AND SYSTEM FOR ACCELERATING TENSOR TRANSPOSE FOR MACHINE LEARNINGAugust 2024February 2026Allow1910YesNo
18797799TRACKING NEAR-IDENTICAL MEMORY ADDRESSES AND REDUCING MEMORY ACCESS REQUESTSAugust 2024February 2026Allow1810NoNo
18796511NIC LINE-RATE HARDWARE PACKET PROCESSINGAugust 2024September 2025Allow1400NoNo
18794143SYSTEM AND METHOD FOR OPTIMIZING DATA-TRANSFER AMONG MULTIPLE COMPUTE UNITS IN A DATA-PARALLEL COMPUTING SYSTEMAugust 2024March 2026Allow1910NoNo
18788391METHOD TO RESET CONFIGURABLE UNITS IN A RECONFIGURABLE PROCESSORJuly 2024March 2026Allow1910NoNo
18833997DECODING METHOD OF SIMULTANEOUSLY MULTI-THREADING PROCESSOR, PROCESSOR, AND CHIPJuly 2024September 2025Allow1300NoNo
18785094BIDIRECTIONAL RING-BASED INTERCONNECTION NETWORKS HAVING A CROSS BAR FOR MULTIPROCESSORSJuly 2024September 2025Allow1400NoNo
18781952CONTROLLERS IN DATA PROCESSING ENGINE COLUMNSJuly 2024February 2026Allow1810YesNo
18781989CONFIGURING PCI EXPRESS MODULE USING HARDWARE IN A MEMORY SUB-SYSTEMJuly 2024November 2025Allow1500NoNo
18832245SERVER DELAY CONTROL DEVICE, SERVER DELAY CONTROL METHOD AND PROGRAMJuly 2024September 2025Allow1300NoNo
18779980STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME TRACKINGJuly 2024March 2026Allow2010NoNo
18779177TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTSJuly 2024November 2025Allow1500NoNo
18777537CLIPPING OPERATIONS USING PARTIAL CLIP INSTRUCTIONSJuly 2024July 2025Allow1200NoNo
18775652SOFTWARE VISIBLE AND CONTROLLABLE LOCK-STEPPING WITH CONFIGURABLE LOGICAL PROCESSOR GRANULARITIESJuly 2024August 2025Allow1300NoNo
18775443Configuration Data Store in a Reconfigurable Data Processor Having Two Access ModesJuly 2024January 2026Allow1810NoNo
18773632PROCESSOR WITH ONE OR MORE PROGRESSIVE CONSERVATIVE EXECUTION MODESJuly 2024November 2025Allow1610NoNo
18774243DYNAMIC PROCESSING MEMORY CORE ON A SINGLE MEMORY CHIPJuly 2024December 2025Abandon1720NoNo
18774678Cached Instruction Recoding for Prediction EmbeddingJuly 2024February 2026Allow1920NoNo
18772379PORT REPLICATORJuly 2024August 2025Allow1300NoNo
18772354MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICEJuly 2024February 2025Allow700NoNo
18770560Schedule Instructions of a Program of Data Flows for Execution in Tiles of a Coarse Grained Reconfigurable ArrayJuly 2024July 2025Allow1220NoNo
18770092Computing System, Method, and Apparatus, and Acceleration DeviceJuly 2024March 2026Allow2010NoNo
18769220HARDWARE ACCELERATOR WITH CONFIGURABLE TENSOR OPERATION PIPELINEJuly 2024February 2026Allow2010NoNo
18769206PROCESSING FOR PROCESSORS PERFORMING TASKS HAVING FORWARD CONDITIONAL BRANCH INSTRUCTIONSJuly 2024September 2025Allow1400NoNo
18768239MICROPROCESSOR VALIDATION USING RANDOM PREPACKAGED GENERATED TEST FUNCTIONS AND USER LEVEL SCHEDULERJuly 2024February 2026Allow2000NoNo
18762987SORTING VECTOR ELEMENTS USING A COUNT VALUEJuly 2024September 2025Allow1500NoNo
18761582BRANCH PREDICTIONJuly 2024July 2025Allow1200YesNo
18758923SHARED RESOURCE MANAGEMENT IN PARTITIONED SYSTEMSJune 2024October 2025Allow1600NoNo
18725085DATA PROCESSING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND READABLE STORAGE MEDIUMJune 2024January 2025Allow700YesNo
18757003SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTSJune 2024January 2026Allow1910NoNo
18756091COMMUNICATION ARCHITECTURE FOR MULTICORE SYSTEMJune 2024August 2025Allow1400NoNo
18756083SHARED QUEUE FOR DATA EXCHANGE BETWEEN STACKSJune 2024August 2025Allow1400NoNo
18754594INSTRUCTION FETCHINGJune 2024February 2026Allow2010NoNo
18752518STRIDE LENGTH PREDICATE CREATIONJune 2024July 2025Allow1300NoNo
18749599VECTOR MASK BUFFERS IN A VECTOR INSTRUCTION EXECUTION PIPELINEJune 2024December 2025Allow1810NoNo
18748324Chip Management Apparatus and Related MethodJune 2024November 2025Allow1710NoNo
18747410INTEGRATED CIRCUIT GENERATION WITH IMPROVED INTERCONNECTJune 2024December 2025Allow1810YesNo
18721358Method and Apparatus for Optimizing Server System Interrupts, Device and MediumJune 2024November 2025Allow1700NoNo
18745756PREDICTION CIRCUITRY USING A PREDICTION TABLE PROVIDING A SKIP-FETCH-INSTRUCTION ENTRYJune 2024February 2026Allow2010YesNo
18743637CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSORJune 2024August 2025Allow1410YesNo
18744042Data Processing System and MethodJune 2024July 2025Allow1300NoNo
18742976RESERVATION STATION WITH MULTIPLE ENTRY TYPESJune 2024January 2026Allow1910YesNo
18741186COMPUTING CHIP AND INSTRUCTION PROCESSING METHOD TO ACCESS SOURCE OPERANDS IN PRIVATE REGISTERS USING A RELATIVE DISTANCE INDEXJune 2024January 2026Allow1910NoNo
18740430Processing of Synchronization Barrier InstructionsJune 2024February 2026Allow2020YesNo
18739272TWO-LEVEL ARBITRATION IN A COMPUTING SYSTEMJune 2024April 2025Allow1110NoNo
18739070Load Instruction FusionJune 2024October 2025Allow1610YesNo
18717527METHOD AND SYSTEM FOR ASSIGNING INSTRUCTIONS TO DECODERS IN DECODER CLUSTERSJune 2024December 2025Allow1810YesNo
18737945OPPORTUNISTIC WRITE-BACK DISCARD OF SINGLE-USE VECTOR REGISTER VALUESJune 2024July 2025Allow1310NoNo
18735514INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICESJune 2024July 2025Allow1400NoNo
18734396DATA PROCESSING SYSTEMS AND METHODS FOR CONTROLLING STORAGE OF INPUT DATA VALUES FOR USE BY AN EXECUTING UNITJune 2024January 2026Allow1910NoNo
18734464CONTROL REGISTER FOR STORING INSTRUCTION SIZE INFORMATIONJune 2024August 2025Allow1400NoNo
18733006PROFILING SYSTEM AND METHODSJune 2024February 2026Abandon2110NoNo
18732492PROCESSOR AND METHOD FOR ASSIGNING CONFIG ID FOR CORE INCLUDED IN THE SAMEJune 2024October 2025Allow1610NoNo
18731952DETERMINISTIC MEMORY FOR TENSOR STREAMING PROCESSORSJune 2024October 2025Allow1710YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2183.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
320
Examiner Affirmed
214
(66.9%)
Examiner Reversed
106
(33.1%)
Reversal Percentile
53.5%
Higher than average

What This Means

With a 33.1% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
875
Allowed After Appeal Filing
316
(36.1%)
Not Allowed After Appeal Filing
559
(63.9%)
Filing Benefit Percentile
71.5%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 36.1% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2183 - Prosecution Statistics Summary

Executive Summary

Art Unit 2183 is part of Group 2180 in Technology Center 2100. This art unit has examined 9,670 patent applications in our dataset, with an overall allowance rate of 76.5%. Applications typically reach final disposition in approximately 37 months.

Comparative Analysis

Art Unit 2183's allowance rate of 76.5% places it in the 50% percentile among all USPTO art units. This art unit has an above-average allowance rate compared to other art units.

Prosecution Patterns

Applications in Art Unit 2183 receive an average of 2.23 office actions before reaching final disposition (in the 75% percentile). The median prosecution time is 37 months (in the 24% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With more office actions than average, plan for multiple rounds of prosecution.
  • The median prosecution time is longer than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.