USPTO Examiner SPANN COURTNEY P - Art Unit 2183

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18586186Instruction Fetch Using a Sequential Prediction CircuitFebruary 2024June 2025Allow1610YesNo
18412504Branch Prediction Using loop Iteration CountJanuary 2024April 2025Allow1510YesNo
18544901REDUCED POWER CONSUMPTION PREDICTION USING PREDICTION TABLESDecember 2023March 2025Allow1500YesNo
18335944COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM USING NON-CONSECUTIVE DATA FORMATTINGJune 2023September 2024Allow1510YesNo
18208444Forming Constant Extensions in the Same Execute Packet in a VLIW ProcessorJune 2023November 2024Allow1820NoNo
18201293DYNAMIC PROCESSING MEMORY CORE ON A SINGLE MEMORY CHIPMay 2023March 2024Allow910NoNo
18163472Floating Point Norm InstructionFebruary 2023June 2025Allow2810YesNo
18157942COMPUTER-READABLE RECORDING MEDIUM STORING INSTRUCTION SEQUENCE GENERATION PROGRAM, INSTRUCTION SEQUENCE GENERATION METHOD, AND INFORMATION PROCESSING DEVICEJanuary 2023February 2024Abandon1300NoNo
18092712MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONSJanuary 2023September 2023Allow810NoNo
18148759INSTRUCTION RETIREMENT UNIT, INSTRUCTION EXECUTION UNIT, PROCESSING UNIT, COMPUTING DEVICE, AND INSTRUCTION PROCESSING METHOD FOR PERFORMING RETIREMENT PROCESSING ON INSTRUCTIONS BASED ON INSTRUCTION COMPLETION INFORMATIONDecember 2022February 2025Allow2610YesNo
18148654COMPUTING DEVICE AND METHOD FOR FUSING AND EXECUTING VECTOR INSTRUCTIONSDecember 2022September 2024Allow2010YesNo
18083249ACCELERATING FETCH TARGET QUEUE (FTQ) PROCESSING IN A PROCESSORDecember 2022November 2024Allow2320NoNo
18066115SYSTEM AND METHOD FOR SCHEDULING OPERATIONS IN A GRAPHICS PIPELINEDecember 2022June 2025Allow3010YesNo
18076592Instruction Scheduling Method, Instruction Scheduling Apparatus, Device And Storage Medium Based on Durations Consumed by Memory Access instructions During Instruction Running ScenariosDecember 2022April 2025Allow2910YesNo
18070781PROCESSOR, PROCESSING METHOD, AND RELATED DEVICE FOR ACCELERATING GRAPH CALCULATIONNovember 2022May 2024Allow2910NoNo
17993564Software-Defined Tensor Streaming Multiprocessor for Large-Scale Machine LearningNovember 2022December 2024Allow2500YesNo
17957604METHODS AND APPARATUS FOR PROVIDING MASK REGISTER OPTIMIZATION FOR VECTOR OPERATIONSSeptember 2022October 2024Allow2420YesNo
17940731ASYNCHRONOUS PIPELINE MERGING USING LONG VECTOR ARBITRATIONSeptember 2022June 2023Allow900YesNo
17879299PREDICTION UNIT THAT PROVIDES A FETCH BLOCK DESCRIPTOR EACH CLOCK CYCLEAugust 2022January 2024Allow1800YesNo
17855860PREDICTION CLASS DETERMINATIONJuly 2022June 2023Allow1200YesNo
17852821BACKWARD COMPATIBILITY BY RESTRICTION OF HARDWARE RESOURCESJune 2022November 2023Allow1620YesNo
17808916PROVIDING EXTENDED BRANCH TARGET BUFFER (BTB) ENTRIES FOR STORING TRUNK BRANCH METADATA AND LEAF BRANCH METADATAJune 2022October 2023Allow1610YesNo
17838713MICRO-OPERATION SUPPLY RATE VARIATIONJune 2022January 2024Allow1910NoNo
17806234Instruction Fetch Using a Return Prediction CircuitJune 2022November 2023Allow1810YesNo
17835352FOLDED INSTRUCTION FETCH PIPELINEJune 2022August 2023Allow1400NoNo
17833504REGISTER BASED SIMD LOOKUP TABLE OPERATIONSJune 2022January 2025Allow3130YesNo
17804949METHOD AND APPARATUS TO EXPEDITE SYSTEM SERVICES USING PROCESSING-IN-MEMORY (PIM)June 2022April 2024Allow2210YesNo
17828075COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM FOR CONVERTING FIRST SINGLE INSTRUCTION MULTIPLE DATA (SIMD) COMMAND USING FIRST MASK REGISTER INTO SECOND SIMD COMMAND USING SECOND MASK REGISTER, COMMAND CONVERSION METHOD FOR CONVERTING FIRST SIMD COMMAND USING FIRST MASK REGISTER INTO SECOND SIMD COMMAND USING SECOND MASK REGISTER, AND COMMAND CONVERSION APPARATUS FOR CONVERTING FIRST SIMD COMMAND USING FIRST MASK REGISTER INTO SECOND SIMD COMMAND USING SECOND MASK REGISTERMay 2022July 2023Allow1400NoNo
17827291REUSING FETCHED, FLUSHED INSTRUCTIONS AFTER AN INSTRUCTION PIPELINE FLUSH IN RESPONSE TO A HAZARD IN A PROCESSOR TO REDUCE INSTRUCTION RE-FETCHINGMay 2022March 2023Allow1000YesNo
17752060RE-ENABLING USE OF PREDICTION TABLE AFTER EXECUTION STATE SWITCHMay 2022August 2023Allow1510NoNo
17733728MICROPROCESSOR WITH SHARED READ AND WRITE BUSES AND INSTRUCTION ISSUANCE TO MULTIPLE REGISTER SETS IN ACCORDANCE WITH A TIME COUNTERApril 2022July 2024Allow2710YesNo
17755130DECOUPLED ACCESS-EXECUTE PROCESSINGApril 2022February 2024Allow2110YesNo
17770553METHOD AND SYSTEM FOR DISTRIBUTING INSTRUCTIONS IN RECONFIGURABLE PROCESSOR AND STORAGE MEDIUMApril 2022February 2024Allow2210NoNo
17721193PROCESSOR AUTHENTICATION METHODApril 2022August 2023Allow1610NoNo
17718258FETCH STAGE HANDLING OF INDIRECT JUMPS IN A PROCESSOR PIPELINEApril 2022June 2023Allow1410YesNo
17712966METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURALITY OF ASSOCIATED DATA ELEMENT VALUESApril 2022December 2024Abandon3240YesNo
17703773ISSUING INSTRUCTIONS BASED ON RESOURCE CONFLICT CONSTRAINTS IN MICROPROCESSORMarch 2022September 2023Allow1810NoNo
17702714STACK TRACES USING SHADOW STACKMarch 2022October 2023Allow1800YesNo
17689368METHOD FOR PATCHING CHIP AND CHIPMarch 2022January 2025Abandon3520YesNo
17640589METHOD, SYSTEM AND DEVICE FOR IMPROVED EFFICIENCY OF PIPELINE PROCESSING OF INSTRUCTIONS, AND COMPUTER STORAGE MEDIUMMarch 2022October 2023Allow2010YesNo
17590719Conditional Instructions PredictionFebruary 2022April 2024Allow2620YesNo
17578516PROCESSING DEVICE WITH A MICROBRANCH TARGET BUFFER FOR BRANCH PREDICTION USING LOOP ITERATION COUNTJanuary 2022September 2023Allow2010NoNo
17577577EFFICIENT INTER-THREAD COMMUNICATION BETWEEN HARDWARE PROCESSING THREADS OF A HARDWARE MULTITHREADED PROCESSOR BY SELECTIVE ALIASING OF REGISTER BLOCKSJanuary 2022April 2023Allow1510NoNo
17571130ARITHMETIC LOGIC UNIT LAYOUT FOR A PROCESSORJanuary 2022August 2023Allow1910NoNo
17565001MULTI-TABLE INSTRUCTION PREFETCH UNIT FOR MICROPROCESSORDecember 2021December 2023Allow2421YesNo
17558361DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BRANCH PREDICTION UNITDecember 2021June 2025Allow4210NoNo
17611670METHOD AND APPARATUS FOR SCHEDULING OUT-OF-ORDER EXECUTION QUEUE IN OUT-OF-ORDER PROCESSORNovember 2021April 2024Allow2920NoNo
17515538PROCESSOR AND OPERATING METHOD THEREOF FOR RENAMING DESTINATION LOGICAL REGISTER OF MOVE INSTRUCTIONOctober 2021April 2024Allow3040YesNo
17512082Memory Systems and Memory Control MethodsOctober 2021March 2025Abandon4140YesNo
17509897PROGRAM FLOW PREDICTION FOR LOOPSOctober 2021January 2023Allow1410NoNo
17451984COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM USING NON-CONSECUTIVE DATA FORMATTINGOctober 2021January 2023Allow1500YesNo
17493667APPARATUS AND METHOD FOR LOOP FLATTENING AND REDUCTION IN A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) PIPELINEOctober 2021March 2024Abandon2910NoNo
17492068CONTROL OF BRANCH PREDICTION FOR ZERO-OVERHEAD LOOPOctober 2021January 2023Allow1610NoNo
17384646ZERO OPERAND INSTRUCTION CONVERSION FOR ACCELERATING SPARSE COMPUTATIONS IN A CENTRAL PROCESSING UNIT PIPELINEJuly 2021March 2023Allow2010YesNo
17369021DYNAMIC PROCESSING MEMORYJuly 2021March 2024Allow3310YesNo
17366244THREAD PRIORITIES USING MISPREDICTION RATE AND SPECULATIVE DEPTHJuly 2021August 2023Allow2640YesNo
17364824CONSTRAINED CARRIES ON SPECULATIVE COUNTERSJune 2021January 2023Allow1810YesNo
17344070PROCESSOR AND PIPELINE PROCESSING METHOD FOR PROCESSING MULTIPLE THREADS INCLUDING WAIT INSTRUCTION PROCESSINGJune 2021January 2023Allow1920NoNo
17335089MICROPROCESSOR WITH SHARED FUNCTIONAL UNIT FOR EXECUTING MULTI-TYPE INSTRUCTIONSJune 2021August 2022Allow1410YesNo
17322598Exception HandlingMay 2021March 2022Allow1000YesNo
17318252PROCESSOR DEPENDENCY-AWARE INSTRUCTION EXECUTIONMay 2021August 2022Allow1520YesNo
17232386SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN EMBEDDED MACHINE LEARNING ACCELERATORSApril 2021January 2025Allow4550NoNo
17214804Reconfigurable Multi-Thread Processor for Simultaneous Operations on Split Instructions and OperandsMarch 2021June 2023Allow2611YesNo
17213453CONTROL FLOW MECHANISM FOR EXECUTION OF GRAPHICS PROCESSOR INSTRUCTIONS USING ACTIVE CHANNEL PACKINGMarch 2021August 2022Allow1720YesNo
17203205MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONSMarch 2021August 2022Allow1710YesNo
17184945APPARATUS AND METHOD TO SWITCH CONFIGURABLE LOGIC UNITSFebruary 2021July 2022Allow1710YesNo
17182328ARITHMETIC PROCESSING APPARATUS USING EITHER SIMPLE OR COMPLEX INSTRUCTION DECODERFebruary 2021May 2023Allow2620NoNo
17269216APPARATUS AND DATA PROCESSING METHOD FOR TRANSACTIONAL MEMORYFebruary 2021March 2022Allow1210YesNo
17163639STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPSFebruary 2021March 2023Allow2520NoNo
17138841Apparatus for Processor with Hardware Fence and Associated MethodsDecember 2020November 2022Abandon2270NoNo
17134046APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO CONVERT 16-BIT FLOATING-POINT FORMATSDecember 2020December 2024Allow4820YesNo
17128816CONTEXT-BASED LOOP BRANCH PREDICTIONDecember 2020June 2024Allow4210YesNo
17117520ENERGY EFFICIENT MICROPROCESSOR WITH INDEX SELECTED HARDWARE ARCHITECTUREDecember 2020July 2022Allow1911YesNo
17108083Performing Rounding Operations Responsive To An InstructionDecember 2020December 2022Abandon2520YesNo
17078296DUAL BRANCH FORMATOctober 2020May 2022Allow1820NoNo
17074991ASYNCHRONOUS PIPELINE MERGING USING LONG VECTOR ARBITRATIONOctober 2020June 2022Allow1900YesNo
17037605Verified Stack Trace Generation And Accelerated Stack-Based Analysis With Shadow StacksSeptember 2020February 2025Allow5221YesNo
17036442DATA PROCESSING APPARATUS AND METHOD FOR PROVIDING CANDIDATE PREDICTION ENTRIESSeptember 2020February 2023Allow2920NoNo
17033883Compressing Micro-Operations in Scheduler Entries in a ProcessorSeptember 2020April 2022Allow1920YesNo
17033770DELAYED CACHE WRITEBACK INSTRUCTIONS FOR IMPROVED DATA SHARING IN MANYCORE PROCESSORSSeptember 2020February 2025Allow5221YesNo
17041818SPECULATION WITH INDIRECT CONTROL FLOW INSTRUCTIONSSeptember 2020June 2022Allow2010YesNo
17024032STORING MULTIPLE INSTRUCTIONS IN A SINGLE REORDERING BUFFER ENTRYSeptember 2020June 2022Allow2120YesNo
16993452PROGRAM COUNTER (PC)-RELATIVE LOAD AND STORE ADDRESSING FOR FUSED INSTRUCTIONSAugust 2020May 2022Allow2120NoNo
16986650PERFORMING FLUSH RECOVERY USING PARALLEL WALKS OF SLICED REORDER BUFFERS (SROBs)August 2020May 2021Allow900YesNo
16943408HANDLING OVERSIZE STORE TO LOAD FORWARDING IN A PROCESSORJuly 2020January 2022Allow1810YesNo
16907988REUSING FETCHED, FLUSHED INSTRUCTIONS AFTER AN INSTRUCTION PIPELINE FLUSH IN RESPONSE TO A HAZARD IN A PROCESSOR TO REDUCE INSTRUCTION RE-FETCHINGJune 2020February 2022Allow2010YesNo
16888783PROCESSING DEVICE WITH A MICROBRANCH TARGET BUFFER FOR BRANCH PREDICTION USING LOOP ITERATION COUNTMay 2020October 2021Allow1620YesNo
16881205Data Bus With Multi-Input PipelineMay 2020September 2021Allow1600YesNo
15930907DETERMINING PREFETCH PATTERNS WITH DISCONTINUOUS STRIDESMay 2020January 2022Allow2020YesNo
16856462FETCH STAGE HANDLING OF INDIRECT JUMPS IN A PROCESSOR PIPELINEApril 2020August 2021Allow1610YesNo
16846686Method for Forming Constant Extensions in the Same Execute Packet in a VLIW ProcessorApril 2020February 2023Allow3440YesNo
16833012PROCESSOR AUTHENTICATION METHOD THROUGH SIGNED INSTRUCTIONMarch 2020January 2022Allow2220YesNo
16793422PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTUREFebruary 2020November 2024Allow5741YesYes
16778913Indirect Branch Predictor for Dynamic Indirect BranchesJanuary 2020September 2021Allow2001YesNo
16778939INDIRECT BRANCH PREDICTOR BASED ON REGISTER OPERANDSJanuary 2020January 2022Allow2300YesNo
16775621PREDICATED LOOPING ON MULTI-PROCESSORS FOR SINGLE PROGRAM MULTIPLE DATA (SPMD) PROGRAMSJanuary 2020October 2021Allow2010NoNo
16743484EXECUTING MUTUALLY EXCLUSIVE VECTOR INSTRUCTIONS ACCORDING TO A VECTOR PREDICATE INSTRUCTIONJanuary 2020December 2021Allow2311YesNo
16728815APPARATUS AND METHOD FOR NON-SPECULATIVE RESOURCE DEALLOCATIONDecember 2019January 2023Abandon3740NoNo
16622482Parallel Information Processing on Multi-Core Computing PlatformsDecember 2019August 2021Allow2020YesNo
16671109Determining branch targets for guest branch instructions executed in native address spaceOctober 2019November 2021Allow2430YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner SPANN, COURTNEY P.

Strategic Value of Filing an Appeal

Total Appeal Filings
4
Allowed After Appeal Filing
1
(25.0%)
Not Allowed After Appeal Filing
3
(75.0%)
Filing Benefit Percentile
31.1%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 25.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner SPANN, COURTNEY P - Prosecution Strategy Guide

Executive Summary

Examiner SPANN, COURTNEY P works in Art Unit 2183 and has examined 249 patent applications in our dataset. With an allowance rate of 80.3%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 31 months.

Allowance Patterns

Examiner SPANN, COURTNEY P's allowance rate of 80.3% places them in the 43% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.

Office Action Patterns

On average, applications examined by SPANN, COURTNEY P receive 2.41 office actions before reaching final disposition. This places the examiner in the 82% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by SPANN, COURTNEY P is 31 months. This places the examiner in the 35% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +27.0% benefit to allowance rate for applications examined by SPANN, COURTNEY P. This interview benefit is in the 78% percentile among all examiners. Recommendation: Interviews are highly effective with this examiner and should be strongly considered as a prosecution strategy. Per MPEP § 713.10, interviews are available at any time before the Notice of Allowance is mailed or jurisdiction transfers to the PTAB.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 25.9% of applications are subsequently allowed. This success rate is in the 32% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 19.6% of cases where such amendments are filed. This entry rate is in the 16% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 200.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 93% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 88% percentile among all examiners. Of these withdrawals, 100.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 26.1% are granted (fully or in part). This grant rate is in the 17% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 11% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 4.0% of allowed cases (in the 75% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.
  • Prioritize examiner interviews: Interviews are highly effective with this examiner. Request an interview after the first office action to clarify issues and potentially expedite allowance.
  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.