Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 19273567 | SYSTEMS AND METHODS FOR IMPLEMENTING DIRECTIONAL OPERAND BROADCAST AND MULTIPLY-ACCUMULATE EXECUTION USING A CONFIGURABLE PATCH MESH IN A MULTI-CORE PROCESSING ARRAY OF AN INTEGRATED CIRCUIT | July 2025 | November 2025 | Allow | 4 | 1 | 0 | Yes | No |
| 18896226 | PREDICTION UNIT WITH FIRST PREDICTOR THAT PROVIDES A HASHED FETCH ADDRESS OF A CURRENT FETCH BLOCK TO ITS OWN INPUT AND TO A SECOND PREDICTOR THAT USES IT TO PREDICT THE FETCH ADDRESS OF A NEXT FETCH BLOCK | September 2024 | September 2025 | Allow | 12 | 0 | 0 | No | No |
| 18896789 | IMPROVING COMPUTING EFFICIENCY OF A PROCESSOR BY OPTIMIZING A COMPUTATIONAL SIZE OF EACH COMPUTING CORE IN THE PROCESSOR | September 2024 | March 2025 | Allow | 6 | 1 | 0 | No | No |
| 18888365 | ENABLING HIGH-PERFORMANCE SCALABLE MATRIX EXTENSION (SME) INSTRUCTION ISSUE IN PROCESSOR DEVICES | September 2024 | August 2025 | Allow | 11 | 0 | 0 | Yes | No |
| 18817355 | SELECTING A CANDIDATE CONSUMER INSTRUCTION BASED ON AN OBSERVED INSTRUCTION HAVING A DEPENDENCY MARKED SOURCE OPERAND FROM PRODUCER DATA OF A PRODUCER INSTRUCTION | August 2024 | January 2026 | Allow | 17 | 1 | 0 | No | No |
| 18743637 | CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSOR | June 2024 | August 2025 | Allow | 14 | 1 | 0 | Yes | No |
| 18740430 | Processing of Synchronization Barrier Instructions | June 2024 | February 2026 | Allow | 20 | 2 | 0 | Yes | No |
| 18656902 | QUANTUM COMPUTER WITH A PRACTICAL-SCALE INSTRUCTION HIERARCHY | May 2024 | October 2025 | Allow | 17 | 1 | 0 | Yes | No |
| 18627035 | Trace Cache Access Prediction and Read Enable | April 2024 | November 2025 | Allow | 19 | 1 | 0 | Yes | No |
| 18609945 | APPARATUS AND METHOD FOR HIDING VECTOR LOAD LATENCY IN A TIME-BASED VECTOR COPROCESSOR | March 2024 | January 2026 | Allow | 22 | 2 | 0 | Yes | No |
| 18607703 | STREAM DATA UNIT WITH MULTIPLE HEAD REGISTERS | March 2024 | December 2024 | Allow | 9 | 0 | 0 | No | No |
| 18585283 | CONTROLLING SPECULATIVE ACTIONS BASED ON A HIT/MISS PREDICTOR | February 2024 | October 2025 | Allow | 19 | 1 | 0 | Yes | No |
| 18427411 | CONDITIONAL BRANCH INSTRUCTIONS | January 2024 | April 2025 | Allow | 14 | 0 | 0 | No | No |
| 18424989 | SYSTEM AND METHOD FOR DISTRIBUTED FORWARDING LOGIC FOR CYCLIC DATA-PIPELINE COHERENCY | January 2024 | March 2026 | Allow | 25 | 2 | 0 | Yes | No |
| 18426237 | LOOP EXECUTION IN A RECONFIGURABLE COMPUTE FABRIC USING FLOW CONTROLLERS FOR RESPECTIVE SYNCHRONOUS FLOWS | January 2024 | March 2025 | Allow | 13 | 1 | 0 | No | No |
| 18544453 | MULTI-CHANNEL PULSE MODULATION CONTROL SYSTEM, DEVICE, AND METHOD BASED ON RISC-V CUSTOM INSTRUCTIONS | December 2023 | August 2025 | Allow | 19 | 1 | 0 | No | No |
| 18532245 | ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY | December 2023 | September 2024 | Allow | 9 | 0 | 0 | Yes | No |
| 18524149 | Stateful Vector Group Permutation with Storage Reuse | November 2023 | May 2025 | Allow | 18 | 0 | 0 | No | No |
| 18494044 | MULTI-PROCESSOR DEVICE, DATA PROCESSING SYSTEM AND PERIPHERAL CONTROLLER SHARING METHOD | October 2023 | March 2026 | Allow | 28 | 2 | 0 | No | No |
| 18494152 | SYSTEM ON CHIP INCLUDING PERFORMANCE CONTROLLER GENERATING CONTROL INFORMATION BASED ON FUNCTIONS AND METHOD OF OPERATING THE SAME | October 2023 | February 2026 | Allow | 27 | 2 | 0 | Yes | No |
| 18377804 | Execution or Write Mask Generation for Data Selection in a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric | October 2023 | July 2024 | Allow | 9 | 0 | 0 | No | No |
| 18474728 | PROCESSOR ARCHITECTURE FOR OPTIMIZED PARALLELIZED SEARCH | September 2023 | January 2026 | Allow | 28 | 2 | 0 | Yes | No |
| 18474207 | INSTRUCTION CONVERSION DEVICE, INSTRUCTION CONVERSION METHOD, INSTRUCTION CONVERSION SYSTEM, AND PROCESSOR FOR CONVERTING EXTENDED INSTRUCTIONS BASED ON AN EMULATION FLAG | September 2023 | February 2026 | Allow | 28 | 3 | 1 | No | No |
| 18549853 | Parallel Decode Instruction Set Computer Architecture with Variable-Length Instructions | September 2023 | December 2025 | Abandon | 27 | 2 | 0 | Yes | No |
| 18364037 | LOW LATENCY INTER CORE COMMUNICATION | August 2023 | September 2025 | Abandon | 26 | 1 | 0 | No | No |
| 18357984 | Measuring Performance Associated with Processing Instructions Based on Counters for Different Events | July 2023 | March 2026 | Allow | 32 | 3 | 0 | Yes | No |
| 18261966 | CIRCUITRY AND METHOD FOR INSTRUCTION EXECUTION IN DEPENDENCE UPON TRIGGER CONDITIONS | July 2023 | November 2024 | Allow | 16 | 0 | 0 | Yes | No |
| 18352351 | Sharing Branch Predictor Resource for Instruction Cache and Trace Cache Predictions | July 2023 | May 2025 | Allow | 22 | 1 | 0 | No | No |
| 18216780 | PROCESSOR SELECTIVELY EXECUTING FIRST INSTRUCTION USING NON-PRE-PROCESSED DATA OR SECOND INSTRUCTION USING PRE-PROCESSED DATA | June 2023 | February 2026 | Allow | 31 | 4 | 0 | Yes | No |
| 18217368 | VECTOR PROCESSOR WITH VECTOR DATA BUFFER | June 2023 | February 2025 | Allow | 20 | 1 | 0 | No | No |
| 18343294 | CRACKING INSTRUCTIONS INTO A PLURALITY OF MICRO-OPERATIONS | June 2023 | November 2024 | Allow | 17 | 0 | 0 | No | No |
| 18332817 | DATA PROCESSING APPARATUS HAVING STREAMING ENGINE WITH READ AND READ/ADVANCE OPERAND CODING | June 2023 | March 2025 | Allow | 21 | 2 | 0 | No | No |
| 18206163 | Processing call and return information due to a branch prediction error | June 2023 | October 2024 | Allow | 16 | 0 | 0 | Yes | No |
| 18325519 | ONE-TIME PROGRAMMABLE (OTP) MEMORY CONTROLLER WITH A CONTROL CIRCUIT CONFIGURED TO ASSERT A PRE-LOAD START SIGNAL AND A PRE-LOAD END SIGNAL, RELATED PROCESSING SYSTEM, INTEGRATED CIRCUIT AND METHOD | May 2023 | March 2025 | Allow | 22 | 1 | 1 | No | No |
| 18202161 | VECTOR POPULATION COUNT DETERMINATION VIA COMPARISON ITERATIONS IN MEMORY | May 2023 | October 2024 | Allow | 17 | 2 | 0 | No | No |
| 18201755 | HARDWARE ACCELERATOR FOR EXECUTION OF INSTRUCTION SET OF RECURRENT NEURAL NETWORK, DATA PROCESSING METHOD, SYSTEM-LEVEL CHIP, AND MEDIUM THEREOF | May 2023 | June 2025 | Allow | 24 | 2 | 0 | Yes | No |
| 18312612 | DEVICE, SYSTEM AND METHOD FOR SCHEDULING JOB REQUESTS | May 2023 | June 2025 | Abandon | 25 | 1 | 0 | No | No |
| 18312079 | MULTICORE PROCESSOR WITH EACH CORE HAVING INDEPENDENT FLOATING POINT DATAPATH AND INTEGER DATAPATH | May 2023 | May 2025 | Allow | 25 | 3 | 0 | Yes | No |
| 18310919 | Managing Table Accesses for Tagged Geometric Length (TAGE) Load Value Prediction | May 2023 | August 2024 | Allow | 15 | 0 | 0 | Yes | No |
| 18194174 | MEMORY DEVICE FOR PROCESSING OPERATION, DATA PROCESSING SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY DEVICE | March 2023 | January 2024 | Allow | 10 | 0 | 0 | Yes | No |
| 18123604 | METHOD AND APPARATUS TO SORT A VECTOR FOR A BITONIC SORTING ALGORITHM | March 2023 | December 2025 | Allow | 33 | 6 | 0 | Yes | No |
| 18110162 | METHODS AND DEVICES FOR PROGRAMMING A STATE MACHINE ENGINE | February 2023 | March 2025 | Allow | 25 | 3 | 0 | Yes | No |
| 18149142 | METHODS AND APPARATUS FOR THREAD-BASED SCHEDULING IN MULTICORE NEURAL NETWORKS | January 2023 | May 2023 | Allow | 5 | 0 | 0 | Yes | No |
| 18149145 | METHODS AND APPARATUS FOR THREAD-BASED SCHEDULING IN MULTICORE NEURAL NETWORKS | January 2023 | June 2023 | Allow | 5 | 0 | 0 | Yes | No |
| 18091441 | DATA DEPENDENCY-AWARE SCHEDULING | December 2022 | March 2025 | Allow | 27 | 2 | 0 | Yes | No |
| 18087467 | VARIABLE-LENGTH INSTRUCTIONS FOR VECTOR OPERATIONS | December 2022 | October 2023 | Allow | 10 | 1 | 0 | No | No |
| 18067492 | METHOD AND STORAGE DEVICE FOR DIVIDING AND ALLOCATING TASKS TO DEDICATED PROCESSORS | December 2022 | August 2025 | Abandon | 32 | 3 | 0 | No | No |
| 18061164 | System and Method for Implementing Strong Load Ordering in a Processor Using a Circular Ordering Ring | December 2022 | July 2023 | Allow | 7 | 0 | 0 | Yes | No |
| 18072818 | JOB LIMIT ENFORCEMENT FOR IMPROVED MULTITENANT QUALITY OF SERVICE | December 2022 | March 2025 | Allow | 27 | 2 | 0 | Yes | Yes |
| 18057140 | Vector Index Registers in Vector Processors that each Store Multiple Addresses for Accessing Multiple Positions in Vectors | November 2022 | February 2026 | Allow | 39 | 6 | 0 | No | No |
| 18050673 | Initialisation of Worker Threads and Associated Operand Registers | October 2022 | November 2025 | Allow | 37 | 4 | 0 | No | No |
| 18045928 | Instruction Support for Matrix Multiplication That Maps Vector Register Length to a Shared Input Matrix Dimension | October 2022 | March 2025 | Abandon | 29 | 2 | 0 | Yes | No |
| 17959829 | REUSE OF BRANCH INFORMATION QUEUE ENTRIES FOR MULTIPLE INSTANCES OF PREDICTED CONTROL INSTRUCTIONS IN CAPTURED LOOPS IN A PROCESSOR | October 2022 | January 2024 | Allow | 16 | 0 | 0 | No | No |
| 17933040 | Processing of Synchronization Barrier Instructions | September 2022 | March 2024 | Allow | 18 | 0 | 1 | No | No |
| 17945843 | ACCELERATING DATA PROCESSING BY OFFLOADING THREAD COMPUTATION | September 2022 | July 2024 | Allow | 22 | 1 | 0 | No | No |
| 17931667 | DYNAMIC, LOW-LATENCY, DEPENDENCY-AWARE SCHEDULING ON SIMD-LIKE DEVICES FOR PROCESSING OF RECURRING AND NON-RECURRING EXECUTIONS OF TIME-SERIES DATA | September 2022 | March 2024 | Allow | 18 | 1 | 0 | No | No |
| 17942554 | ISSUING A SEQUENCE OF INSTRUCTIONS INCLUDING A CONDITION-DEPENDENT INSTRUCTION | September 2022 | January 2024 | Allow | 16 | 0 | 0 | Yes | No |
| 17941986 | System for Executing an Application on Heterogeneous Reconfigurable Processors | September 2022 | January 2024 | Allow | 16 | 0 | 0 | No | No |
| 17899714 | CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSOR | August 2022 | October 2023 | Allow | 14 | 0 | 0 | No | No |
| 17823279 | Processor Implementing Parallel In-order Execution During Load Misses | August 2022 | February 2024 | Allow | 17 | 1 | 0 | Yes | No |
| 17817866 | Stack Pointer Instruction Buffer For Zero-Cycle Loads | August 2022 | September 2023 | Allow | 13 | 0 | 0 | No | No |
| 17879525 | PREDICTION UNIT WITH FIRST PREDICTOR THAT PROVIDES A HASHED FETCH ADDRESS OF A CURRENT FETCH BLOCK TO ITS OWN INPUT AND TO A SECOND PREDICTOR THAT USES IT TO PREDICT THE FETCH ADDRESS OF A NEXT FETCH BLOCK | August 2022 | May 2024 | Allow | 22 | 0 | 0 | Yes | No |
| 17812214 | Method Of Debugging A Processor That Executes Vertices Of an Application, Each Vertex Being Assigned To a Programming Thread of the Processor | July 2022 | September 2023 | Allow | 14 | 1 | 0 | No | No |
| 17839856 | CONCURRENT MULTI-DATATYPE EXECUTION WITHIN A PROCESSING RESOURCE | June 2022 | June 2024 | Allow | 24 | 3 | 0 | Yes | No |
| 17733386 | Hardware Unit for Performing Matrix Multiplication with Clock Gating | April 2022 | May 2025 | Allow | 36 | 4 | 0 | Yes | No |
| 17659569 | Load-Store Unit Dual Tags and Replays | April 2022 | March 2024 | Allow | 23 | 2 | 0 | Yes | No |
| 17708344 | HYBRID PARALLELIZED TAGGED GEOMETRIC (TAGE) BRANCH PREDICTION | March 2022 | December 2024 | Allow | 32 | 3 | 0 | No | No |
| 17704122 | PROCESSOR USING TARGET INSTRUCTIONS TO MARK EXECUTION SEQUENCES WHICH ARE TARGETS OF BRANCH INSTRUCTIONS | March 2022 | July 2025 | Abandon | 39 | 4 | 0 | No | No |
| 17763490 | METHOD AND DEVICE TO SYNCHRONIZE MULTI-THREAD LOCKING | March 2022 | December 2024 | Abandon | 32 | 2 | 0 | No | No |
| 17701749 | IC INCLUDING LOGIC TILE, HAVING RECONFIGURABLE MAC PIPELINE, AND RECONFIGURABLE MEMORY | March 2022 | January 2023 | Allow | 10 | 0 | 0 | No | No |
| 17699217 | ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD OF REDUCING PIPELINE STALLS IN EXECUTING SINGLE INSTRUCTION/MULTIPLE DATA | March 2022 | December 2024 | Abandon | 33 | 4 | 0 | No | No |
| 17677413 | METHODS AND SYSTEMS FOR NESTED STREAM PREFETCHING FOR GENERAL PURPOSE CENTRAL PROCESSING UNITS | February 2022 | April 2023 | Allow | 13 | 0 | 0 | Yes | No |
| 17671356 | APPARATUS AND METHOD FOR VECTOR HORIZONTAL ADD OF SIGNED/UNSIGNED WORDS AND DOUBLEWORDS | February 2022 | June 2025 | Abandon | 40 | 4 | 0 | Yes | No |
| 17665958 | METHOD AND APPARATUS TO SORT A VECTOR FOR A BITONIC SORTING ALGORITHM | February 2022 | November 2022 | Allow | 9 | 0 | 0 | No | No |
| 17591963 | HARDWARE-IMPLEMENTED UNIVERSAL FLOATING-POINT INSTRUCTION SET ARCHITECTURE FOR COMPUTING DIRECTLY WITH HUMAN-READABLE DECIMAL CHARACTER SEQUENCE FLOATING-POINT REPRESENTATION OPERANDS | February 2022 | February 2023 | Allow | 13 | 1 | 1 | Yes | No |
| 17587719 | System and Method for Implementing Strong Load Ordering in a Processor Using a Circular Ordering Ring | January 2022 | November 2022 | Allow | 9 | 0 | 0 | Yes | No |
| 17648517 | DATA EXCHANGE PATHWAYS BETWEEN PAIRS OF PROCESSING UNITS IN COLUMNS IN A COMPUTER | January 2022 | September 2022 | Allow | 8 | 0 | 0 | No | No |
| 17570349 | METHOD AND DEVICE FOR PROVIDING A VECTOR STREAM INSTRUCTION SET ARCHITECTURE EXTENSION FOR A CPU | January 2022 | March 2025 | Abandon | 38 | 4 | 0 | No | No |
| 17566040 | STATEFUL MICROCODE BRANCHING | December 2021 | January 2024 | Allow | 24 | 2 | 0 | Yes | No |
| 17623324 | INSTRUCTIONS FOR OPERATING ACCELERATOR CIRCUIT | December 2021 | December 2025 | Abandon | 48 | 3 | 1 | No | No |
| 17557712 | STREAM DATA UNIT WITH MULTIPLE HEAD REGISTERS | December 2021 | November 2023 | Allow | 23 | 2 | 0 | No | Yes |
| 17558368 | DEVICE, METHOD AND SYSTEM TO DECODE AN INSTRUCTION BASED ON AN AVAILABILITY OF A PREDICTED DATA VALUE | December 2021 | December 2025 | Abandon | 48 | 2 | 0 | No | No |
| 17555408 | Fully pipelined hardware operator logic circuit for converting human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point format representations | December 2021 | February 2023 | Allow | 14 | 1 | 1 | No | No |
| 17553780 | Throttling Code Fetch For Speculative Code Paths | December 2021 | March 2025 | Allow | 39 | 1 | 0 | Yes | No |
| 17543096 | APPARATUS AND METHOD FOR BRANCH PREDICTION USING MACHINE LEARNING WITH NEW LEARNING MODELS | December 2021 | March 2025 | Allow | 39 | 4 | 0 | No | No |
| 17613661 | RISC-V BRANCH PREDICTION METHOD, DEVICE, ELECTRONIC DEVICE AND STORAGE MEDIUM | November 2021 | July 2024 | Abandon | 32 | 2 | 0 | No | No |
| 17523560 | METHOD AND APPARATUS FOR DYNAMICALLY SIMPLIFYING PROCESSOR INSTRUCTIONS | November 2021 | July 2023 | Allow | 20 | 1 | 0 | No | No |
| 17454171 | VECTOR REGISTERS IMPLEMENTED IN MEMORY | November 2021 | September 2022 | Allow | 11 | 0 | 0 | Yes | No |
| 17520281 | SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE FOR PARTIAL SUM ACCUMULATION IN MACHINE LEARNING ACCELERATORS | November 2021 | July 2024 | Allow | 32 | 3 | 0 | Yes | No |
| 17515712 | Managing Out-of-Order Retirement of Instructions Based on Received Instructions Indicating Start or Stop to Out-of-Order Retirement | November 2021 | July 2023 | Allow | 21 | 3 | 0 | Yes | No |
| 17451406 | INSTRUCTION SCHEDULING IN A PROCESSOR USING OPERATION SOURCE PARENT TRACKING | October 2021 | November 2023 | Allow | 25 | 2 | 0 | Yes | No |
| 17603896 | Reconfigurable System-On-Chip | October 2021 | March 2025 | Abandon | 41 | 4 | 0 | No | No |
| 17488359 | INFORMATION PROCESSING DEVICE, COMPILING METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM FOR ACCELERATING EXECUTION SPEED OF PROGRAMS | September 2021 | June 2023 | Allow | 21 | 3 | 0 | Yes | No |
| 17476749 | Tensor Partitioning and Partition Access Order | September 2021 | September 2022 | Allow | 12 | 0 | 0 | Yes | No |
| 17476690 | NEURON CACHE-BASED HARDWARE BRANCH PREDICTION | September 2021 | September 2023 | Allow | 24 | 2 | 0 | Yes | No |
| 17473001 | Execution or Write Mask Generation for Data Selection in a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric | September 2021 | May 2023 | Allow | 20 | 0 | 0 | No | No |
| 17471170 | METHOD OF CONVERTING EXTENDED INSTRUCTIONS BASED ON AN EMULATION FLAG AND RETIREMENT OF CORRESPONDING MICROINSTRUCTIONS, DEVICE AND SYSTEM USING THE SAME | September 2021 | July 2023 | Allow | 22 | 2 | 1 | Yes | No |
| 17470089 | VERIFYING COMPRESSED STREAM FUSED WITH COPY OR TRANSFORM OPERATIONS | September 2021 | November 2024 | Allow | 38 | 1 | 0 | No | No |
| 17469311 | SYNCHRONIZATION MECHANISMS FOR A MULTI-CORE PROCESSOR USING WAIT COMMANDS HAVING EITHER A BLOCKING OR A NON-BLOCKING STATE | September 2021 | September 2023 | Allow | 25 | 1 | 0 | Yes | No |
| 17458717 | INSTRUCTION HANDLING FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR | August 2021 | April 2023 | Allow | 20 | 3 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner DOMAN, SHAWN.
With a 22.2% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 37.5% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner DOMAN, SHAWN works in Art Unit 2183 and has examined 249 patent applications in our dataset. With an allowance rate of 70.3%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 35 months.
Examiner DOMAN, SHAWN's allowance rate of 70.3% places them in the 32% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.
On average, applications examined by DOMAN, SHAWN receive 2.88 office actions before reaching final disposition. This places the examiner in the 84% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by DOMAN, SHAWN is 35 months. This places the examiner in the 39% percentile for prosecution speed. Prosecution timelines are slightly slower than average with this examiner.
Conducting an examiner interview provides a +22.8% benefit to allowance rate for applications examined by DOMAN, SHAWN. This interview benefit is in the 68% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.
When applicants file an RCE with this examiner, 22.8% of applications are subsequently allowed. This success rate is in the 30% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.
This examiner enters after-final amendments leading to allowance in 9.0% of cases where such amendments are filed. This entry rate is in the 9% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.
When applicants request a pre-appeal conference (PAC) with this examiner, 60.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 50% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 55.0% of appeals filed. This is in the 27% percentile among all examiners. Of these withdrawals, 45.5% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 27.3% are granted (fully or in part). This grant rate is in the 15% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 12% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 1.1% of allowed cases (in the 62% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.