USPTO Examiner PETRANEK JACOB ANDREW - Art Unit 2183

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18956439DMA CONTROLLER AND LSU TO TRANSPOSE DATA ARRAYS STORED IN MAIN MEMORY FOR STORAGE IN PROCESSOR REGISTERSNovember 2024December 2025Allow1300NoNo
18919332MULTI-CARD PROCESSOR ACCESS FRAMEWORKOctober 2024February 2026Allow1610YesNo
18906697ADAPTIVE BUFFER SHARING IN MULTI-CORE RECONFIGURABLE STREAMING-BASED ARCHITECTURESOctober 2024September 2025Allow1100NoNo
18886319POWER EFFICIENT MULTI-BIT STORAGE SYSTEMSeptember 2024September 2025Allow1210NoNo
18828069VISION PROCESSING ACCELERATOR WITH LOW LATENCY IMAGE DISTORTION PROCESSING PIPELINESSeptember 2024February 2026Allow1710NoNo
18817548SHARING LOOP CACHE INSTANCES AMONG MULTIPLE THREADS IN PROCESSOR DEVICESAugust 2024August 2025Allow1100NoNo
18797799TRACKING NEAR-IDENTICAL MEMORY ADDRESSES AND REDUCING MEMORY ACCESS REQUESTSAugust 2024February 2026Allow1810NoNo
18777537CLIPPING OPERATIONS USING PARTIAL CLIP INSTRUCTIONSJuly 2024July 2025Allow1200NoNo
18775443Configuration Data Store in a Reconfigurable Data Processor Having Two Access ModesJuly 2024January 2026Allow1810NoNo
18768239MICROPROCESSOR VALIDATION USING RANDOM PREPACKAGED GENERATED TEST FUNCTIONS AND USER LEVEL SCHEDULERJuly 2024February 2026Allow2000NoNo
18741186COMPUTING CHIP AND INSTRUCTION PROCESSING METHOD TO ACCESS SOURCE OPERANDS IN PRIVATE REGISTERS USING A RELATIVE DISTANCE INDEXJune 2024January 2026Allow1910NoNo
18739272TWO-LEVEL ARBITRATION IN A COMPUTING SYSTEMJune 2024April 2025Allow1110NoNo
18737945OPPORTUNISTIC WRITE-BACK DISCARD OF SINGLE-USE VECTOR REGISTER VALUESJune 2024July 2025Allow1310NoNo
18734396DATA PROCESSING SYSTEMS AND METHODS FOR CONTROLLING STORAGE OF INPUT DATA VALUES FOR USE BY AN EXECUTING UNITJune 2024January 2026Allow1910NoNo
18670721PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE TO MEMORY DATA WIDER THAN A NATIVELY SUPPORTED DATA WIDTHMay 2024June 2025Allow1310NoNo
18661804STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONSMay 2024March 2026Allow2220NoNo
18659834DEVICES AND METHODS FOR MANAGING COMMAND FETCH AND COMMAND EXECUTIONMay 2024May 2025Allow1200NoNo
18654060MULTI-LEVEL PHT ENTRY SWAPS BASED ON FIRST LEVEL MISS AND SECOND LEVEL HITMay 2024October 2025Allow1710YesNo
18654249Hardware Guided Software Prefetch InsertionMay 2024May 2025Allow1300NoNo
18646992PROCESSOR PIPELINE FOR INTERLOCKED DATA TRANSFER OPERATIONS WITH VARIABLE LATENCYApril 2024October 2025Allow1810NoNo
18618648SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTUREMarch 2024October 2024Allow700NoNo
18614049STORING A DUPLICATED RETURN ADDRESS AND STACK POINTER IN REGISTERS TO PREVENT OVERFLOW ATTACKSMarch 2024October 2025Allow1920NoNo
18694318PROFILING CIRCUITRYMarch 2024January 2026Abandon2210NoNo
18604800PROCESSOR INSTRUCTION FOR DYNAMIC FLOATING POINT EXPONENT EXTRACTIONMarch 2024April 2025Allow1300NoNo
18602924NEURAL PROCESSING DEVICE, PROCESSING ELEMENT INCLUDED THEREIN AND METHOD FOR OPERATING VARIOUS FORMATS OF NEURAL PROCESSING DEVICEMarch 2024November 2024Allow810NoNo
18601640Atomic Operation Predictor to Predict Whether An Atomic Operation Will Complete SuccessfullyMarch 2024October 2024Allow700NoNo
18588724Hardware Support for Conversion between Integer and Floating-Point DataFebruary 2024May 2025Allow1400NoNo
18428319Macro-Op Fusion for Pipelined ArchitecturesJanuary 2024August 2025Allow1810YesNo
18400560WORKFLOW EXECUTION STATE VARIABLESDecember 2023April 2025Allow1520NoNo
18393825CONTROL OF INSTRUCTION ISSUE BASED ON ISSUE GROUPSDecember 2023January 2025Allow1300NoNo
18393657PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FUNCTION OPERATIONSDecember 2023July 2024Allow700NoNo
18532502APPARATUS AND METHODS RELATED TO MICROCODE INSTRUCTIONS INDICATING INSTRUCTION TYPESDecember 2023February 2025Allow1410NoNo
18527004HARDWARE ARCHITECTURE AND AN INSTRUCTION SET ARCHITECTURE FOR MACHINE-LEARNING COMPUTATIONSDecember 2023November 2025Abandon2310NoNo
18522822PROCESSOR FOR CONFIGURABLE PARALLEL COMPUTATIONSNovember 2023February 2025Allow1400NoNo
18502291SYSTEMS AND METHODS OF INSTRUCTIONS TO ACCELERATE MULTIPLICATION OF SPARSE MATRICES USING BITMASKS THAT IDENTIFY NON-ZERO ELEMENTSNovember 2023January 2025Allow1410NoNo
18382938HIERARCHICAL NETWORKS ON CHIP (NOC) FOR NEURAL NETWORK ACCELERATOROctober 2023January 2025Allow1410NoNo
183808683-LEVEL REAL-TIME CONCURRENT PRODUCTION OPERATION WORKGROUP SYSTEMS FOR FINE-GRAINED PROACTIVE CLOSED LOOP PROBLEM SOLVING OPERATIONSOctober 2023August 2025Allow2220NoNo
18484582Hardware Verification of Dynamically Generated CodeOctober 2023January 2025Allow1510NoNo
18553093OVERLAYS FOR SOFTWARE AND HARDWARE VERIFICATIONSeptember 2023March 2026Abandon3010NoNo
18473119EXECUTION UNIT SHARING BETWEEN PROCESSING CORES IN A CLUSTER OF A SYSTEM-ON-CHIP (SOC)September 2023December 2024Allow1500NoNo
18459241NEURAL PROCESSING DEVICE, PROCESSING ELEMENT INCLUDED THEREIN AND METHOD FOR OPERATING VARIOUS FORMATS OF NEURAL PROCESSING DEVICEAugust 2023February 2024Allow610NoNo
18454173A METHOD FOR FETCHING ENCRYPTED INSTRUCTIONS, DECODING AND EXECUTING DECRYPTED INSTRUCTIONS, AND COMPARING INSTRUCTION SIGNATURES TO ENSURE EXECUTION INTEGRITYAugust 2023June 2025Allow2110NoNo
18231024RECONFIGURABLE NEURAL NETWORK PROCESSING BASED ON SUBGRAPH RECOGNITIONAugust 2023March 2024Allow700NoNo
18364971MULTI-CARD PROCESSOR ACCESS FRAMEWORKAugust 2023September 2024Allow1300NoNo
18362596SYSTEM-ON-A-CHIP INCLUDING SOFT FLOAT FUNCTION CIRCUITJuly 2023September 2025Allow2510NoNo
18350197REDUCING DATA FORMAT CONVERSION OF AN ACCELERATORJuly 2023August 2024Allow1420YesNo
18326255HYBRID MODEL FOR TIME SERIES DATA PROCESSINGMay 2023November 2023Allow510NoNo
18322275PROCESSOR AND DATA OPERATION METHOD THEREOFMay 2023October 2025Abandon2920NoNo
18198387Transposing At-Speed in a Vector-Matrix AcceleratorMay 2023August 2024Allow1500NoNo
18197506HIERARCHICAL NETWORKS ON CHIP (NOC) FOR NEURAL NETWORK ACCELERATORMay 2023August 2023Allow300NoNo
18196418OVERLAY LAYER HARDWARE UNIT FOR NETWORK OF PROCESSOR CORESMay 2023October 2024Allow1710NoNo
18195776MULTIPLE SYSTEM-ON-CHIP ARRANGEMENT FOR VEHICLE COMPUTING SYSTEMSMay 2023November 2024Allow1810NoNo
18129808PROCESSOR CORES USING CONTENT OBJECT IDENTIFIERS FOR ROUTING AND COMPUTATIONMarch 2023December 2024Allow2100NoNo
18128852Apparatus and Method for Temperature-Constrained Frequency Control and SchedulingMarch 2023October 2024Allow1910NoNo
18025909METHOD OF INTERLEAVED PROCESSING ON A GENERAL-PURPOSE COMPUTING COREMarch 2023July 2025Allow2820YesYes
18175281INSTRUCTION OFFLOAD TO PROCESSOR CORES IN ATTACHED MEMORYFebruary 2023January 2024Allow1110NoNo
18172702METHOD AND SYSTEM TO PROCESS ASYNCHRONOUS AND DISTRIBUTED TRAINING TASKSFebruary 2023June 2024Allow1610NoNo
18107690Two-Level Arbitration in a Reconfigurable ProcessorFebruary 2023March 2024Allow1300NoNo
18105187Fast Argument Load in a Reconfigurable Data ProcessorFebruary 2023April 2024Allow1400NoNo
18105189Reconfigurable Data Processor with Fast Argument Load using a Runtime Program on a Host ProcessorFebruary 2023April 2024Allow1500NoNo
18017538MESSAGE-BASED PROCESSING WITH ASSIGNMENT OF NEURAL NETWORK LAYERS TO PROCESSOR CLUSTERSJanuary 2023July 2024Allow1810NoNo
18151009HARDWARE ACCELERATED ANOMALY DETECTION USING A MIN/MAX COLLECTOR IN A SYSTEM ON A CHIPJanuary 2023December 2023Allow1110NoNo
18086458Multi-Threaded Processor with Power Granularity and Thread GranularityDecember 2022January 2024Allow1300NoNo
18064520TWO-DIMENSIONAL PROCESSING ARRAY WITH A VERTICALLY STACKED MEMORY TILE ARRAYDecember 2022April 2025Allow2820NoNo
18076067Serverless Workflow Enablement and Execution PlatformDecember 2022August 2025Allow3210NoNo
18061539FAST MAPPER RESTORE FOR FLUSH IN PROCESSORDecember 2022January 2024Allow1300NoNo
18054401Fence Enforcement Techniques based on Stall CharacteristicsNovember 2022December 2023Allow1300NoNo
17983432COMPUTER-READABLE RECORDING MEDIUM STORING CONVERSION PROGRAM AND CONVERSION METHODNovember 2022October 2024Abandon2410NoNo
17973430CARRY CHAIN FOR SIMD OPERATIONSOctober 2022November 2023Allow1310NoNo
18046151DATA PROCESSING METHOD AND APPARATUS AND HETEROGENEOUS SYSTEMOctober 2022April 2025Allow3010NoNo
17961158DETECTING REAL-TIME CLOCK LOSSOctober 2022August 2023Allow1000YesNo
17958381APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR STRUCTURED-SPARSE TILE MATRIX FMAOctober 2022May 2025Allow3120NoNo
17932883INDIRECT BRANCH PREDICTOR STORING ENCRYPTED BRANCH INFORMATION FIELDSSeptember 2022March 2025Allow3030YesNo
17945492MICROPROCESSOR INCLUDING A DECODE UNIT THAT PERFORMS PRE-EXECUTION OF LOAD CONSTANT MICRO-OPERATIONSSeptember 2022April 2024Allow1910NoNo
17945045OVERLAY LAYER FOR NETWORK OF PROCESSOR CORESSeptember 2022November 2024Allow2610NoNo
17908577OPTIMIZING EXECUTION OF CODE ON RECONFIGURABLE HARDWARE USING LIKELY DATA VALUES BASED ON DATA SAMPLINGSeptember 2022August 2025Allow3530YesNo
17905225DECOUPLED ACCESS-EXECUTE PROCESSING AND PREFETCHING CONTROLAugust 2022September 2023Allow1300NoNo
17816449AUTOMATED ORCHESTRATION OF LARGE-SCALE FLOW LOG TRANSFORMATIONAugust 2022November 2023Allow1610NoNo
17867832SYNCHRONIZING COPROCESSORS USING SYNCHRONIZATION INSTRUCTIONS TO FORCE A SECOND COPROCESSOR TO WAIT UNTIL RECEIVING AN ACKNOWLEDGEMENT SIGNAL FROM A FIRST COPROCESSORJuly 2022November 2023Allow1610NoNo
17866345SYSTEMS AND METHODS FOR MULTI-BRANCH ROUTING FOR INTERCONNECTED CHIP NETWORKSJuly 2022December 2023Allow1710NoNo
17859377POWER EFFICIENT MULTI-BIT STORAGE SYSTEMJuly 2022July 2024Allow2420NoNo
17758129Accelerator Controller for Inserting Template Microcode Instructions into a Microcode Buffer to Accelerate Matrix OperationsJune 2022September 2023Allow1500NoNo
17835746System on Chip Including a Reconfigurable Connection Interface Between Master Devices and Slave DevicesJune 2022July 2024Allow2520NoNo
17827882PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE TO MEMORY DATA WIDER THAN A NATIVELY SUPPORTED DATA WIDTHMay 2022January 2024Allow2010NoNo
17780327IN-MEMORY COMPUTING PROCESSOR, PROCESSING SYSTEM, PROCESSING APPARATUS, DEPLOYMENT METHOD OF ALGORITHM MODELMay 2022January 2026Allow4430YesNo
17824775MATRIX PROCESSING INSTRUCTION WITH OPTIONAL UP/DOWN SAMPLING OF MATRIXMay 2022January 2024Abandon2010NoNo
17749268SINGLE INSTRUCTION MULTIPLE DATA EXECUTION WITH VARIABLE SIZE LOGICAL REGISTERSMay 2022October 2023Allow1710NoNo
17778091SYSTEM-ON-CHIP WITH A PLURALITY OF CHIPS COMMUNICATING WIRELESSLY USING HORIZONTAL INDUCTIVE COUPLINGMay 2022January 2025Allow3220NoNo
17744371STOCHASTIC HYPERDIMENSIONAL ARITHMETIC COMPUTINGMay 2022November 2024Allow3020NoNo
17741915ASIC POWER CONTROLMay 2022August 2025Abandon3930NoNo
17661696BRANCH PREDICTOR STORING ENCRYPTED INFORMATIONMay 2022January 2024Allow2120YesNo
17720322Acceleration System and Dynamic Configuration Method ThereofApril 2022July 2023Allow1510NoNo
17754739CO-SCHEDULED LOADS IN A DATA PROCESSING APPARATUSApril 2022February 2023Allow1000NoNo
17712126INSTRUCTION SET ARCHITECTURE SUPPORT FOR A LOAD GLOBAL POINTER INSTRUCTIONApril 2022November 2025Allow4410NoNo
17707176TECHNIQUES, DEVICES, AND INSTRUCTION SET ARCHITECTURE FOR EFFICIENT MODULAR DIVISION AND INVERSIONMarch 2022September 2023Allow1700YesNo
17656058GENERATING MASKS FROM DECODED INSTRUCTIONS TO APPLY TO FETCHED INSTRUCTIONS FOR UNMASKINGMarch 2022October 2024Allow3130NoNo
17696137HARDWARE AND SOFTWARE CO-DESIGNED SYSTEM FOR EFFICIENT DISTRIBUTED CONTROL OF EXECUTION ON A COMPUTE ACCELERATORMarch 2022January 2025Allow3410NoNo
17693240Static Identifications in Object-based Memory AccessMarch 2022September 2025Allow4240NoNo
17691615MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSORMarch 2022June 2025Abandon3930YesYes
17686003PROCESSOR CORES USING PACKET IDENTIFIERS FOR ROUTING AND COMPUTATIONMarch 2022October 2023Allow1910NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner PETRANEK, JACOB ANDREW.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
50
Examiner Affirmed
32
(64.0%)
Examiner Reversed
18
(36.0%)
Reversal Percentile
57.3%
Higher than average

What This Means

With a 36.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
115
Allowed After Appeal Filing
39
(33.9%)
Not Allowed After Appeal Filing
76
(66.1%)
Filing Benefit Percentile
56.1%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 33.9% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner PETRANEK, JACOB ANDREW - Prosecution Strategy Guide

Executive Summary

Examiner PETRANEK, JACOB ANDREW works in Art Unit 2183 and has examined 855 patent applications in our dataset. With an allowance rate of 77.4%, this examiner has a below-average tendency to allow applications. Applications typically reach final disposition in approximately 42 months.

Allowance Patterns

Examiner PETRANEK, JACOB ANDREW's allowance rate of 77.4% places them in the 44% percentile among all USPTO examiners. This examiner has a below-average tendency to allow applications.

Office Action Patterns

On average, applications examined by PETRANEK, JACOB ANDREW receive 2.66 office actions before reaching final disposition. This places the examiner in the 78% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by PETRANEK, JACOB ANDREW is 42 months. This places the examiner in the 18% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.

Interview Effectiveness

Conducting an examiner interview provides a +8.7% benefit to allowance rate for applications examined by PETRANEK, JACOB ANDREW. This interview benefit is in the 39% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 25.6% of applications are subsequently allowed. This success rate is in the 41% percentile among all examiners. Strategic Insight: RCEs show below-average effectiveness with this examiner. Carefully evaluate whether an RCE or continuation is the better strategy.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 20.2% of cases where such amendments are filed. This entry rate is in the 25% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 26.1% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 30% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 59.7% of appeals filed. This is in the 34% percentile among all examiners. Of these withdrawals, 21.6% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.

Petition Practice

When applicants file petitions regarding this examiner's actions, 51.1% are granted (fully or in part). This grant rate is in the 50% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 5.4% of allowed cases (in the 87% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 10.6% of allowed cases (in the 89% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Expect multiple rounds of prosecution: This examiner issues more office actions than average. Address potential issues proactively in your initial response and consider requesting an interview early in prosecution.
  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • Plan for extended prosecution: Applications take longer than average with this examiner. Factor this into your continuation strategy and client communications.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.