Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 18745756 | PREDICTION CIRCUITRY USING A PREDICTION TABLE PROVIDING A SKIP-FETCH-INSTRUCTION ENTRY | June 2024 | February 2026 | Allow | 20 | 1 | 0 | Yes | No |
| 18739070 | Load Instruction Fusion | June 2024 | October 2025 | Allow | 16 | 1 | 0 | Yes | No |
| 18649817 | SYSTEM TO ISSUE ONE OR MORE INSTRUCTIONS TO ONE OR MORE EXECUTION UNITS | April 2024 | January 2026 | Abandon | 21 | 1 | 0 | No | No |
| 18626629 | APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE | April 2024 | October 2025 | Allow | 19 | 1 | 0 | Yes | No |
| 18621071 | Apparatus and Method for Remote Atomic Floating Point Operations | March 2024 | March 2026 | Allow | 23 | 2 | 0 | Yes | No |
| 18593817 | ASYNCHRONOUS RELEASE OPERATIONS IN A MULTIPROCESSOR SYSTEM | March 2024 | March 2026 | Allow | 24 | 2 | 0 | Yes | No |
| 18532836 | Physical Register Sharing | December 2023 | August 2025 | Allow | 20 | 1 | 0 | Yes | No |
| 18525217 | POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE | November 2023 | December 2025 | Abandon | 25 | 1 | 0 | No | No |
| 18220169 | SINGLE INSTRUCTION MULTIPLE DISPATCHES FOR SHORT KERNELS IN A RECONFIGURABLE PARALLEL PROCESSOR | July 2023 | December 2025 | Allow | 30 | 2 | 0 | No | No |
| 18345007 | Supporting Multiple Vector Lengths with Configurable Vector Register File | June 2023 | March 2026 | Allow | 32 | 2 | 0 | Yes | No |
| 18216201 | INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT | June 2023 | January 2026 | Abandon | 31 | 2 | 0 | Yes | No |
| 18213598 | HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS | June 2023 | December 2025 | Allow | 30 | 3 | 0 | Yes | No |
| 18328688 | SYSTEMS AND METHODS FOR PROCESSING FORMATTED DATA IN COMPUTATIONAL STORAGE | June 2023 | October 2025 | Allow | 29 | 4 | 0 | Yes | No |
| 18312365 | MANAGING SPECULATIVE INSTRUCTION EXECUTION USING SPECULATIVE ID IN A GRAPHFLOW APPARATUS | May 2023 | August 2025 | Allow | 27 | 3 | 0 | Yes | No |
| 17867859 | METHOD OF ACCELERATING A VECTOR OPERATION USING ELEMENT -WISE COMPARISON, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM | July 2022 | December 2025 | Abandon | 41 | 5 | 0 | Yes | No |
| 17855816 | VECTOR PROCESSOR WITH VECTOR AND ELEMENT REDUCTION METHOD | July 2022 | November 2025 | Abandon | 41 | 4 | 0 | Yes | No |
| 17720657 | Cache Preload Operations Using Streaming Engine | April 2022 | November 2025 | Allow | 43 | 4 | 0 | Yes | Yes |
| 17676910 | INSERTING NULL VECTORS INTO A STREAM OF VECTORS | February 2022 | October 2025 | Allow | 43 | 2 | 0 | No | Yes |
| 17623329 | SYSTEM AND ARCHITECTURE OF PURE FUNCTIONAL NEURAL NETWORK ACCELERATOR | December 2021 | September 2025 | Allow | 45 | 4 | 0 | Yes | No |
| 17561029 | HARDWARE-SOFTWARE CO-DESIGNED MULTI-CAST FOR IN-MEMORY COMPUTING ARCHITECTURES | December 2021 | August 2025 | Allow | 44 | 1 | 1 | Yes | No |
| 17360949 | PROVIDING ATOMICITY FOR COMPLEX OPERATIONS USING NEAR-MEMORY COMPUTING | June 2021 | December 2025 | Abandon | 54 | 8 | 0 | Yes | No |
| 17244797 | PARTITIONABLE DIGITAL HARDWARE SYSTEM FOR IMPLEMENTING RECURRENT NEURAL NETWORKS | April 2021 | March 2026 | Allow | 59 | 3 | 0 | Yes | No |
| 17214291 | INSTRUCTION AND LOGIC FOR COMPUTATIONS OF SUM OF ABSOLUTE DIFFERENCES VALUES FOR MULTIPLE VECTOR LANES USING OFFSETS | March 2021 | March 2026 | Abandon | 59 | 4 | 0 | Yes | No |
| 17133618 | SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES | December 2020 | November 2025 | Abandon | 59 | 4 | 0 | Yes | No |
| 16786997 | FACILITATING PROVISIONING IN A MIXED ENVIRONMENT OF LOCALES | February 2020 | June 2020 | Allow | 4 | 0 | 0 | Yes | No |
| 16533588 | DISTRIBUTED PHYSICAL PROCESSING OF MATRIX SUM OPERATION | August 2019 | February 2021 | Allow | 18 | 1 | 0 | Yes | No |
| 16422602 | VECTOR STORE USING BIT-REVERSED ORDER | May 2019 | February 2026 | Abandon | 60 | 12 | 0 | Yes | No |
| 16408445 | MANAGING AN ISSUE QUEUE FOR FUSED INSTRUCTIONS AND PAIRED INSTRUCTIONS IN A MICROPROCESSOR | May 2019 | August 2020 | Allow | 15 | 1 | 0 | Yes | No |
| 16384819 | SYSTEMS AND METHODS FOR STREAM-DATAFLOW ACCELERATION WHEREIN A DELAY IS IMPLEMENTED SO AS TO EQUALIZE ARRIVAL TIMES OF DATA PACKETS AT A DESTINATION FUNCTIONAL UNIT | April 2019 | April 2021 | Allow | 24 | 4 | 0 | Yes | No |
| 15843982 | PRIORITIZED INSTRUCTIONS IN AN INSTRUCTION COMPLETION TABLE OF A SIMULTANEOUS MULTITHREADING PROCESSOR | December 2017 | March 2021 | Allow | 39 | 5 | 0 | Yes | No |
| 15816363 | PROVIDING A PREDICTED TARGET ADDRESS TO MULTIPLE LOCATIONS BASED ON DETECTING AN AFFILIATED RELATIONSHIP | November 2017 | August 2020 | Allow | 33 | 4 | 0 | Yes | No |
| 15795772 | MANAGING AN ISSUE QUEUE FOR FUSED INSTRUCTIONS AND PAIRED INSTRUCTIONS IN A MICROPROCESSOR | October 2017 | April 2019 | Allow | 18 | 3 | 0 | No | No |
| 15680759 | PROVIDING A PREDICTED TARGET ADDRESS TO MULTIPLE LOCATIONS BASED ON DETECTING AN AFFILIATED RELATIONSHIP | August 2017 | September 2020 | Allow | 36 | 4 | 0 | Yes | No |
| 15662454 | Processor for Correlation-Based Infinite Loop Detection | July 2017 | December 2019 | Allow | 28 | 2 | 0 | No | No |
| 15355747 | EFFICIENT SCHEDULING FOR HYPER-THREADED CPUS USING MEMORY MONITORING | November 2016 | February 2021 | Allow | 51 | 9 | 0 | Yes | No |
| 15270275 | SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT | September 2016 | November 2017 | Allow | 14 | 2 | 0 | Yes | No |
| 15267650 | SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT | September 2016 | May 2017 | Allow | 8 | 0 | 0 | Yes | No |
| 15091788 | SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT | April 2016 | August 2016 | Allow | 4 | 1 | 0 | Yes | No |
| 15011319 | FACILITATING PROVISIONING IN A MIXED ENVIRONMENT OF LOCALES | January 2016 | November 2019 | Allow | 45 | 3 | 0 | Yes | No |
| 14930848 | ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSOR | November 2015 | February 2021 | Allow | 60 | 5 | 0 | No | Yes |
| 14869641 | SYSTEM LEVEL TESTING OF MULTI-THREADING FUNCTIONALITY INCLUDING BUILDING INDEPENDENT INSTRUCTION STREAMS WHILE HONORING ARCHITECTURALLY IMPOSED COMMON FIELDS AND CONSTRAINTS | September 2015 | March 2020 | Allow | 53 | 6 | 0 | Yes | No |
| 14752891 | Systems, Methods, and Apparatuses for Last Branch Record Support Compatible with Binary Translation and Speculative Execution using an Architectural Bit Array and a Write Bit Array | June 2015 | February 2021 | Allow | 60 | 4 | 0 | No | No |
| 14618693 | SYSTEM LEVEL TESTING OF MULTI-THREADING FUNCTIONALITY INCLUDING BUILDING INDEPENDENT INSTRUCTION STREAMS WHILE HONORING ARCHITECTURALLY IMPOSED COMMON FIELDS AND CONSTRAINTS | February 2015 | March 2020 | Allow | 60 | 6 | 0 | Yes | No |
| 14301936 | PREDICTING INDIRECT BRANCHES USING PROBLEM BRANCH FILTERING AND PATTERN CACHE | June 2014 | May 2020 | Allow | 60 | 8 | 0 | Yes | No |
| 14288020 | FACILITATING PROVISIONING IN A MIXED ENVIRONMENT OF LOCALES | May 2014 | December 2015 | Allow | 19 | 3 | 0 | Yes | No |
| 14063409 | APPARATUS FOR GATING A LOAD OPERATION BASED ON ENTRIES OF A PREDICTION TABLE | October 2013 | August 2018 | Allow | 58 | 4 | 0 | Yes | No |
| 14042681 | INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION | September 2013 | March 2015 | Abandon | 17 | 3 | 0 | Yes | Yes |
| 13956347 | PROVIDING VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY | July 2013 | April 2016 | Allow | 32 | 1 | 0 | Yes | No |
| 13993321 | SYSTEM, APPARATUS AND METHOD FOR GENERATING A LOOP ALIGNMENT COUNT OR A LOOP ALIGNMENT MASK | June 2013 | May 2018 | Allow | 59 | 4 | 0 | Yes | No |
| 13844111 | METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA | March 2013 | June 2016 | Allow | 39 | 4 | 0 | Yes | No |
| 13799393 | Apparatus, System and Method For Configuration of Adaptive Integrated Circuitry Having Fixed, Application Specific Computational Elements | March 2013 | December 2016 | Allow | 45 | 2 | 0 | Yes | No |
| 13792039 | METHODS AND APPARATUS FOR CREATING AND EXECUTING A PACKET OF INSTRUCTIONS ORGANIZED ACCORDING TO DATA DEPENDENCIES BETWEEN ADJACENT INSTRUCTIONS AND UTILIZING NETWORKS BASED ON ADJACENCIES TO TRANSPORT DATA IN RESPONSE TO EXECUTION OF THE INSTRUCTIONS | March 2013 | May 2016 | Allow | 39 | 2 | 0 | Yes | No |
| 13749504 | SYSTEM AND METHOD FOR AUTOMATIC STORAGE LOAD BALANCING IN VIRTUAL SERVER ENVIRONMENTS | January 2013 | July 2013 | Allow | 6 | 1 | 0 | Yes | No |
| 13717480 | RUNNING SHIFT FOR DIVIDE INSTRUCTIONS FOR PROCESSING VECTORS | December 2012 | February 2016 | Allow | 38 | 2 | 0 | Yes | No |
| 13681520 | FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY BASED ON AN INDICATED SUBRANGE OF REGISTERS | November 2012 | March 2017 | Allow | 52 | 6 | 0 | Yes | No |
| 13680369 | MULTIPROCESSOR COMPUTING DEVICE | November 2012 | May 2016 | Abandon | 41 | 2 | 0 | Yes | Yes |
| 13670326 | Instructions With Floating Point Control Override | November 2012 | February 2014 | Allow | 15 | 2 | 0 | Yes | No |
| 13628781 | PROCESSING VECTORS USING WRAPPING NEGATION INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE | September 2012 | July 2013 | Allow | 10 | 1 | 0 | Yes | No |
| 13628857 | PROCESSING VECTORS USING WRAPPING BOOLEAN INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE | September 2012 | July 2013 | Allow | 10 | 1 | 0 | Yes | No |
| 13625164 | PROCESSING VECTORS USING WRAPPING MINIMA AND MAXIMA INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE | September 2012 | July 2013 | Allow | 10 | 1 | 0 | Yes | No |
| 13625097 | PROCESSING VECTORS USING WRAPPING SHIFT INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE | September 2012 | June 2013 | Allow | 9 | 1 | 0 | Yes | No |
| 13625131 | PROCESSING VECTORS USING WRAPPING MULTIPLY AND DIVIDE INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE | September 2012 | July 2013 | Allow | 9 | 1 | 0 | Yes | No |
| 13610299 | PROCESSING VECTORS USING WRAPPING ADD AND SUBTRACT INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE | September 2012 | June 2013 | Allow | 9 | 1 | 0 | Yes | No |
| 13610851 | ORGANIZATION OF VIRTUAL HETEROGENEOUS ENTITIES INTO SYSTEM RESOURCE GROUPS FOR DEFINING POLICY MANAGEMENT FRAMEWORK IN A MANAGED SYSTEMS ENVIRONMENT | September 2012 | April 2013 | Allow | 7 | 1 | 0 | Yes | No |
| 13604390 | OPTIMIZING PROCESSING IN A MULTI-CORE PROCESSOR COMPLEX BASED ON INSTRUCTION THROUGHPUT | September 2012 | October 2015 | Abandon | 37 | 4 | 0 | Yes | No |
| 13604496 | PROCESSING COMPLEX HAVING A SOFTWARE CONTROLLER FOR SWITCHING OPERATIONS BETWEEN SETS OF CORES | September 2012 | August 2016 | Abandon | 47 | 6 | 0 | Yes | No |
| 13557725 | PROCESSOR EMPLOYING SPLIT SCHEDULER IN WHICH NEAR, LOW LATENCY OPERATION DEPENDENCIES ARE TRACKED SEPARATE FROM OTHER OPERATION DEPENDENCIES | July 2012 | December 2012 | Allow | 4 | 1 | 0 | Yes | No |
| 13484709 | INSTRUCTION FOR COMPARING ACTIVE VECTOR ELEMENTS TO PRECEDING ACTIVE ELEMENTS TO DETERMINE VALUE DIFFERENCES | May 2012 | April 2013 | Allow | 10 | 1 | 0 | Yes | No |
| 13484666 | CONDITIONAL EXTRACT INSTRUCTION FOR PROCESSING VECTORS | May 2012 | December 2015 | Abandon | 42 | 4 | 0 | Yes | No |
| 13479436 | Resource Property Aggregation in a Multi-Provider System | May 2012 | June 2013 | Abandon | 13 | 2 | 0 | Yes | No |
| 13463454 | RUNNING MULTIPLY-ACCUMULATE INSTRUCTIONS FOR PROCESSING VECTORS | May 2012 | March 2013 | Allow | 10 | 1 | 0 | No | No |
| 13456371 | RUNNING UNARY OPERATION INSTRUCTIONS FOR PROCESSING VECTORS | April 2012 | February 2013 | Allow | 10 | 1 | 0 | Yes | No |
| 13431995 | Virtual Input-Output Connections for Machine Virtualization | March 2012 | July 2015 | Allow | 40 | 4 | 0 | Yes | No |
| 13431382 | COMPONENT LOCK TRACING BY ASSOCIATING COMPONENT TYPE PARAMETERS WITH PARTICULAR LOCK INSTANCES | March 2012 | December 2012 | Allow | 8 | 1 | 0 | Yes | No |
| 13330804 | INSTRUCTION SET ARCHITECTURE WITH EXTENDED REGISTER ADDRESSING USING ONE OR MORE PRIMARY OPCODE BITS | December 2011 | December 2016 | Allow | 60 | 3 | 0 | Yes | No |
| 13329575 | INSTRUCTION PREDICATION USING INSTRUCTION FILTERING | December 2011 | December 2016 | Allow | 60 | 3 | 0 | Yes | No |
| 13273320 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION | October 2011 | November 2012 | Allow | 13 | 1 | 0 | Yes | No |
| 13237646 | DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR | September 2011 | December 2012 | Allow | 15 | 1 | 0 | Yes | No |
| 13234785 | FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY BASED ON AN INDICATED SUBRANGE OF REGISTERS | September 2011 | March 2017 | Allow | 60 | 6 | 0 | Yes | No |
| 13219418 | VECTOR SHUFFLE INSTRUCTIONS OPERATING ON MULTIPLE LANES EACH HAVING A PLURALITY OF DATA ELEMENTS USING A SAME SET OF PER-LANE CONTROL BITS | August 2011 | August 2014 | Allow | 35 | 2 | 0 | Yes | No |
| 13211701 | Local Computation Logic Embedded in a Register File to Accelerate Programs | August 2011 | September 2019 | Allow | 60 | 8 | 0 | Yes | Yes |
| 13189140 | GETFIRST AND ASSIGNLAST INSTRUCTIONS FOR PROCESSING VECTORS | July 2011 | October 2015 | Abandon | 51 | 4 | 0 | Yes | No |
| 13188737 | RUNNING SUBTRACT AND RUNNING DIVIDE INSTRUCTIONS FOR PROCESSING VECTORS | July 2011 | January 2013 | Allow | 18 | 1 | 0 | Yes | No |
| 13115012 | ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM | May 2011 | September 2013 | Abandon | 28 | 2 | 0 | Yes | No |
| 12932542 | INTERCONNECTION NETWORK CONNECTING OPERATION-CONFIGURABLE NODES ACCORDING TO ONE OR MORE LEVELS OF ADJACENCY IN MULTIPLE DIMENSIONS OF COMMUNICATION IN A MULTI-PROCESSOR AND A NEURAL PROCESSOR | February 2011 | January 2013 | Allow | 22 | 1 | 0 | Yes | No |
| 13001852 | BRANCH PREDICTION USING A LEADING VALUE OF A CALL STACK STORING FUNCTION ARGUMENTS | December 2010 | December 2013 | Allow | 36 | 1 | 0 | Yes | No |
| 12971734 | CSTATE BOOST METHOD AND APPARATUS | December 2010 | December 2015 | Abandon | 60 | 3 | 0 | Yes | No |
| 12972361 | PARALLEL DATA PROCESSING SYSTEMS AND METHODS USING COOPERATIVE THREAD ARRAYS WITH UNIQUE THREAD IDENTIFIERS AS AN INPUT TO COMPUTE AN IDENTIFIER OF A LOCATION IN A SHARED MEMORY | December 2010 | September 2011 | Allow | 9 | 1 | 0 | Yes | No |
| 12970927 | SECURITY SANDBOX | December 2010 | April 2016 | Abandon | 60 | 4 | 0 | Yes | No |
| 12965673 | SIMD ARRAY OPERABLE TO PROCESS DIFFERENT RESPECTIVE PACKET PROTOCOLS SIMULTANEOUSLY WHILE EXECUTING A SINGLE COMMON INSTRUCTION STREAM | December 2010 | October 2011 | Allow | 11 | 1 | 0 | No | No |
| 12962207 | HARDWARD BREAKPOINTS IMPLEMENTED USING METADATA STORED AT MEMORY ADDRESS | December 2010 | January 2016 | Abandon | 60 | 4 | 0 | Yes | No |
| 12962113 | ODD AND EVEN START BIT VECTORS | December 2010 | July 2013 | Allow | 31 | 1 | 0 | Yes | No |
| 12961829 | PROGRAMMABLE ATOMIC MEMORY USING HARDWARE VALIDATION AGENT | December 2010 | April 2015 | Allow | 53 | 3 | 0 | Yes | No |
| 12958604 | METHOD AND APPARATUS FOR AN ENHANCED SPEED UNIFIED SCHEDULER UTILIZING OPTYPES FOR COMPACT LOGIC | December 2010 | February 2016 | Abandon | 60 | 4 | 0 | No | No |
| 12957699 | MULTIFLOW METHOD AND APPARATUS FOR OPERATION FUSION | December 2010 | March 2016 | Abandon | 60 | 4 | 0 | No | No |
| 12957754 | UNIFIED SCHEDULER FOR A PROCESSOR MULTI-PIPELINE EXECUTION UNIT AND METHODS | December 2010 | January 2016 | Abandon | 60 | 4 | 0 | No | No |
| 12927837 | INTERCONNECTION NETWORKS AND METHODS OF CONSTRUCTION THEREOF FOR EFFICIENTLY SHARING MEMORY AND PROCESSING IN A MULTIPROCESSOR WHEREIN CONNECTIONS ARE MADE ACCORDING TO ADJACENCY OF NODES IN A DIMENSION | November 2010 | December 2011 | Allow | 12 | 1 | 0 | Yes | No |
| 12907471 | SELECT FIRST AND SELECT LAST INSTRUCTIONS FOR PROCESSING VECTORS | October 2010 | September 2015 | Abandon | 59 | 4 | 0 | Yes | No |
| 12895034 | Measuring Runtime Coverage of Architectural Events of a Microprocessor | September 2010 | October 2013 | Allow | 36 | 1 | 0 | Yes | No |
| 12892128 | ARITHMETIC PROCESSING UNIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ARITHMETIC PROCESSING METHOD | September 2010 | September 2013 | Abandon | 36 | 1 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner VICARY, KEITH E.
With a 27.3% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 42.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.
Examiner VICARY, KEITH E works in Art Unit 2183 and has examined 396 patent applications in our dataset. With an allowance rate of 54.3%, this examiner allows applications at a lower rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 45 months.
Examiner VICARY, KEITH E's allowance rate of 54.3% places them in the 15% percentile among all USPTO examiners. This examiner is less likely to allow applications than most examiners at the USPTO.
On average, applications examined by VICARY, KEITH E receive 3.23 office actions before reaching final disposition. This places the examiner in the 91% percentile for office actions issued. This examiner issues more office actions than most examiners, which may indicate thorough examination or difficulty in reaching agreement with applicants.
The median time to disposition (half-life) for applications examined by VICARY, KEITH E is 45 months. This places the examiner in the 12% percentile for prosecution speed. Applications take longer to reach final disposition with this examiner compared to most others.
Conducting an examiner interview provides a +62.7% benefit to allowance rate for applications examined by VICARY, KEITH E. This interview benefit is in the 97% percentile among all examiners. Recommendation: Interviews are highly effective with this examiner and should be strongly considered as a prosecution strategy. Per MPEP § 713.10, interviews are available at any time before the Notice of Allowance is mailed or jurisdiction transfers to the PTAB.
When applicants file an RCE with this examiner, 16.2% of applications are subsequently allowed. This success rate is in the 13% percentile among all examiners. Strategic Insight: RCEs show lower effectiveness with this examiner compared to others. Consider whether a continuation application might be more strategic, especially if you need to add new matter or significantly broaden claims.
This examiner enters after-final amendments leading to allowance in 16.4% of cases where such amendments are filed. This entry rate is in the 18% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.
When applicants request a pre-appeal conference (PAC) with this examiner, 30.8% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 32% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 62.1% of appeals filed. This is in the 40% percentile among all examiners. Of these withdrawals, 25.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows below-average willingness to reconsider rejections during appeals. Be prepared to fully prosecute appeals if filed.
When applicants file petitions regarding this examiner's actions, 65.0% are granted (fully or in part). This grant rate is in the 70% percentile among all examiners. Strategic Note: Petitions show above-average success regarding this examiner's actions. Petitionable matters include restriction requirements (MPEP § 1002.02(c)(2)) and various procedural issues.
Examiner's Amendments: This examiner makes examiner's amendments in 14.6% of allowed cases (in the 96% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.
Quayle Actions: This examiner issues Ex Parte Quayle actions in 4.7% of allowed cases (in the 79% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.