USPTO Art Unit 2825 Prosecution Statistics

Art Unit Information

Art Unit: 2825
Group: 2820
Tech Center: 2800
Total Cases: 17,670
Last Active: January 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19019732METHOD FOR OPERATING A DYNAMIC MEMORY STRUCTURE HAVING A WRITE GATING DEVICE, A READ GATING DEVICE, AND A CAPACITORJanuary 2025June 2025Allow510YesNo
18911618DEVICE FOR RECEIVING SINGLE-ENDED SIGNAL OF LIGHT EMITTING DIODE CONTROL CARD AND FORWARDING AS DIFFERENTIAL SIGNALSOctober 2024December 2024Allow200NoNo
18823046ELECTRONIC DEVICE WITH BUFFERED OPERATION ENGINE AND METHOD FOR PERFORMING CALCULATION USING SAMESeptember 2024February 2025Allow510YesNo
18798572OPERATION METHOD FOR THREE-DIMENSIONAL FLASH MEMORY INCLUDING FERROELECTRIC-BASED DATA STORAGE PATTERN AND BACK GATEAugust 2024February 2026Allow1800NoNo
18788047SENSING CIRCUIT IN A VERTICAL MEMORY SYSTEMJuly 2024February 2026Allow1900NoNo
18729153Storage Array, and Interconnection Structure and Method for Operating ThereofJuly 2024February 2025Allow710NoNo
18762228CHARGE LOSS COMPENSATION DURING READ OPERATIONS IN A MEMORY DEVICEJuly 2024July 2025Allow1210NoNo
18751938FOUR-POLY-PITCH SRAM CELL WITH BACKSIDE METAL TRACKSJune 2024November 2025Allow1710NoNo
18749384SEMICONDUCTOR MEMORY DEVICE WITH EVEN & ODD COPLANAR WORDLINESJune 2024February 2026Allow2000NoNo
18749412MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGESJune 2024March 2026Allow2130NoNo
18748679SEEDING BIAS CONTROL FOR SUB-BLOCK GROUPS IN A MEMORY DEVICEJune 2024March 2026Allow2100NoNo
18749394SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUITJune 2024March 2026Allow2101NoNo
18747740APPARATUSES AND METHODS REFRESH RATE REGISTER ADJUSTMENT BASED ON REFRESH QUEUEJune 2024February 2026Allow2000NoNo
18746904MEMORY DEVICE WITH SEGMENTED SGD DRAINJune 2024February 2026Allow2000NoNo
18746226APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURESJune 2024February 2026Allow2001NoNo
18746238SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY STRING AND PLURALITY OF SELECT TRANSITSTORS AND METHOD INCLUDING A WRITE OPERATIONJune 2024January 2026Allow1900NoNo
18738908ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRAMMING DISTRIBUTION AND A PROGRAMMING DISTRIBUTION ADJACENT TO AN INITIAL PROGRAMMING DISTRIBUTIONJune 2024May 2025Allow1110NoNo
18737111SEMICONDUCTOR DEVICE WITH POWER-DOWN SIGNAL GENERATIONJune 2024May 2025Allow1110NoNo
18737192SEMICONDUCTOR DEVICE HAVING RANKS PERFORMING A TERMINATION OPERATIONJune 2024October 2025Allow1720NoNo
18715959Method for Implementing Content-Addressable Memory Based on Ambipolar FETJune 2024January 2026Allow2000NoNo
18679914SEMICONDUCTOR MEMORY DEVICE PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAMEMay 2024July 2025Allow1310NoNo
18678692IMPLEMENTATION OF HIERARCHICAL NAVIGABLE SMALL WORLD (HNSW) SEARCH TECHNIQUES USING NAND MEMORYMay 2024February 2026Abandon2010NoNo
18677014ONE-SIDED TRANSMITTER EQUALIZATIONMay 2024February 2026Allow2000NoNo
18675770BIT LINE LOGIC CIRCUIT AND METHODMay 2024October 2025Allow1710NoNo
18674089METHOD OF OPERATING NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE AND MEMORY CONTROLLER PERFORMING THE SAMEMay 2024February 2026Allow2100NoNo
18672775MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SAME USING BIT LINE BIAS VOLTAGE SCHEMEMay 2024March 2026Allow2110NoNo
18670401MEMORY CELL WITH DYNAMIC DISTURB REDUCTIONMay 2024February 2026Allow2110NoNo
18666886SEMICONDUCTOR MEMORY DEVICE TO HOLD 5-BITS OF DATA PER MEMORY CELLMay 2024February 2026Allow2110NoNo
18666874STORAGE DEVICE FOR SELECTIVELY PERFORMING HIGH-RELIABILITY PROGRAM OPERATION ACCORDING TO TEMPERATURE, AND OPERATION METHOD OF THE STORAGE DEVICEMay 2024February 2026Allow2110YesNo
18666823MEMORY DEVICE AND ERROR CORRECTION METHOD THEREOFMay 2024October 2025Allow1700NoNo
18666427COMPUTE-IN-MEMORY CIRCUIT BASED ON CHARGE REDISTRIBUTION, AND CONTROL METHOD THEREOFMay 2024November 2025Allow1810NoNo
18666063PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITYMay 2024September 2025Allow1620YesNo
18664387SEMICONDUCTOR INTEGRATED CIRCUITMay 2024December 2024Allow700NoNo
18662053Semiconductor Memory Device with Spin-Orbit Coupling ChannelMay 2024October 2025Allow1700NoNo
18662806NON-VOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) WITH MULTIPLE MAGNETIC TUNNEL JUNCTION CELLSMay 2024April 2025Allow1110NoNo
18661902MEMORY SELECTOR THRESHOLD VOLTAGE RECOVERYMay 2024April 2025Allow1110NoNo
18661126FOUR-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL WITH ENHANCED DATA RETENTIONMay 2024November 2025Allow1800NoNo
18656344APPARATUS FOR CONTROLLING NAND FLASH MEMORY DEVICE AND METHOD FOR CONTROLLING SAMEMay 2024March 2026Allow2210NoNo
18655941GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICESMay 2024November 2025Allow1800NoNo
18655700MEMORY DEVICE WEAR LEVELINGMay 2024October 2025Allow1820YesNo
18653788METHODS FOR EFFICIENT 3D SRAM-BASED COMPUTE-IN-MEMORYMay 2024August 2024Allow300NoNo
18651072VOLATILE MEMORY DEVICE WITH GLOBAL INPUT AND OUTPUT LINE ALLOCATED FOR METADATAApril 2024February 2026Allow2210YesNo
18649590STATIC RANDOM ACCESS MEMORY WITH ADAPTIVE PRECHARGE SIGNAL GENERATED IN RESPONSE TO TRACKING OPERATIONApril 2024May 2025Allow1210NoNo
18647554MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEMApril 2024December 2025Allow2010YesNo
18643832COMPUTE IN MEMORY (CIM) MEMORY ARRAY FOR STORING WEIGHTSApril 2024February 2026Allow2210NoNo
18640966COMPARISON OPERATIONS IN MEMORYApril 2024June 2025Allow1410NoNo
18639330MEMORY DEVICE USING A PLURALITY OF SUPPLY VOLTAGES AND OPERATING METHOD THEREOFApril 2024May 2025Allow1320YesNo
18637913KNOWN-FAILURE ERROR HANDLING IN A MEMORY SUB-SYSTEMApril 2024March 2026Allow2310YesNo
18636277GATE-CONTROLLED THYRISTOR AND CAM ARRAYApril 2024February 2026Allow2210NoNo
18636569MEMORY DEVICE AND PROGRAM OPERATION THEREOFApril 2024June 2025Allow1410YesNo
18635365SEMICONDUCTOR DEVICE STRUCTURE HAVING FUSE ELEMENTSApril 2024February 2025Allow1020NoNo
18635208APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATIONApril 2024October 2025Allow1800NoNo
18635049MEMORY CHIP AND OPERATING METHOD THEREOFApril 2024April 2025Allow1211NoNo
18633847GAIN CELL MEMORY DEVICE USING ENHANCED SENSING SCHEME AND METHODS FOR OPERATING THE SAMEApril 2024February 2026Allow2210YesNo
18632358TRANSISTORLESS MEMORY CELLApril 2024March 2025Allow1111NoNo
18629906WRITE LEVELING IN DDR MEMORY DEVICE AND OPERATING METHOD THEREOFApril 2024March 2026Allow2310NoNo
18626748MEMORY DEVICE PREVENTING GENERATION OF UNDER-PROGRAMMED MEMORY CELL, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD THEREOFApril 2024August 2025Allow1620YesNo
18625310SRAM CELL STRUCTURE WITH 3 P-CHANNEL TRANSISTORS AND 3 N-CHANNEL TRANSISTORS AND METHOD OF OPERATING THE SRAM CELLApril 2024March 2026Allow2310NoNo
18624312MEMORY CARD WITH MULTIPLE MODES, AND HOST DEVICE CORRESPONDING TO THE MEMORY CARDApril 2024July 2025Allow1510NoNo
18624551MEMORY CIRCUIT WITH LEVEL SHIFTER CIRCUIT AND METHOD OF OPERATING SAMEApril 2024January 2026Allow2210NoNo
18623116STORAGE DEVICE FOR GENERATING IDENTITY CODE AND IDENTITY CODE GENERATING METHODApril 2024February 2025Allow1010YesNo
18617898TECHNIQUES FOR FASTER RAMP-UP TIMES FOR UNSELECTED WORD LINES IN NON-VOLATILE MEMORYMarch 2024January 2026Allow2210YesNo
18615521RRAM CIRCUITMarch 2024January 2025Allow1010NoNo
18614244TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENTMarch 2024February 2025Allow1110NoNo
18614460BIT CELL BASED WRITE SELF-TIME DELAY PATHMarch 2024March 2026Allow2420NoNo
18614153MEMORIES, OPERATION METHODS THEREOF AND MEMORY SYSTEMSMarch 2024September 2025Allow1700NoNo
18612239NONVOLATILE SEMICONDUCTOR MEMORY DEVICEMarch 2024February 2026Allow2300YesNo
18610896SEMICONDUCTOR DEVICES INCLUDING A CLOCK DIVIDER RELATED TO THE GENERATION OF A COMMANDMarch 2024January 2026Allow2210NoNo
18608147MEMORY DEVICE AND METHOD FOR COMPUTING-IN-MEMORY (CIM)March 2024September 2025Allow1800NoNo
18606333Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory ArraysMarch 2024October 2024Allow710NoNo
18603118HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISIONMarch 2024October 2024Allow710NoNo
18603154DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICEMarch 2024December 2025Allow2110NoNo
18601706MEMORY DEVICE HAVING A NEGATIVE VOLTAGE CIRCUITMarch 2024March 2025Allow1220NoNo
18598888GENERATING ACCESS LINE VOLTAGESMarch 2024February 2026Allow2310NoNo
18596651SEMICONDUCTOR DEVICE AND SIMULTANEOUS BLOCK OPERATIONS METHOD USING MULTIPLE SOURCE LINESMarch 2024March 2026Allow2410YesNo
18594877SEMICONDUCTOR STORAGE DEVICE COMPRISING A REPLICA BIT LINE CIRCUITMarch 2024December 2025Allow2110NoNo
18593980SEMICONDUCTOR MEMORY DEVICEMarch 2024October 2025Allow1900NoNo
18594104MEMORY SYSTEM INCLUDING CURRENT COPY CIRCUIT CONFIGURED TO COPY CURRENTMarch 2024December 2025Allow2110NoNo
18591563SEMICONDUCTOR FLASH MEMORY DEVICE WITH VOLTAGE CONTROL ON COMPLETION OF A PROGRAM OPERATION AND SUBSEQUENT TO COMPLETION OF THE PROGRAM OPERATIONFebruary 2024June 2025Allow1620NoNo
18590490STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUITFebruary 2024November 2025Allow2120YesNo
18587961SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACKED SEMICONDUCTOR DEVICE USING THE SAMEFebruary 2024November 2024Allow900NoNo
18587207APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICESFebruary 2024July 2025Allow1720NoNo
18586174MEMORY DEVICE AND METHOD FOR OPERATING THE SAME INCLUDING SETTING A RECOVERY VOLTAGEFebruary 2024December 2024Allow1010NoNo
18584023DYNAMIC ADJUSTMENT OF SIGNAL DELAY WITH MEMORY ARRAY VOLTAGEFebruary 2024December 2025Allow2210YesNo
18584183RESISTANCE CHANGE ELEMENT, STORAGE DEVICE, AND NEURAL NETWORK APPARATUSFebruary 2024December 2025Allow2210NoNo
18582654CONTROLLER FOR MANAGING BAD BLOCK, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE STORAGE DEVICEFebruary 2024February 2026Allow2310NoNo
18582185PARALLEL ACCESS IN A MEMORY ARRAYFebruary 2024January 2025Allow1110NoNo
18581398SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING COMPLEMENTARY DELAY CIRCUITS FOR MAXIMIZING OPERATION EFFICIENCY WHILE MINIMIZING AREA OCCUPIED BY DELAY CIRCUITSFebruary 2024December 2025Allow2210NoNo
18582433SEMICONDUCTOR STORAGE DEVICEFebruary 2024January 2026Allow2310NoNo
18438709Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming AssembliesFebruary 2024April 2025Allow1420NoNo
18438635MEMORY SYSTEM APPLYING READ VOLTAGE FOR READING DATA WITH SMALL NUMBER OF FAIL BITSFebruary 2024March 2026Allow2510NoNo
18439464DELAY ADJUSTER BASED CLOCK QUALIFIER TIMING ENHANCEMENT FOR MEMORY INTERFACEFebruary 2024January 2026Allow2310NoNo
18436330CIRCUITRY TO DETECT CYCLE COUNT FOR INCREASED THROUGHPUT READS AND WRITE OPERATIONS FOR MEMORYFebruary 2024January 2026Allow2300NoNo
18435134POWER MANAGEMENT INTEGRATED CIRCUIT WITH CHARGE PUMPFebruary 2024May 2025Allow1520NoNo
18430892MEMORY DEVICE INCLUDING CHARGE PUMP FOR GENERATING VOLTAGE AND OPERATING METHOD THEREOFFebruary 2024March 2026Allow2510YesNo
18428045RECEIVER INCLUDING A PULSE AMPLITUDE MODULATION DECODER, AND A MEMORY DEVICE INCLUDING THE SAMEJanuary 2024October 2025Allow2100NoNo
18425450MEMORY DEVICE PERFORMING LEAKAGE DETECTION OPERATIONJanuary 2024March 2026Allow2510NoNo
18424413LATCH CIRCUIT FORMED BY MODIFIED MEMORY CELLSJanuary 2024February 2025Allow1210NoNo
18422092SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL MEMORY CELLSJanuary 2024October 2025Allow2130NoNo
18417325MEMORY DEVICE WITH WORD LINE PULSE RECOVERYJanuary 2024March 2025Allow1430NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2825.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
71
Examiner Affirmed
35
(49.3%)
Examiner Reversed
36
(50.7%)
Reversal Percentile
94.7%
Higher than average

What This Means

With a 50.7% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
534
Allowed After Appeal Filing
239
(44.8%)
Not Allowed After Appeal Filing
295
(55.2%)
Filing Benefit Percentile
93.7%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 44.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2825 - Prosecution Statistics Summary

Executive Summary

Art Unit 2825 is part of Group 2820 in Technology Center 2800. This art unit has examined 17,670 patent applications in our dataset, with an overall allowance rate of 89.2%. Applications typically reach final disposition in approximately 25 months.

Comparative Analysis

Art Unit 2825's allowance rate of 89.2% places it in the 89% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2825 receive an average of 1.34 office actions before reaching final disposition (in the 13% percentile). The median prosecution time is 25 months (in the 79% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.