USPTO Examiner TRAN ANTHAN - Art Unit 2825

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18635049MEMORY CHIP AND OPERATING METHOD THEREOFApril 2024April 2025Allow1211NoNo
18632358TRANSISTORLESS MEMORY CELLApril 2024March 2025Allow1111NoNo
18587961SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACKED SEMICONDUCTOR DEVICE USING THE SAMEFebruary 2024November 2024Allow900NoNo
18528395MULTI-MODE COMPATIBLE ZQ CALIBRATION CIRCUIT IN MEMORY DEVICEDecember 2023April 2025Allow1720YesNo
18503022SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODENovember 2023March 2025Allow1610NoNo
18372144Compute-In-Memory architecture using look-up tablesSeptember 2023May 2025Allow2000NoNo
18474194MEMORY DEVICE AND OPERATION METHOD THEREOFSeptember 2023May 2025Allow2000NoNo
18238674SEMICONDUCTOR ELEMENT MEMORY DEVICEAugust 2023April 2025Allow1900NoNo
18451162SEMICONDUCTOR MEMORY DEVICEAugust 2023July 2024Allow1110NoNo
18358049RECEIVER CIRCUIT, MEMORY DEVICE AND OPERATION METHOD USING THE SAMEJuly 2023August 2024Allow1310NoNo
18354300MEMORY SYSTEMJuly 2023December 2024Allow1720NoNo
18337214COMPENSATING NON-IDEALITY OF A NEUROMORPHIC MEMORY DEVICEJune 2023February 2025Allow2000NoNo
18335385APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICEJune 2023May 2025Allow2301NoNo
18322610MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING TARGET REFRESH OPERATION, AND OPERATION METHOD THEREOFMay 2023April 2025Allow2301NoNo
18318970Decoder Circuits Using Shared Transistors for Low-Power, High-Speed, and Small AreaMay 2023April 2025Allow2301NoNo
18311800MEMORY DEVICE AND DATA APPROXIMATION SEARCH METHOD THEREOFMay 2023December 2024Allow1900NoNo
18142112CORRECTIVE READS WITH IMPROVED RECOVERY FROM DATA RETENTION LOSSMay 2023April 2025Allow2410YesNo
18298985SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR MEMORY APPARATUSApril 2023June 2024Allow1411NoNo
18021177METHOD FOR OPERATING DYNAMIC MEMORYFebruary 2023June 2024Allow1600NoNo
18162811LAYOUT OF DRIVING CIRCUIT, SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MEMORYFebruary 2023November 2024Allow2100NoNo
18162391MAGNETIC PROCESSING UNITJanuary 2023March 2025Allow2510NoNo
18095306MEMORY DEVICEJanuary 2023February 2025Allow2610NoNo
18093817SIGNAL SYNCHRONIZATION ADJUSTMENT METHOD AND SIGNAL SYNCHRONIZATION ADJUSTMENT CIRCUITJanuary 2023August 2024Allow2000NoNo
18148378METHOD FOR STORING INFORMATION IN A CODED MANNER IN NON-VOLATILE MEMORY CELLS, DECODING METHOD AND NON-VOLATILE MEMORYDecember 2022June 2025Allow2910YesNo
18091020INTERFACE PROTOCOLS BETWEEN MEMORY CONTROLLER AND NAND FLASH MEMORY FOR CACHE PROGRAMMINGDecember 2022August 2024Allow2000NoNo
18090303MEMORY DEVICE AND OPERATING METHOD THEREOFDecember 2022December 2024Allow2420NoNo
18078732MERGED BUFFER AND MEMORY DEVICE INCLUDING THE MERGED BUFFERDecember 2022June 2023Allow600NoNo
17980382Drift Aware Read OperationsNovember 2022August 2024Allow2130YesNo
18046995INPUT/OUTPUT PAD SUITABLE FOR MEMORY AND METHOD OF CONTROLLING SAMEOctober 2022October 2024Allow2410NoNo
17953297METHOD FOR OBTAINING CIRCUIT NOISE PARAMETERS AND ELECTRONIC DEVICESeptember 2022July 2024Allow2210NoNo
17933933SRAM ARCHITECTURESeptember 2022August 2023Allow1110NoNo
17948858OPERATING METHOD OF STORAGE DEVICE, OPERATING METHOD OF HOST, AND STORAGE SYSTEM INCLUDING THE STORAGE DEVICE AND THE HOSTSeptember 2022February 2025Allow2911YesNo
17942874SEMICONDUCTOR SYSTEM AND METHOD OF OPERATING THE SAMESeptember 2022April 2023Allow701NoNo
17929981APPARATUSES AND METHODS FOR GENERATING REFRESH ADDRESSESSeptember 2022July 2024Allow2300NoNo
17895959CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAYAugust 2022December 2024Allow2720NoNo
17895412HYBRID SMART VERIFY FOR QLC/TLC DIEAugust 2022September 2024Allow2501NoNo
17894248MEMORY FOR PROGRAMMING DATA STATES OF MEMORY CELLSAugust 2022January 2025Allow2811NoNo
17801467METHODS AND SYSTEMS FOR IMPROVING ECC OPERATION OF MEMORIESAugust 2022November 2024Allow2711NoNo
17890047PEAK CURRENT REDUCTION USING DYNAMIC CLOCKING DURING CHARGE PUMP RECOVERY PERIODAugust 2022May 2023Allow910NoNo
17818110SENSE AMPLIFICATION CIRCUIT AND METHOD OF READING OUT DATAAugust 2022December 2022Allow500NoNo
17871811NEURAL NETWORK COMPUTATION METHOD USING ADAPTIVE DATA REPRESENTATIONJuly 2022December 2022Allow500NoNo
17871681APPARATUS WITH VOLTAGE PROTECTION MECHANISMJuly 2022June 2023Allow1111NoNo
17866448Systems, Devices, and Methods of Cache MemoryJuly 2022January 2025Allow3021YesNo
17812485SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SENSE CIRCIUTJuly 2022April 2024Allow2100NoNo
17860419Decoupled Execution Of Workload For Crossbar ArraysJuly 2022March 2025Abandon3220NoNo
17853517Synchronous Input Buffer Control Using a Write ShifterJune 2022November 2024Allow2811NoNo
17853315READ AND PROGRAMMING DECODING SYSTEM FOR ANALOG NEURAL MEMORYJune 2022October 2024Allow2840NoNo
17845640INPUT BUFFER BIAS CURRENT CONTROLJune 2022October 2024Allow2811NoNo
17843237SELECTIVE READING OF MEMORY WITH IMPROVED ACCURACYJune 2022June 2023Allow1210NoNo
17841517APPARATUSES AND METHODS FOR CONTROLLING SENSE AMPLIFIER OPERATIONJune 2022September 2024Allow2711NoNo
17841287MEMORY DEVICEJune 2022September 2024Allow2711NoNo
17838596AMPLIFICATION CONTROL METHOD AND CIRCUIT, SENSITIVE AMPLIFIER AND SEMICONDUCTOR MEMORYJune 2022March 2024Allow2100NoNo
17806346SEMICONDUCTOR MEMORY DEVICEJune 2022December 2023Allow1900NoNo
17805991READOUT CIRCUIT LAYOUTJune 2022December 2023Abandon1820NoNo
17834659MULTIPLEXED SIGNAL DEVELOPMENT IN A MEMORY DEVICEJune 2022March 2023Allow900NoNo
17832479METHODS AND SYSTEMS FOR SELECTIVELY ENABLING/DISABLING MEMORY DIESJune 2022February 2024Allow2000NoNo
17829054VOLTAGE MANAGEMENT FOR IMPROVED tRP TIMING FOR FeRAM DEVICESMay 2022January 2025Allow3230NoNo
17827852MEMORY DEVICE AND METHOD OF READING DATAMay 2022December 2023Allow1800NoNo
17752489SYSTEMS AND METHODS FOR IDENTIFYING COUNTERFEIT MEMORYMay 2022June 2024Abandon2410NoNo
17664035STORAGE DEVICEMay 2022October 2023Allow1700NoNo
17746477MEMORY CHIP AND OPERATING METHOD THEREOFMay 2022January 2024Allow2001NoNo
17663053AMPLIFIER AND MEMORYMay 2022November 2024Abandon3020NoNo
17742654CIRCUIT AND METHOD FOR DATA TRANSMISSION, AND STORAGE APPARATUSMay 2022July 2023Allow1400NoNo
17742148TERNARY CONTENT ADDRESSABLE MEMORYMay 2022June 2024Allow2620YesNo
17727493THREE-STATE PROGRAMMING OF MEMORY CELLSApril 2022August 2023Allow1611NoNo
17721985RRAM VOLTAGE COMPENSATIONApril 2022April 2025Allow3651NoNo
17720296SENSE AMPLIFIER, MEMORY DEVICE AND OPERATION METHOD THEREOFApril 2022August 2024Allow2800NoNo
17717116DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTUREApril 2022March 2025Allow3541NoNo
17716609MEMORY DEVICE AND SYSTEMApril 2022February 2025Allow3431YesNo
17708629LARGE FILE INTEGRITY TECHNIQUESMarch 2022March 2023Allow1110NoNo
17703199CLUSTERING FOR READ THRESHOLDS HISTORY TABLE COMPRESSION IN NAND STORAGE SYSTEMSMarch 2022June 2023Allow1500NoNo
17700289APPARATUSES INCLUDING OUTPUT DRIVERS AND METHODS FOR PROVIDING OUTPUT DATA SIGNALSMarch 2022October 2024Allow3130YesNo
17685196SENSE AMPLIFIER SCHEMES FOR ACCESSING MEMORY CELLSMarch 2022October 2023Allow2021YesNo
17653033STORAGE CIRCUIT PROVIDED WITH VARIABLE RESISTANCE TYPE ELEMENTSMarch 2022June 2025Allow4031YesNo
17679601GIANT SPIN HALL-BASED COMPACT NEUROMORPHIC CELL OPTIMIZED FOR DIFFERENTIAL READ INFERENCEFebruary 2022May 2023Allow1511NoNo
17650622APPARATUSES AND METHODS FOR SAMPLE RATE ADJUSTMENTFebruary 2022April 2024Allow2601NoNo
17650516REFRESH CIRCUIT AND MEMORYFebruary 2022May 2023Allow1500NoNo
17667326BLOCK FAMILY COMBINATION AND VOLTAGE BIN SELECTIONFebruary 2022April 2023Allow1410NoNo
17633246AUTHENTICATED SIGNALS FOR WRITE PROTECTIONFebruary 2022February 2024Abandon2510NoNo
17665391SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEMFebruary 2022November 2023Allow2100NoNo
17584868SEMICONDUCTOR MEMORY DEVICEJanuary 2022June 2023Allow1710YesNo
17628843MAGNETIC PROCESSING UNITJanuary 2022September 2022Allow800NoNo
17578803SEMICONDUCTOR MEMORY DEVICEJanuary 2022April 2024Abandon2710NoNo
17575378APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICEJanuary 2022March 2023Allow1401NoNo
17574494DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUITJanuary 2022April 2024Allow2720NoNo
17647472METHOD AND APPARATUS FOR DETERMINING MISMATCH OF SENSE AMPLIFIER, STORAG MEDIUM, AND ELECTRONIC EQUIPMENTJanuary 2022January 2024Allow2410NoNo
17563095WRITING METHOD OF FLASH MEMORY AND MEMORY STORAGE DEVICEDecember 2021May 2024Allow2830NoNo
17557342MEMORY DEVICE AND METHOD OF OPERATING THE SAMEDecember 2021December 2023Allow2410NoNo
17554226SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACKED SEMICONDUCTOR DEVICE USING THE SAMEDecember 2021November 2023Allow2301NoNo
17555178SPLIT PULSE WIDTH MODULATION TO REDUCE CROSSBAR ARRAY INTEGRATION TIMEDecember 2021January 2025Allow3700NoNo
17644349MODIFIED TOP ELECTRODE CONTACT FOR MRAM EMBEDDING IN ADVANCED LOGIC NODESDecember 2021February 2025Allow3821YesNo
17551457MEMORY CELL IN WAFER BACKSIDEDecember 2021July 2024Allow3111YesNo
17549359METHOD AND APPARATUS FOR RECOVERING REGULAR ACCESS PERFORMANCE IN FINE-GRAINED DRAMDecember 2021April 2023Allow1601NoNo
17544679PROGRAMMING ENHANCEMENT IN SELF-SELECTING MEMORYDecember 2021March 2023Allow1601NoNo
17544202ARTIFICIAL INTELLIGENCE PROCESSOR AND METHOD OF PROCESSING DEEP-LEARNING OPERATION USING THE SAMEDecember 2021July 2023Allow2010NoNo
17544138SELECTOR DEVICE, RESISTIVE TYPE MEMORY DEVICE AND ASSOCIATED MANUFACTURING METHODDecember 2021January 2025Abandon3841NoNo
17540752EARLY DISCHARGE SEQUENCES DURING READ RECOVERY TO ALLEVIATE LATENT READ DISTURBDecember 2021June 2024Allow3121YesNo
17535771A MEMORY SYSTEM FOR PROGRAMMING DUMMY DATA TO A PORTION OF A STORAGE REGION IN A PROGRAM MODENovember 2021April 2024Allow2930YesNo
17535881NON-VOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE SAMENovember 2021April 2023Allow1601NoNo
17611253MEMORY DEVICE WITH IMPROVED DRIVER OPERATION AND METHODS TO OPERATE THE MEMORY DEVICENovember 2021January 2024Allow2610NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TRAN, ANTHAN.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
2
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
10.2%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
17
Allowed After Appeal Filing
7
(41.2%)
Not Allowed After Appeal Filing
10
(58.8%)
Filing Benefit Percentile
66.1%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 41.2% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner TRAN, ANTHAN - Prosecution Strategy Guide

Executive Summary

Examiner TRAN, ANTHAN works in Art Unit 2825 and has examined 577 patent applications in our dataset. With an allowance rate of 89.8%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 21 months.

Allowance Patterns

Examiner TRAN, ANTHAN's allowance rate of 89.8% places them in the 70% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by TRAN, ANTHAN receive 1.73 office actions before reaching final disposition. This places the examiner in the 51% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TRAN, ANTHAN is 21 months. This places the examiner in the 85% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -2.6% benefit to allowance rate for applications examined by TRAN, ANTHAN. This interview benefit is in the 5% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 31.7% of applications are subsequently allowed. This success rate is in the 57% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 22.6% of cases where such amendments are filed. This entry rate is in the 21% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 109.1% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 77% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 85.7% of appeals filed. This is in the 76% percentile among all examiners. Of these withdrawals, 58.3% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 26.9% are granted (fully or in part). This grant rate is in the 18% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 1.2% of allowed cases (in the 71% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).

Quayle Actions: This examiner issues Ex Parte Quayle actions in 8.1% of allowed cases (in the 85% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.
  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.