Detailed information about the 100 most recent patent applications.
| Application Number | Title | Filing Date | Disposal Date | Disposition | Time (months) | Office Actions | Restrictions | Interview | Appeal |
|---|---|---|---|---|---|---|---|---|---|
| 17137461 | PROGRAM METHOD INCLUDING MULTIPLE PRECHARGE STEPS FOR MEMORY DEVICE | December 2020 | March 2022 | Allow | 14 | 0 | 0 | No | No |
| 17136441 | PROGRAMMING TIME IMPROVEMENT BY LOW VOLTAGE VERIFY SKIP | December 2020 | December 2023 | Abandon | 36 | 4 | 1 | No | No |
| 17135071 | POWER SAVING AND FAST READ SEQUENCE FOR NON-VOLATILE MEMORY | December 2020 | March 2023 | Allow | 27 | 3 | 0 | Yes | No |
| 17129016 | MEMORY DEVICE AND METHOD FOR COUPLING A MAIN BITLINE TO TWO POINTS OF A LOCAL BITLINE | December 2020 | April 2022 | Allow | 15 | 1 | 0 | No | No |
| 17124084 | OPERATIONAL MODES FOR REDUCED POWER CONSUMPTION IN A MEMORY SYSTEM | December 2020 | January 2022 | Allow | 13 | 0 | 0 | No | No |
| 17122031 | Sensing Techniques for Resistive Memory | December 2020 | April 2022 | Allow | 16 | 1 | 0 | No | No |
| 17120337 | APPARATUS AND METHODS FOR DETERMINING DATA STATES OF MEMORY CELLS | December 2020 | May 2023 | Allow | 29 | 1 | 0 | No | No |
| 17247267 | WAVE PIPELINE | December 2020 | February 2022 | Allow | 14 | 0 | 0 | No | No |
| 17111751 | SENSE LINE STRUCTURES IN CAPACITIVE SENSE NAND MEMORY | December 2020 | January 2023 | Allow | 26 | 0 | 0 | No | No |
| 17112755 | DRAGGING FIRST PASS READ LEVEL THRESHOLDS BASED ON CHANGES IN SECOND PASS READ LEVEL THRESHOLDS | December 2020 | December 2021 | Allow | 13 | 1 | 0 | No | No |
| 17111729 | CAPACITIVE SENSE NAND MEMORY | December 2020 | April 2022 | Allow | 17 | 1 | 0 | No | No |
| 17110782 | APPARATUSES AND METHODS FOR SENSING MEMORY CELLS | December 2020 | August 2021 | Allow | 9 | 1 | 0 | No | No |
| 17098831 | ALL BIT LINE SENSING FOR DETERMINING WORD LINE-TO-MEMORY HOLE SHORT CIRCUIT | November 2020 | February 2022 | Allow | 15 | 0 | 0 | Yes | No |
| 17096966 | SENSE AMPLIFIER AND OPERATING METHOD FOR NON-VOLATILE MEMORY WITH REDUCED NEED ON ADJUSTING OFFSET TO COMPENSATE THE MISMATCH | November 2020 | February 2022 | Allow | 15 | 0 | 0 | No | No |
| 17096064 | TWO-BIT MAGNETORESISTIVE RANDOM-ACCESS MEMORY CELL | November 2020 | September 2022 | Allow | 22 | 2 | 0 | No | No |
| 17091860 | MEMORY CYCLING TRACKING FOR THRESHOLD VOLTAGE VARIATION SYSTEMS AND METHODS | November 2020 | January 2022 | Allow | 14 | 0 | 0 | No | No |
| 17090438 | POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS | November 2020 | June 2022 | Allow | 19 | 1 | 0 | Yes | No |
| 17087429 | SINGLE-LAYER POLYSILICON NONVOLATILE MEMORY CELL AND MEMORY INCLUDING THE SAME | November 2020 | August 2022 | Allow | 21 | 2 | 0 | No | No |
| 17076316 | PHASE-CHANGE MEMORY DEVICE FOR IMPROVING RESISTANCE DRIFT AND DYNAMIC RESISTANCE DRIFT COMPENSATION METHOD OF THE SAME | October 2020 | March 2022 | Allow | 17 | 1 | 0 | Yes | No |
| 17075589 | MEMORY DEVICE FOR PERFORMING PROGRAM VERIFY OPERATION AND METHOD OF OPERATING THE SAME | October 2020 | February 2022 | Allow | 16 | 1 | 0 | Yes | No |
| 17074758 | DATA ERASE OPERATIONS FOR A MEMORY SYSTEM | October 2020 | May 2022 | Allow | 18 | 2 | 0 | Yes | No |
| 17073404 | OPERATING METHOD OF GENERATING ENHANCED BIT LINE VOLTAGE AND NON-VOLATILE MEMORY DEVICE | October 2020 | October 2021 | Allow | 12 | 0 | 0 | No | No |
| 17068258 | MEMORY DEVICE FOR PERFORMING DUMMY PROGRAM OPERATION AND OPERATING METHOD THEREOF | October 2020 | March 2022 | Allow | 17 | 1 | 0 | No | No |
| 17037655 | OPERATING METHOD FOR IMPROVING PERFORMANCE OF SELECTOR DEVICE | September 2020 | June 2022 | Allow | 20 | 2 | 0 | No | No |
| 17016580 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS AT OPPOSING SIDES OF SEMICONDUCTOR | September 2020 | October 2021 | Allow | 14 | 0 | 0 | No | No |
| 17004680 | SEMICONDUCTOR STORAGE DEVICE THAT PERFORMS A VERIFICATION OPERATION IN A SELECTIVE MANNER | August 2020 | April 2022 | Allow | 19 | 1 | 0 | Yes | No |
| 17002583 | PHASE TRANSITION BASED RESISTIVE RANDOM-ACCESS MEMORY | August 2020 | October 2022 | Abandon | 25 | 2 | 0 | No | No |
| 16999869 | FLOATING BODY DRAM WITH REDUCED ACCESS ENERGY | August 2020 | December 2021 | Allow | 16 | 1 | 0 | No | No |
| 16968662 | CROSS POINT DEVICE AND STORAGE APPARATUS | August 2020 | August 2023 | Abandon | 36 | 1 | 0 | No | No |
| 16988729 | NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD FOR MITIGATING MEMORY CELL OVERWRITTEN | August 2020 | April 2022 | Allow | 20 | 2 | 0 | No | No |
| 16983874 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE ADDRESS COUNTING CIRCUIT | August 2020 | May 2022 | Allow | 21 | 2 | 0 | Yes | No |
| 16944032 | SEMICONDUCTOR MEMORY DEVICE | July 2020 | December 2021 | Allow | 16 | 1 | 0 | Yes | No |
| 16943345 | STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE | July 2020 | May 2022 | Allow | 21 | 3 | 0 | No | No |
| 16941045 | NON-VOLATILE MEMORY DEVICE INCLUDING A VERIFY CIRCUIT TO CONTROL WORD AND BIT LINE VOLTAGES AND METHOD OF OPERATING THE SAME | July 2020 | September 2021 | Allow | 14 | 0 | 0 | No | No |
| 16925215 | DYNAMIC VOLTAGE SETTING OPTIMIZATION DURING LIFETIME OF A MEMORY DEVICE | July 2020 | April 2023 | Allow | 33 | 1 | 0 | No | No |
| 16919739 | VOLTAGE GENERATING CIRCUIT AND A NONVOLATILE MEMORY APPARATUS USING THE VOLTAGE GENERATING CIRCUIT | July 2020 | July 2021 | Allow | 13 | 0 | 0 | No | No |
| 16959496 | SUPPORTING RESPONSES FOR MEMORY TYPES WITH NON-UNIFORM LATENCIES ON SAME CHANNEL | July 2020 | June 2022 | Allow | 23 | 1 | 0 | No | No |
| 16917291 | Dual Sense Bin Balancing In NAND Flash | June 2020 | February 2022 | Allow | 20 | 2 | 0 | Yes | No |
| 16911461 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY IN WHICH THE CHANNEL POTENTIAL OF A MEMORY CELL IN A NON-SELECTED NAND CELL UNIT IS INCREASED | June 2020 | April 2022 | Allow | 22 | 2 | 0 | No | No |
| 16904869 | NON-VOLATILE MEMORY DEVICE HAVING A READING CIRCUIT OPERATING AT LOW VOLTAGE | June 2020 | November 2021 | Allow | 17 | 1 | 0 | No | No |
| 16898533 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE THAT CONTROLS THE ERASE SPEEDS OF CELL STRINGS | June 2020 | August 2021 | Allow | 14 | 1 | 0 | No | No |
| 16896787 | MAGNETIC DEVICES INCLUDING IRON-RHODIUM FILMS PROVIDING BI-STABLE MAGNETIC ORDER AT ROOM TEMPERATURE, MAGNETIC MEMORY SYSTEMS INCLUDING THE SAME AND RELATED METHODS OF OPERATION | June 2020 | March 2023 | Abandon | 33 | 3 | 1 | No | No |
| 16892817 | METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY | June 2020 | December 2021 | Allow | 18 | 1 | 0 | No | No |
| 16892398 | SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONALLY STACKED MEMORY CELLS | June 2020 | August 2021 | Allow | 14 | 0 | 0 | No | No |
| 16888095 | PRE-CHARGE TIMING CONTROL FOR PEAK CURRENT BASED ON DATA LATCH COUNT | May 2020 | September 2021 | Allow | 16 | 1 | 0 | No | No |
| 16888009 | Pre-Charge Ramp Rate Control For Peak Current Based On Data Latch Count | May 2020 | October 2021 | Allow | 16 | 1 | 0 | No | No |
| 16888233 | FLASH MEMORY DEVICE AND BIT LINE CHARGING METHOD THEREOF | May 2020 | October 2021 | Allow | 17 | 1 | 0 | No | No |
| 16882754 | VOLTAGE GENERATING CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND BIT LINE CHARGING METHOD THEREOF | May 2020 | September 2021 | Allow | 16 | 1 | 0 | No | No |
| 16882064 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS WITH DIFFERENT CHANNEL-FORMATION MATERIALS | May 2020 | September 2022 | Allow | 28 | 2 | 0 | No | No |
| 16869059 | TWO MEMORY CELLS SENSED TO DETERMINE ONE DATA VALUE | May 2020 | May 2021 | Allow | 13 | 1 | 0 | Yes | No |
| 16842225 | MANAGING BIT LINE VOLTAGE GENERATING CIRCUITS IN MEMORY DEVICES | April 2020 | February 2022 | Allow | 23 | 0 | 0 | No | No |
| 16831568 | SEMICONDUCTOR MEMORY DEVICE HAVING BONDED FIRST AND SECOND SEMICONDUCTOR CHIPS PROVIDED WITH RESPECTIVE IMPEDANCE CALIBRATION CONTROL CIRCUITS | March 2020 | February 2022 | Allow | 23 | 3 | 0 | No | No |
| 16829149 | Memory Repair Scheme | March 2020 | August 2021 | Allow | 17 | 1 | 0 | Yes | No |
| 16824460 | SEMICONDUCTOR DEVICE PERFORMING ROW HAMMER REFRESH OPERATION | March 2020 | September 2021 | Allow | 18 | 0 | 1 | No | No |
| 16819710 | SEMICONDUCTOR APPARATUS FOR COMPENSATING FOR DEGRADATION AND SEMICONDUCTOR SYSTEM USING THE SAME | March 2020 | April 2021 | Allow | 13 | 0 | 0 | No | No |
| 16819451 | LONGEST ELEMENT LENGTH DETERMINATION IN MEMORY | March 2020 | December 2020 | Allow | 9 | 1 | 0 | Yes | No |
| 16819790 | SEMICONDUCTOR APPARATUS FOR COMPENSATING FOR DEGRADATION AND SEMICONDUCTOR SYSTEM USING THE SAME | March 2020 | August 2021 | Allow | 17 | 1 | 0 | No | No |
| 16818989 | SEMICONDUCTOR DEVICE PERFORMING ROW HAMMER REFRESH OPERATION | March 2020 | September 2021 | Allow | 18 | 1 | 0 | No | No |
| 16813721 | MULTILAYER BACK END OF LINE (BEOL)-STACKABLE CROSS-POINT MEMORY ARRAY WITH COMPLEMENTARY PASS TRANSISTOR SELECTORS | March 2020 | September 2020 | Allow | 6 | 0 | 0 | No | No |
| 16809365 | NEURAL NETWORK COMPUTATION CIRCUIT INCLUDING SEMICONDUCTOR MEMORY ELEMENT, AND METHOD OF OPERATION | March 2020 | September 2022 | Allow | 30 | 1 | 0 | No | No |
| 16802073 | SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM | February 2020 | March 2021 | Allow | 12 | 1 | 0 | No | No |
| 16786779 | Wordline Coupling Techniques | February 2020 | April 2022 | Allow | 26 | 2 | 1 | No | No |
| 16784899 | REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES | February 2020 | September 2020 | Allow | 7 | 1 | 0 | No | No |
| 16784837 | SEMICONDUCTOR MEMORY DEVICE WITH CACHE LATCHES | February 2020 | June 2021 | Allow | 16 | 1 | 0 | Yes | No |
| 16775639 | IN-STORAGE LOGIC FOR HARDWARE ACCELERATORS | January 2020 | February 2022 | Allow | 25 | 0 | 0 | No | No |
| 16734467 | PROGRAMMING METHOD FOR TIGHTENING THRESHOLD VOLTAGE DISTRIBUTION OF MEMORY CELLS | January 2020 | September 2021 | Abandon | 20 | 2 | 0 | Yes | No |
| 16729787 | MULTI-STATE PROGRAMMING OF MEMORY CELLS | December 2019 | July 2021 | Allow | 18 | 1 | 0 | Yes | No |
| 16713165 | MODE CONVERSION METHOD AND APPARATUS FOR A NONVOLATILE MEMORY | December 2019 | March 2021 | Allow | 16 | 0 | 0 | No | No |
| 16709687 | Circuit Architecture to Derive Higher Mux From Lower Mux Design | December 2019 | April 2021 | Allow | 16 | 1 | 0 | No | No |
| 16708313 | READ-ONCE MEMORY | December 2019 | August 2021 | Allow | 20 | 1 | 1 | No | No |
| 16704817 | TEMPERATURE AND CYCLING DEPENDENT REFRESH OPERATION FOR MEMORY CELLS | December 2019 | April 2021 | Allow | 16 | 1 | 1 | Yes | No |
| 16702509 | DYNAMIC RANDOM ACCESS MEMORY WITH SHAPED WORD-LINE WAVEFORM | December 2019 | April 2021 | Allow | 16 | 1 | 0 | No | No |
| 16679762 | WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY | November 2019 | December 2020 | Allow | 14 | 1 | 0 | No | No |
| 16679782 | WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY | November 2019 | August 2020 | Allow | 9 | 0 | 0 | No | No |
| 16679355 | PHASE-CHANGE MEMORY CELL WITH VANADIUM OXIDE-BASED SWITCHING LAYER | November 2019 | March 2021 | Allow | 16 | 1 | 0 | No | No |
| 16672089 | YIELD-CENTRIC POWER GATED REGULATED SUPPLY DESIGN WITH PROGRAMMABLE LEAKERS | November 2019 | March 2021 | Allow | 17 | 1 | 0 | No | No |
| 16670619 | METHOD OF OPERATING MEMORY DEVICE IN TEST MODE | October 2019 | December 2020 | Allow | 13 | 0 | 0 | No | No |
| 16668073 | AREA EFFECTIVE ERASE VOLTAGE ISOLATION IN NAND MEMORY | October 2019 | September 2020 | Allow | 11 | 0 | 0 | No | No |
| 16668685 | NONVOLATILE MEMORY INCLUDING DUTY CORRECTION CIRCUIT AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY | October 2019 | October 2020 | Allow | 12 | 2 | 0 | Yes | No |
| 16667773 | METHODS AND SYSTEMS FOR HIGHLY OPTIMIZED MEMRISTOR WRITE PROCESS | October 2019 | February 2021 | Allow | 15 | 1 | 0 | No | No |
| 16664970 | MEMORY UNIT FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS, MEMORY ARRAY STRUCTURE FOR MULTI-BIT CONVOLUTIONAL NEURAL NETWORK BASED COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF | October 2019 | August 2022 | Allow | 34 | 1 | 0 | No | No |
| 16595991 | Mattress with Adjustable Firmness | October 2019 | November 2020 | Allow | 13 | 1 | 0 | No | No |
| 16594260 | MEMORY SYSTEM IN WHICH CONTROLLER ACQUIRES STATUS OF NONVOLATILE MEMORY AND CONTROL METHOD THEREOF | October 2019 | February 2021 | Allow | 16 | 1 | 0 | No | No |
| 16593529 | REINFORCEMENT LEARNING PULSE PROGRAMMING | October 2019 | June 2022 | Allow | 32 | 0 | 0 | No | No |
| 16587215 | Memory Circuit and Cache Circuit Configuration | September 2019 | August 2021 | Allow | 23 | 1 | 0 | No | No |
| 16583157 | TECHNIQUES TO GENERATE & ADJUST PROGRAM CURRENT PULSES FOR CROSS-POINT NONVOLATILE MEMORY | September 2019 | September 2021 | Abandon | 24 | 2 | 0 | Yes | No |
| 16570634 | MEMORY CELL AND MEMORY CELL ARRAY HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHODS OF OPERATING SAME | September 2019 | April 2021 | Allow | 19 | 3 | 0 | No | No |
| 16558683 | CHARGE SEPARATION FOR MEMORY SENSING | September 2019 | September 2020 | Allow | 13 | 2 | 0 | Yes | No |
| 16555012 | APPARATUSES AND METHODS FOR SUBARRAY ADDRESSING | August 2019 | August 2020 | Allow | 11 | 1 | 0 | Yes | No |
| 16552506 | MEMORY MODULES AND MEMORY SYSTEMS INCLUDING A POWER MANAGEMENT INTEGRATED CIRCUIT | August 2019 | September 2020 | Allow | 12 | 1 | 0 | No | No |
| 16547727 | MATERIAL IMPLICATION OPERATIONS IN MEMORY | August 2019 | September 2020 | Allow | 13 | 1 | 0 | No | No |
| 16543739 | MAGNETIC STORAGE DEVICE | August 2019 | October 2020 | Allow | 14 | 0 | 1 | No | No |
| 16484881 | MEMORY WITH IMPROVED CROSS TEMPERATURE RELIABILITY AND READ PERFORMANCE | August 2019 | April 2021 | Allow | 21 | 2 | 0 | No | No |
| 16531619 | APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE | August 2019 | November 2020 | Allow | 16 | 1 | 0 | Yes | No |
| 16523953 | MEMORY CIRCUIT INCLUDING A FIRST PROGRAM DEVICE | July 2019 | July 2021 | Allow | 23 | 2 | 1 | Yes | No |
| 16518701 | SEQUENTIAL WRITE AND SEQUENTIAL WRITE VERIFY IN MEMORY DEVICE | July 2019 | January 2021 | Allow | 18 | 2 | 0 | No | No |
| 16514431 | IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES | July 2019 | February 2021 | Allow | 19 | 1 | 1 | No | No |
| 16509913 | FLASH MEMORY WITH REFERENCE VOLTAGE GENERATION FROM A PLURALITY OF CELLS | July 2019 | October 2020 | Allow | 15 | 0 | 0 | No | No |
| 16509090 | APPARATUSES AND METHODS FOR SENSING MEMORY CELLS | July 2019 | August 2020 | Allow | 13 | 2 | 0 | Yes | No |
| 16504351 | SENSING CIRCUIT WITH ADAPTIVE LOCAL REFERENCE GENERATION OF RESISTIVE MEMORY AND SENSING METHOD THEREOF | July 2019 | June 2020 | Allow | 11 | 0 | 0 | No | No |
This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BUI, THA-O H.
With a 25.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.
Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.
In this dataset, 29.2% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.
⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.
⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.
Examiner BUI, THA-O H works in Art Unit 2825 and has examined 554 patent applications in our dataset. With an allowance rate of 87.9%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 19 months.
Examiner BUI, THA-O H's allowance rate of 87.9% places them in the 69% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.
On average, applications examined by BUI, THA-O H receive 1.63 office actions before reaching final disposition. This places the examiner in the 29% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.
The median time to disposition (half-life) for applications examined by BUI, THA-O H is 19 months. This places the examiner in the 94% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.
Conducting an examiner interview provides a +0.3% benefit to allowance rate for applications examined by BUI, THA-O H. This interview benefit is in the 19% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.
When applicants file an RCE with this examiner, 29.5% of applications are subsequently allowed. This success rate is in the 59% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.
This examiner enters after-final amendments leading to allowance in 34.9% of cases where such amendments are filed. This entry rate is in the 54% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.
When applicants request a pre-appeal conference (PAC) with this examiner, 47.6% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 43% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.
This examiner withdraws rejections or reopens prosecution in 69.2% of appeals filed. This is in the 55% percentile among all examiners. Of these withdrawals, 44.4% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.
When applicants file petitions regarding this examiner's actions, 25.0% are granted (fully or in part). This grant rate is in the 13% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.
Examiner's Amendments: This examiner makes examiner's amendments in 0.2% of allowed cases (in the 50% percentile). This examiner makes examiner's amendments more often than average to place applications in condition for allowance (MPEP § 1302.04).
Quayle Actions: This examiner issues Ex Parte Quayle actions in 13.1% of allowed cases (in the 92% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.
Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:
Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.
No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.
Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.
Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.