USPTO Examiner BUI THA O H - Art Unit 2825

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18615521RRAM CIRCUITMarch 2024January 2025Allow1010NoNo
18582185PARALLEL ACCESS IN A MEMORY ARRAYFebruary 2024January 2025Allow1110NoNo
18400297NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICEDecember 2023January 2025Allow1210YesNo
18522829NONVOLATILE MEMORY DEVICE INCLUDING A LOGIC CIRCUIT TO CONTROL WORD LINE VOLTAGESNovember 2023July 2024Allow810NoNo
18388032VOLATILE DATA STORAGE IN NAND MEMORYNovember 2023June 2025Allow1900NoNo
18386472MEMORY DEVICE HAVING ASYMMETRIC PAGE BUFFER ARRAY ARCHITECTURENovember 2023June 2025Allow1900NoNo
18377623Resistive Change Element ArraysOctober 2023August 2024Allow1010NoNo
18370866MEMORY CONTROL CIRCUIT CAPABLE OF GENERATING AN UPDATED REFERENCE CURRENTSeptember 2023June 2025Allow2000NoNo
18242397POWER LEAKAGE BLOCKING IN LOW-DROPOUT REGULATORSeptember 2023June 2024Allow910NoNo
18460911CODE COMPARATORS WITH NONPOLAR DYNAMICAL SWITCHESSeptember 2023May 2025Allow2100NoNo
18459357MEMORY DEVICE INCLUDING ROW DECODERAugust 2023May 2025Allow2100NoNo
18456554SEMICONDUCTOR MEMORY DEVICEAugust 2023April 2025Allow2000NoNo
18362198Novel Bank Design with Differential Bulk Bias in eFuse arrayJuly 2023September 2024Allow1410NoNo
18341088MEMORY CIRCUIT AND CACHE CIRCUIT CONFIGURATIONJune 2023May 2024Allow1110NoNo
18340977THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY HAVING A CONTROLLER CONFIGURED TO EXECUTE A PROGRAM OPERATION ON MEMORY CELLSJune 2023August 2024Allow1410NoNo
18338153SEMICONDUCTOR DEVICEJune 2023March 2025Allow2100NoNo
18315703SEMICONDUCTOR DEVICESMay 2023April 2025Allow2300NoNo
18195181REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICESMay 2023April 2024Allow1110NoNo
18312696MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY AND CONTROLLER CAPABLE OF DETERMINING NECESSARY SHIFTED BOUNDARY READ VOLTAGES IN A SHORT PERIOD OF TIMEMay 2023April 2024Allow1110NoNo
18142423PIECEWISE LINEAR AND TRIMMABLE TEMPERATURE SENSORMay 2023March 2024Allow1010NoNo
18031356HIGH-SPEED AND LARGE-CURRENT ADJUSTABLE PULSE CIRCUIT, OPERATING CIRCUIT AND OPERATING METHOD OF PHASE-CHANGE MEMORYApril 2023December 2024Allow2010NoNo
18192294SEMICONDUCTOR MEMORY WITH ADJUSTMENT CIRCUIT AND METHOD FOR CONTROLLING A SEMICONDUCTOR MEMORYMarch 2023July 2025Allow2710NoNo
18188684QUANTUM INFORMATION STORAGE DEVICEMarch 2023May 2025Allow2500NoNo
18186960CONVERTIBLE MEMORY DEVICEMarch 2023March 2025Allow2410NoNo
18186480STORAGE DEVICE FOR BACKING UP STATE GROUP DATA IN THE EVENT OF A SUDDEN POWER-OFF AND PROGRAM METHOD THEREOFMarch 2023May 2025Allow2620YesNo
18122928MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR MULTI-PASS PROGRAMMING THEREOF TO REDUCE PROGRAMMING TIMEMarch 2023February 2025Allow2310NoNo
18184842VOLTAGE GENERATOR AND MEMORY DEVICE INCLUDING THE SAMEMarch 2023March 2025Allow2410YesNo
18121466SEMICONDUCTOR DEVICE FOR WRITING TO A STORAGE ELEMENTMarch 2023February 2025Allow2310NoNo
18180864FORMING OPERATION METHOD OF RESISTIVE RANDOM ACCESS MEMORYMarch 2023December 2024Allow2110NoNo
18179505MEMORY SYSTEM FOR PERFORMING AN ERASE VOLTAGE APPLICATION OPERATION AND AN ERASE VERIFY OPERATION FOR A NONVOLATILE MEMORYMarch 2023March 2025Allow2410YesNo
18117974APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHEMarch 2023March 2024Allow1210NoNo
18179310MEMORY SYSTEM AND CONTROL METHOD TO SAVE DATA AFTER A POWER DISABLE REQUESTMarch 2023June 2025Allow2720YesNo
18115999PIPE REGISTER AND SEMICONDUCTOR APPARATUS INCLUDING THE PIPE REGISTERMarch 2023March 2025Allow2410NoNo
18176347FLASH MEMORY DEVICE FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SENSING METHOD THEREOFFebruary 2023December 2024Allow2100NoNo
18176442SEMICONDUCTOR MEMORY DEVICE HAVING A CONTROL CIRCUIT FOR CHANGING A DRIVE CAPABILITY OF AN OUTPUT CIRCUIT OF THE SEMICONDUCTOR MEMORY DEVICEFebruary 2023March 2025Allow2410NoNo
18175043NONVOLATILE MEMORY DEVICE INCLUDING A LOGIC CIRCUIT TO CONTROL WORD AND BITLINE VOLTAGESFebruary 2023August 2023Allow610NoNo
18173242DEGRADATION-AWARE TRAINING SCHEME FOR RELIABLE MEMRISTOR DEEP LEARNING ACCELERATOR DESIGNFebruary 2023March 2025Allow2510NoNo
18110489MEMORIES FOR PERFORMING SUCCESSIVE PROGRAMMING OPERATIONSFebruary 2023February 2025Allow2410NoNo
18169610ERROR DETECTION, CORRECTION, AND MEDIA MANAGEMENT ON A DRAM DEVICEFebruary 2023March 2025Allow2510NoNo
18167617MEMORY DEVICE AND METHOD FOR FORMING THE SAMEFebruary 2023December 2024Allow2200NoNo
18166737MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM INCLUDING COMMAND AND ADDRESS TRAININGFebruary 2023February 2025Allow2400NoNo
18107200MEMORY DEVICES WITH DYNAMIC PROGRAM VERIFY LEVELSFebruary 2023August 2023Allow710NoNo
18163584WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM)February 2023September 2024Allow1900NoNo
18103364DRIVE CIRCUIT WITH IMPROVED TIMING MARGIN FOR MEMORY DEVICEJanuary 2023February 2025Allow2510NoNo
18101140SEMICONDUCTOR DEVICE INCLUDING TRANSISTORJanuary 2023February 2024Allow1310NoNo
18101287MEMORY DEVICE SUPPORTING IN-MEMORY MAC OPERATION BETWEEN TERNARY INPUT DATA AND BINARY WEIGHT USING CHARGE SHARING METHOD AND OPERATION METHOD THEREOFJanuary 2023December 2024Allow2210NoNo
18156955THREE-DIMENSIONAL MEMORY DEVICE AND IMPROVED METHODS OF READING THE SAME BY SHORTENING READ TIMESJanuary 2023August 2024Allow1930NoNo
18155900COUNTER CIRCUITJanuary 2023September 2024Allow2000NoNo
18095711MEMORY DEVICES FOR PROGRAM VERIFY OPERATIONSJanuary 2023July 2023Allow610NoNo
18095049MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELSJanuary 2023October 2023Allow910NoNo
18062262SEMICONDUCTOR DEVICE AND TESTING METHOD FOR MEMORY CIRCUITDecember 2022March 2025Allow2720NoNo
18054359RRAM CIRCUITNovember 2022November 2023Allow1310NoNo
17975609SEMICONDUCTOR MEMORY DEVICEOctober 2022June 2024Allow2000NoNo
17973726SELECTABLE ROW HAMMER MITIGATIONOctober 2022February 2025Allow2710YesNo
17962683CONFLICT DETECTION AND ADDRESS ARBITRATION FOR ROUTING SCATTER AND GATHER TRANSACTIONS FOR A MEMORY BANKOctober 2022March 2025Allow2910YesNo
17956938SPIN-ORBIT-TORQUE (SOT) MRAM WITH DOUBLED LAYER OF SOT METALSeptember 2022March 2025Allow2910NoNo
17956225STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THE SAMESeptember 2022August 2024Allow2310YesNo
17954664SIGNAL SAMPLING CIRCUIT AND SEMICONDUCTOR MEMORYSeptember 2022April 2025Allow3010NoNo
17936107DATA RECEIVING CIRCUIT, DATA RECEIVING SYSTEM, AND MEMORY DEVICESeptember 2022August 2024Allow2310NoNo
17949000SEMICONDUCTOR MEMORY DEVICE INCLUDING COMMAND LOG REGISTER AND COMMAND LOG OUTPUT METHOD THEREOFSeptember 2022August 2024Allow2300NoNo
17944692WRITE-ONCE MEMORY ENCODED DATASeptember 2022February 2025Allow2920NoNo
17943550POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORSSeptember 2022June 2023Allow910NoNo
17943139DATA ERASE OPERATIONS FOR A MEMORY SYSTEMSeptember 2022March 2025Allow3040YesNo
17941655ALIASED ROW HAMMER DETECTORSeptember 2022September 2024Allow2410YesNo
17897716Wordline Coupling TechniquesAugust 2022July 2023Allow1010NoNo
17895304MIXED BITLINE LOCKOUT FOR QLC/TLC DIEAugust 2022March 2025Allow3020YesNo
17892437PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICEAugust 2022April 2024Allow1900NoNo
17892130RECONFIGURABLE COMPUTATIONAL MEMORY DEVICE, OPERATION METHOD OF THE RECONFIGURABLE COMPUTATIONAL MEMORY DEVICE AND SEMICONDUCTOR DIE INCLUDING THE RECONFIGURABLE COMPUTATIONAL MEMORY DEVICEAugust 2022August 2024Allow2310YesNo
17891395MEMORY CLOCK LEVEL-SHIFTING BUFFER WITH EXTENDED RANGEAugust 2022April 2024Allow2000NoNo
17891859ADAPTIVE INTEGRITY SCAN RATES IN A MEMORY SUB-SYSTEM BASED ON BLOCK HEALTH METRICSAugust 2022June 2025Allow3430YesNo
17884929NON-VOLATILE MEMORY WITH EARLY DUMMY WORD LINE RAMP DOWN AFTER PRECHARGEAugust 2022August 2024Allow2410YesNo
17881231MEMORY DEVICE WITH DUMMY WORD LINE, SYSTEM AND METHOD FOR PROGRAMMING THEREOFAugust 2022August 2024Allow2520YesNo
17876718METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES FOR CAPACITIVE SENSE NAND MEMORYJuly 2022April 2024Allow2100NoNo
17874973STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICEJuly 2022June 2024Allow2340YesNo
17874813DRIVE CIRCUIT, METHOD FOR DRIVING DRIVE CIRCUIT, AND MEMORYJuly 2022June 2024Allow2310NoNo
17873850POWER ARCHITECTURE FOR NON-VOLATILE MEMORYJuly 2022May 2023Allow1010NoNo
17871422MEMORY DEVICE, MEMORY SYSTEM, AND READ OPERATION METHOD THEREOFJuly 2022October 2024Allow2630YesNo
17813998READOUT CIRCUIT LAYOUT STRUCTURE AND METHOD OF READING DATAJuly 2022January 2023Allow600NoNo
17866327MITIGATING DUTY CYCLE DISTORTION DEGRADATION DUE TO DEVICE AGING ON HIGH-BANDWIDTH MEMORY INTERFACEJuly 2022March 2024Allow2000NoNo
17864674THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY WHEREIN FIRST THROUGH FIFTH VOLTAGES ARE APPLIED AT DIFFERENT TIMINGS IN A PROGRAM OPERATIONJuly 2022March 2023Allow810YesNo
17857581PHASE-CHANGE MEMORY DEVICE FOR IMPROVING RESISTANCE DRIFT AND DYNAMIC RESISTANCE DRIFT COMPENSATION METHOD OF THE SAMEJuly 2022August 2023Allow1310NoNo
17847810PROGRAMMABLE LOGIC COMPUTATION IN MEMORYJune 2022April 2024Allow2200NoNo
17847967SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEMJune 2022July 2024Allow2510NoNo
17844965SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD FOR PERFORMING PROGRAM OPERATIONJune 2022May 2025Allow3520NoNo
17842766SEMICONDUCTOR STORAGE DEVICE HAVING BIT LINE SELECTION CIRCUIT FORMED IN MEMORY CELL ARRAYJune 2022April 2024Allow2200NoNo
17829333SENSE AMPLIFIER AND OPERATING METHOD FOR NON-VOLATILE MEMORY WITH REDUCED NEED ON ADJUSTING OFFSET TO COMPENSATE THE MISMATCHMay 2022February 2023Allow810NoNo
17751131REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICESMay 2022February 2023Allow810NoNo
17737259ONE-TIME PROGRAMMABLE (OTP) MEMORY AND METHOD OF OPERATING THE SAMEMay 2022January 2025Allow3330NoNo
17736226SEMICONDUCTOR MEMORY DEVICE INCLUDING ACTIVE REGIONS FOR REDUCING DISTURBANCEMay 2022June 2024Allow2610NoNo
17733162ELECTRONIC DEVICES FOR PERFORMING A POST-WRITE OPERATION AND ELECTRONIC SYSTEMSApril 2022April 2024Allow2300NoNo
17726351OPERATIONAL MODES FOR REDUCED POWER CONSUMPTION IN A MEMORY SYSTEMApril 2022June 2023Allow1410NoNo
17724499SEMICONDUCTOR DEVICE AND OPERATION METHOD HAVING POWER-ON OPERATIONApril 2022April 2024Allow2400NoNo
17723167SEMICONDUCTOR MEMORY DEVICE INCLUDING PASS TRANSISTORS WITH VARIABLE SIZESApril 2022May 2024Allow2500NoNo
17720843SEMICONDUCTOR MEMORY DEVICE WITH OPERATION LIMIT CONTROLLERApril 2022March 2024Allow2310YesNo
17719646SEMICONDUCTOR ELEMENT MEMORY DEVICEApril 2022September 2023Allow1700NoNo
17717657THRESHOLD VOLTAGE VARIATION COMPENSATION IN INTEGRATED CIRCUITSApril 2022January 2024Allow2100NoNo
17715959MEMORY DEVICE WITH SRAM CELLS ASSISTED BY NON-VOLATILE MEMORY CELLS AND OPERATION METHOD THEREOFApril 2022November 2023Allow1900NoNo
17715370FLOATING BODY DRAM WITH REDUCED ACCESS ENERGYApril 2022June 2023Allow1510NoNo
17715647MEMORY APPARATUS AND METHOD OF OPERATION USING STATE DEPENDENT STROBE TIER SCAN TO REDUCE PEAK ICCApril 2022April 2024Allow2410NoNo
17714379READ THRESHOLD CALIBRATION FOR CROSS-TEMPERATURE LONG, SEQUENTIAL READSApril 2022March 2024Allow2410NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BUI, THA-O H.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
8
Examiner Affirmed
6
(75.0%)
Examiner Reversed
2
(25.0%)
Reversal Percentile
38.8%
Lower than average

What This Means

With a 25.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is below the USPTO average, indicating that appeals face more challenges here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
27
Allowed After Appeal Filing
8
(29.6%)
Not Allowed After Appeal Filing
19
(70.4%)
Filing Benefit Percentile
41.9%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 29.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Examiner BUI, THA-O H - Prosecution Strategy Guide

Executive Summary

Examiner BUI, THA-O H works in Art Unit 2825 and has examined 798 patent applications in our dataset. With an allowance rate of 90.7%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 20 months.

Allowance Patterns

Examiner BUI, THA-O H's allowance rate of 90.7% places them in the 73% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by BUI, THA-O H receive 1.46 office actions before reaching final disposition. This places the examiner in the 34% percentile for office actions issued. This examiner issues fewer office actions than average, which may indicate efficient prosecution or a more lenient examination style.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by BUI, THA-O H is 20 months. This places the examiner in the 89% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -0.8% benefit to allowance rate for applications examined by BUI, THA-O H. This interview benefit is in the 8% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 30.3% of applications are subsequently allowed. This success rate is in the 51% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 35.5% of cases where such amendments are filed. This entry rate is in the 45% percentile among all examiners. Strategic Recommendation: This examiner shows below-average receptiveness to after-final amendments. You may need to file an RCE or appeal rather than relying on after-final amendment entry.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 56.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 45% percentile among all examiners. Note: Pre-appeal conferences show below-average success with this examiner. Consider whether your arguments are strong enough to warrant a PAC request.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 72.4% of appeals filed. This is in the 56% percentile among all examiners. Of these withdrawals, 52.4% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 28.6% are granted (fully or in part). This grant rate is in the 20% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.1% of allowed cases (in the 46% percentile). This examiner makes examiner's amendments less often than average. You may need to make most claim amendments yourself.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 17.7% of allowed cases (in the 92% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

    Relevant MPEP Sections for Prosecution Strategy

    • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
    • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
    • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
    • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
    • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
    • MPEP § 1214.07: Reopening prosecution after appeal

    Important Disclaimer

    Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

    No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

    Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

    Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.