USPTO Examiner SIDDIQUE MUSHFIQUE - Art Unit 2825

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18662806NON-VOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) WITH MULTIPLE MAGNETIC TUNNEL JUNCTION CELLSMay 2024April 2025Allow1110NoNo
18661902MEMORY SELECTOR THRESHOLD VOLTAGE RECOVERYMay 2024April 2025Allow1110NoNo
18636569MEMORY DEVICE AND PROGRAM OPERATION THEREOFApril 2024June 2025Allow1410YesNo
18635365SEMICONDUCTOR DEVICE STRUCTURE HAVING FUSE ELEMENTSApril 2024February 2025Allow1020NoNo
18415023Integrated AssembliesJanuary 2024June 2025Allow1730NoNo
18412873CURRENT CONTROL CIRCUIT AND DISCHARGE ENABLE CIRCUIT FOR DISCHARGING BIT LINES OF MEMORY DEVICE AND OPERATION METHOD THEREOFJanuary 2024November 2024Allow1010YesNo
18535647MEMORY DEVICE FOR PERFORMING SMART REFRESH OPERATION AND METHOD OF REDUCING POWER CONSUMPTION DURING REFRESHDecember 2023June 2025Allow1810NoNo
18513328MEMORY DEVICE CAPABLE OF ADJUSTING CLOCK SIGNAL BASED ON OPERATING SPEED AND PROPAGATION DELAY OF COMMAND/ADDRESS SIGNALNovember 2023May 2025Allow1820NoNo
18509485CLOCK SYSTEM AND MEMORYNovember 2023April 2024Allow510NoNo
18480305SEMICONDUCTOR STORAGE DEVICEOctober 2023August 2024Allow1110NoNo
18239140SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUITAugust 2023September 2024Allow1310NoNo
18365317MEMORY DEVICE WITH ERROR PER ROW COUNTER (EPRC) PERFORMING ERROR CHECK AND SCRUB (ECS)August 2023February 2024Allow620NoNo
18361559SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY PROGRAMJuly 2023June 2025Allow2240YesNo
18226096SEMICONDUCTOR ELEMENT MEMORY DEVICEJuly 2023June 2025Allow2300NoNo
18347571IN MEMORY SEARCHING DEVICEJuly 2023June 2025Allow2310YesNo
18218243QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAMEJuly 2023April 2024Allow910NoNo
18217205SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXINGJune 2023April 2024Allow1010NoNo
18340726Memory System Topologies Including A Memory Die StackJune 2023May 2025Allow2230NoNo
18336418SRAM WITH TRACKING CIRCUITRY FOR REDUCING ACTIVE POWERJune 2023September 2024Allow1520YesNo
18313948MEMORY SUBWORD DRIVER CIRCUITS AND LAYOUTMay 2023September 2024Allow1610NoNo
18139316METHOD OF REDUCING PROGRAM DISTURBANCE IN MEMORY DEVICE AND MEMORY DEVICE UTILIZING SAMEApril 2023May 2025Allow2510YesNo
18138849MEMORY DEVICE FOR REDUCING ROW HAMMER DISTURBANCE, AND A METHOD OF REFRESHING THE SAMEApril 2023February 2024Allow1010NoNo
18303522MEMORY DEVICES HAVING SENSE AMPLIFIERS THEREIN THAT SUPPORT OFFSET CANCELLATION HAVING IMPROVED SENSE AMPLIFIER CHARACTERISTICS AND METHODS OF OPERATING SAMEApril 2023July 2025Allow2610YesNo
18300706NON-VOLATILE STATIC RANDOM ACCESS MEMORY (nvSRAM) WITH MULTIPLE MAGNETIC TUNNEL JUNCTION CELLSApril 2023January 2024Allow910NoNo
18299363SEMICONDUCTOR-ELEMENT-INCLUDING MEMORY DEVICEApril 2023January 2025Allow2200NoNo
18184329SEMICONDUCTOR STORAGE DEVICE INCLUDING SENSE AMPLIFIER THAT SENSES DATA FROM MULTIPLE MEMORY CIRCUITSMarch 2023March 2025Allow2410NoNo
18120136VARYING A TIME AVERAGE FOR FEEDBACK OF A MEMORY SYSTEMMarch 2023December 2023Allow910NoNo
18182305MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGESMarch 2023February 2024Allow1120NoNo
18180117MEMORY DEVICE WITH SINGLE-TRANSISTOR DRAM CELLS WITH NO CAPACITORS, AND MEMORY CELLS STACKED IN THE VERTICAL DIRECTION USING GATE-ALL-AROUND (GAA) TECHNOLOGYMarch 2023February 2025Allow2410NoNo
18178915MEMORY DEVICE AND SENSE AMPLIFIER CAPABLE OF PERFORMING IN-MEMORY LOGICAL NOT OPERATION AND COMPUTINGMarch 2023February 2025Allow2310NoNo
18174186SEMICONDUCTOR MEMORY DEVICE INCLUDING AN ON-DIE ECC ENGINEFebruary 2023April 2025Allow2510YesNo
18172136MEMORY DEVICE WITH VERTICAL PILLAR SHAPED CELLS AND SGT STRUCTUREFebruary 2023January 2025Allow2310NoNo
18164199SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOFFebruary 2023September 2023Allow710NoNo
18105442APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICESFebruary 2023October 2023Allow810YesNo
18104069DATA DESTRUCTIONJanuary 2023October 2023Allow810NoNo
18103226METHOD FOR CHECKING THE ERASING PHASE OF A MEMORY DEVICEJanuary 2023September 2023Allow710YesNo
18100969TEST CIRCUIT FOR DETECTING WORD LINE DEFECT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAMEJanuary 2023December 2024Allow2310NoNo
18099386MEMORY DEVICE FOR SUPPRESSING HOT CARRIER INJECTION AND METHOD OF OPERATING THE SAMEJanuary 2023May 2025Allow2811NoNo
18153464BIT LINE LOGIC CIRCUITS AND METHODSJanuary 2023January 2024Allow1210NoNo
18095646READ-TIME OVERHEAD AND POWER OPTIMIZATIONS WITH COMMAND QUEUES IN MEMORY DEVICEJanuary 2023October 2023Allow910NoNo
18151459MEMORY CIRCUIT, SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION METHODJanuary 2023January 2025Allow2510NoNo
18064859Four-Poly-Pitch Sram Cell With Backside Metal TracksDecember 2022March 2024Allow1510YesNo
18075570PERFORMING REFRESH OPERATIONS ON MEMORY CELLSDecember 2022November 2023Allow1220YesNo
17992651MEMORY DEVICE CAPABLE OF ADJUSTING CLOCK SIGNAL BASED ON OPERATING SPEED AND PROPAGATION DELAY OF COMMAND/ADDRESS SIGNALNovember 2022July 2023Allow810NoNo
17999234A SEMICONDUCTOR STORAGE WITH TWO POWER SOURCE PATHSNovember 2022October 2024Allow2310NoNo
17986652RESISTIVE RANDOM-ACCESS MEMORY FOR EXCLUSIVE NOR (XNOR) NEURAL NETWORKSNovember 2022September 2023Abandon1010NoNo
17998782TWO-DIMENSIONAL MATERIAL-BASED SELECTOR WITH STACK UNIT, MEMORY UNIT, ARRAY, AND METHOD OF OPERATING THE SAMENovember 2022February 2025Allow2710NoNo
17986556STORAGE DEVICE AND STORAGE SYSTEM INCLUDING PUFNovember 2022March 2025Allow2820YesNo
17982382SYSTEMS AND METHODS FOR A COMPRESSED BITCELL READ-ONLY MEMORYNovember 2022October 2024Allow2310NoNo
17979591SIGNAL GENERATOR FOR GENERATING CONTROL SIGNALS FOR PAGE BUFFER OF MEMORY DEVICENovember 2022May 2023Allow710NoNo
18051719MAGNETIC DOMAIN WALL-BASED MEMORY DEVICE WITH TRACK-CROSSING ARCHITECTURENovember 2022February 2025Allow2710NoNo
17974852APPARATUS AND METHOD WITH IN-MEMORY DELAY DEPENDENT PROCESSINGOctober 2022May 2023Allow710NoNo
18049855DIRTY WRITE ON POWER OFFOctober 2022October 2023Allow1210NoNo
17971340STABILIZATION OF SELECTOR DEVICES IN A MEMORY ARRAYOctober 2022November 2023Allow1310NoNo
17970212SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAMEOctober 2022February 2025Allow2820NoNo
17970103MEMORY SYSTEM AND APPARATUS FOR EVICTING COLD DATA FROM VOLATILE MEMORY AND STORING THE EVICTED COLD DATA INTO THE NON-VOLATILE MEMORYOctober 2022December 2024Allow2610NoNo
18045846SENSE AMPLIFIER CIRCUIT WITH PRECHARGE, MEMORY DEVICE INCLUDING THE SAME AND SENSING METHOD OF MEMORY DEVICEOctober 2022November 2024Allow2520YesNo
18045590SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ADJUSTING OPERATION CONDITION OF THE SAMEOctober 2022January 2025Allow2711YesNo
17960660RESISTIVE RANDOM ACCESS MEMORY DEVICE WITH THREE-DIMENSIONAL CROSS-POINT STRUCTURE AND METHOD OF OPERATING THE SAMEOctober 2022January 2024Allow1530NoNo
17960346NON-VOLATILE MEMORY DEVICE USING CENTER DUMMY LINE TRANSISTOR FOR INCREASING BOOSTING EFFICIENCY AND PROGRAMMING METHOD THEREOFOctober 2022September 2024Allow2310YesNo
17960139COMPUTER SYSTEM, MEMORY DEVICE FORMED ON A WAFER ON WAFER STACK IN THE COMPUTER SYSTEM AND MEMORY CONTROL METHOD APPLIED TO THE COMPUTER SYSTEM BASED ON WAFER-ON-WAFER ARCHITECTUREOctober 2022October 2024Allow2510YesNo
17953329INPUT BUFFER CIRCUIT AND SEMICONDUCTOR MEMORYSeptember 2022September 2024Allow2310NoNo
17954176APPARATUSES AND METHODS TO DEPRIORITIZE TRAFFIC TO UNAVAILABLE MEMORY BANKSSeptember 2022May 2025Allow3230NoNo
17931457MEMORY SUBWORD DRIVER CIRCUITS WITH COMMON TRANSISTORS AT WORD LINESSeptember 2022December 2023Allow1520NoNo
17939594DETERMINING THRESHOLD VALUES FOR VOLTAGE DISTRIBUTION METRICSSeptember 2022April 2023Allow810NoNo
17903052MULTI-CHANNEL MEMORY DEVICE CAPABLE OF SWITCHING REDUNDANCY MEMORY BLOCKS TO REPLACE FAILED MEMORY BLOCKSeptember 2022August 2024Allow2310NoNo
17903390ROBUSTNESS-AWARE NAND FLASH MANAGEMENTSeptember 2022July 2023Allow1110NoNo
17823674MIXED WRITE CURSOR FOR BLOCK STRIPE WRITINGAugust 2022June 2024Allow2200NoNo
17821783IN-MEMORY COMPUTING USING SOT-MRAMAugust 2022September 2024Allow2510NoNo
17821676MEMORY WITH PARALLEL MAIN AND TEST INTERFACESAugust 2022November 2024Allow2621NoNo
17821645STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYSAugust 2022August 2024Allow2411NoNo
17820906MEMORY DEVICE AND METHOD FOR OPERATING SELECTIVE ERASE SCHEMEAugust 2022May 2024Allow2110NoNo
17889183APPARATUSES AND METHODS FOR SKIPPING WORDLINE ACTIVATION OF DEFECTIVE MEMORY DURING REFRESH OPERATIONSAugust 2022September 2024Allow2540YesNo
17887985MEMORY SYSTEM AND NONVOLATILE MEMORY FOR IMPROVING RELIABILITY OF STORED DATA AND SHORTENING OPERATION TIMEAugust 2022November 2024Allow2710NoNo
17887226Integrated AssembliesAugust 2022November 2023Allow1530NoNo
17884053MEMORY DEVICE AND MEMORY SYSTEM WITH A SELF-REFRESH FUNCTIONAugust 2022July 2024Allow2310NoNo
17884261SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRYAugust 2022June 2024Allow2210NoNo
17883392TWO-STAGE VOLTAGE CALIBRATION UPON POWER-UP OF MEMORY DEVICEAugust 2022April 2024Allow2010YesNo
17874296FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLSJuly 2022June 2023Abandon1110NoNo
17868074TRIGGERING A REFRESH FOR NON-VOLATILE MEMORYJuly 2022May 2025Allow3421YesNo
17866558MEMORY ARRAY HAVING ERROR CHECKING AND CORRECTION CIRCUITJuly 2022October 2024Allow2710NoNo
17863556METHOD AND APPARATUS WITH FLASH MEMORY CONTROLJuly 2022March 2025Allow3320YesNo
17864237MEMORY SYSTEM CAPABLE OF COMPENSATING FOR KICKBACK NOISEJuly 2022March 2023Allow810YesNo
17862697MEMORY DEVICE AND OPERATING METHOD FOR PERFORMING PRE-PROGRAM OPERATION ON OVER-ERASURE CELLSJuly 2022May 2024Allow2210NoNo
17863092MEMORY DEVICES WITH IMPROVED BIT LINE LOADINGJuly 2022November 2024Allow2820YesNo
17862472STORAGE DEVICE AND METHOD OF DISCHARGING AN OPERATING VOLTAGEJuly 2022May 2024Allow2210YesNo
17862081SEMICONDUCTOR MEMORY DEVICE INCLUDING WORD LINE AND BIT LINEJuly 2022February 2023Allow810NoNo
17811153APPARATUSES AND METHODS FOR DETECTING ILLEGAL COMMANDS AND COMMAND SEQUENCESJuly 2022February 2023Allow810NoNo
17791176BLOCK-TO-BLOCK ISOLATION AND DEEP CONTACT USING PILLARS IN A MEMORY ARRAYJuly 2022June 2024Allow2310NoNo
17810777NONVOLATILE MEMORY DEVICES FOR REDUCING DEGRADATION DUE TO DIFFERENCE OF THRESHOLD VOLTAGE DISTRIBUTIONS BETWEEN OUTER CELLS AND INNER CELLSJuly 2022May 2024Allow2210YesNo
17854153LOCAL AMPLIFYING CIRCUIT, DATA READOUT METHOD AND MEMORYJune 2022June 2024Allow2310NoNo
17855094EFFICIENT AND LOW POWER REFERENCE VOLTAGE MIXINGJune 2022January 2025Allow3021YesNo
17844955ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)June 2022August 2024Allow2610NoNo
17845259MEMORY CONTROLLER PERFORMING TRAINING TO IMPROVE COMMUNICATION AND METHOD OF OPERATING THE SAMEJune 2022December 2024Allow3020YesNo
17807760METHOD AND APPARATUS FOR DETERMINING SENSE BOUNDARY OF SENSE AMPLIFIER, MEDIUM, AND DEVICEJune 2022June 2023Allow1210YesNo
17844434ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)June 2022March 2025Allow3331NoNo
17806630NAND FLASH PROGRAMMING AND METHOD OF APPLYING READ PULSE BEFORE END OF PROGRAMJune 2022August 2024Allow2620YesNo
17836296READOUT CIRCUIT LAYOUT AND SENSE AMPLIFICATION CIRCUITJune 2022July 2024Allow2610NoNo
17835917OTP DEVICE WITH READ MODULE AND BIASING CIRCUITRY TO DETECT AND MEASURE ACCURATE BREAKDOWN STATES OF ANTI-FUSE MEMORY CELLSJune 2022April 2024Allow2210NoNo
17835912PRECHARGE CIRCUITRY FOR USE WITH BITLINESJune 2022May 2025Allow3540YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner SIDDIQUE, MUSHFIQUE.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
2
Examiner Affirmed
2
(100.0%)
Examiner Reversed
0
(0.0%)
Reversal Percentile
10.2%
Lower than average

What This Means

With a 0.0% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
10
Allowed After Appeal Filing
4
(40.0%)
Not Allowed After Appeal Filing
6
(60.0%)
Filing Benefit Percentile
63.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 40.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner SIDDIQUE, MUSHFIQUE - Prosecution Strategy Guide

Executive Summary

Examiner SIDDIQUE, MUSHFIQUE works in Art Unit 2825 and has examined 759 patent applications in our dataset. With an allowance rate of 89.6%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 20 months.

Allowance Patterns

Examiner SIDDIQUE, MUSHFIQUE's allowance rate of 89.6% places them in the 69% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by SIDDIQUE, MUSHFIQUE receive 1.88 office actions before reaching final disposition. This places the examiner in the 59% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by SIDDIQUE, MUSHFIQUE is 20 months. This places the examiner in the 89% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +7.3% benefit to allowance rate for applications examined by SIDDIQUE, MUSHFIQUE. This interview benefit is in the 37% percentile among all examiners. Recommendation: Interviews provide a below-average benefit with this examiner.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 34.7% of applications are subsequently allowed. This success rate is in the 72% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 43.1% of cases where such amendments are filed. This entry rate is in the 59% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 150.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 89% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences are highly effective with this examiner compared to others. Before filing a full appeal brief, strongly consider requesting a PAC. The PAC provides an opportunity for the examiner and supervisory personnel to reconsider the rejection before the case proceeds to the PTAB.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 80.0% of appeals filed. This is in the 69% percentile among all examiners. Of these withdrawals, 75.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 40.0% are granted (fully or in part). This grant rate is in the 39% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 22% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.0% of allowed cases (in the 28% percentile). This examiner issues Quayle actions less often than average. Allowances may come directly without a separate action for formal matters.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Request pre-appeal conferences: PACs are highly effective with this examiner. Before filing a full appeal brief, request a PAC to potentially resolve issues without full PTAB review.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.