USPTO Art Unit 2111 Prosecution Statistics

Art Unit Information

Art Unit: 2111
Group: 2110
Tech Center: 2100
Total Cases: 11,763
Last Active: November 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18864841OPTIMIZATION OF THE COMPUTATION OF PARITY CHECK MESSAGES IN A MIN-SUM LDPC DECODING METHODNovember 2024March 2025Allow400YesNo
18864829STOP CRITERION FOR DECODING AN LDPC CODENovember 2024April 2025Allow500YesNo
18900854UNIVERSAL TEST CHIPLETSeptember 2024February 2025Allow410NoNo
18771866SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAMEJuly 2024May 2025Allow1010YesNo
18770975MULTI-PORT MEDIA ACCESS CHANNEL (MAC) WITH FLEXIBLE DATA-PATH WIDTHJuly 2024March 2025Allow800NoNo
18769924MANAGEMENT OF MESSAGE TRANSMISSION USING FORWARD ERROR CORRECTIONJuly 2024May 2025Allow1010NoNo
18768178MEMORY SYSTEMJuly 2024May 2025Allow1010NoNo
18757268Energy-Efficient Error-Correction-Detection StorageJune 2024June 2025Allow1110NoNo
18754683INTEGRATED CIRCUIT DIE TEST ARCHITECTUREJune 2024January 2025Allow700NoNo
18752634A Scannable Memory Array and A Method for Scanning MemoryJune 2024November 2024Allow410YesNo
18740683TRANSMISSION SIDE TRANSMISSION DEVICE AND REDUNDANCY METHOD OF TRANSMISSION SIDE TRANSMISSION DEVICEJune 2024April 2025Allow1010NoNo
18735554PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAMEJune 2024March 2025Allow1010NoNo
18680660BANDWIDTH UTILIZATION TECHNIQUES FOR IN-BAND REDUNDANT DATAMay 2024April 2025Allow1100NoNo
18673628HANDLING NON-CORRECTABLE ERRORSMay 2024March 2025Allow1010YesNo
18671394ELECTRONIC DEVICE WITH ERASURE CODING ACCELERATION FOR DISTRIBUTED FILE SYSTEMS AND OPERATING METHOD THEREOFMay 2024April 2025Allow1110NoNo
18710586HYPER FRAME NUMBER (HFN) RESYNCHRONIZATION OF PACKET DATA CONVERGENCE PROTOCOL (PDCP) PROTOCOL DATA UNITSMay 2024July 2025Allow1400NoNo
18663701METHODS, DEVICES, AND MEDIUM FOR COMMUNICATIONMay 2024April 2025Allow1110NoNo
18660954MEMORY BANK PROTECTIONMay 2024April 2025Allow1110NoNo
18661526TEMPERATURE SENSOR MANAGEMENT DURING ERROR HANDLING OPERATIONS IN A MEMORY SUB-SYSTEMMay 2024June 2025Allow1300NoNo
18659942LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAMEMay 2024July 2025Allow1400NoNo
18660055VARIABLE CONFIGURATIONS OF NFRP RU TONE SETS IN WIRELESS NETWORKSMay 2024May 2025Allow1210NoNo
18656177TECHNIQUES FOR RETIRING BLOCKS OF A MEMORY SYSTEMMay 2024March 2025Allow1110NoNo
18654208SYSTEMS AND METHODS FOR COMPRESSED SENSING MEASUREMENT OF LONG-RANGE CORRELATED NOISEMay 2024January 2025Allow810YesNo
18652714METHODS FOR ERROR COUNT REPORTING WITH SCALED ERROR COUNT INFORMATION, AND MEMORY DEVICES EMPLOYING THE SAMEMay 2024June 2025Allow1310NoNo
18651185Data Processing Method and DeviceApril 2024May 2025Allow1310NoNo
18649379CODING METHOD, DECODING METHOD, AND COMMUNICATIONS APPARATUSApril 2024June 2025Allow1300NoNo
18649031ENERGY EFFICIENT STORAGE OF ERROR-CORRECTION-DETECTION INFORMATIONApril 2024February 2025Allow1010NoNo
18645817POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALINGApril 2024November 2024Allow700NoNo
18644084GENERATING A TARGET DATA BASED ON A FUNCTION ASSOCIATED WITH A PHYSICAL VARIATION OF A DEVICEApril 2024May 2025Allow1310NoNo
18641983INTERACTIVE DRAM SIGNAL ANALYZER AND METHOD OF ANALYZING AND CALIBRATING DRAM SIGNAL USING THE SAMEApril 2024March 2025Allow1120NoNo
18641942SOLID-STATE DRIVE WITH MULTIMODE COMPRESSION AND ERROR CORRECTIONApril 2024May 2025Allow1300NoNo
18640651BIT RETIRING TO MITIGATE BIT ERRORSApril 2024December 2024Allow800NoNo
18637901TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENTApril 2024May 2025Allow1320NoNo
18629536RATE MATCHING METHOD AND APPARATUS FOR POLAR CODEApril 2024May 2025Allow1310NoNo
18628831DATA STORAGE DEVICE AND SEARCHING METHOD FOR READING VOLTAGE THEREOFApril 2024May 2025Allow1300NoNo
18621069METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICEMarch 2024June 2025Allow1400NoNo
18618965ON-SSD ERASURE CODING WITH UNI-DIRECTIONAL COMMANDSMarch 2024June 2025Allow1520YesNo
18617433METHOD FOR POLAR CODE DESIGN WITH PARITY CHECK BITSMarch 2024May 2025Allow1400NoNo
18617114BASE STATION, TERMINAL, AND COMMUNICATION METHODMarch 2024April 2025Allow1210NoNo
18612919Threshold-Based Min-Sum Algorithm to Lower the Error Floors of Quantized Low-Density Parity-Check DecodersMarch 2024April 2025Allow1310YesNo
18612251RESET FOR SCAN MODE EXIT FOR DEVICES WITH POWER-ON RESET GENERATION CIRCUITRYMarch 2024May 2025Allow1400NoNo
18609417ITERATIVE ERROR CORRECTION IN MEMORY SYSTEMSMarch 2024October 2024Allow710NoNo
18607152MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATIONMarch 2024June 2025Allow1500NoNo
18605685Memory with Scan Chain Testing of Column Redundancy Logic and MultiplexingMarch 2024March 2025Allow1210NoNo
18604227ERROR CORRECTION MEMORY DEVICE WITH FAST DATA ACCESSMarch 2024March 2025Allow1210NoNo
18602031CONTROLLER AND MEMORY SYSTEMMarch 2024May 2025Allow1400NoNo
18598899APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAMEMarch 2024June 2025Allow1510NoNo
18597454TOPOLOGY-BASED RETIREMENT IN A MEMORY SYSTEMMarch 2024April 2025Allow1420YesNo
18594878CYCLIC REDUNDANCY CHECK SYSTEM AND CYCLIC REDUNDANCY CHECK METHODMarch 2024April 2025Allow1400NoNo
18592287SELF-FUNCTIONAL DETECTION SYSTEM FOR TAP CONTROLLER AND METHOD THEREOFFebruary 2024May 2025Allow1500NoNo
18590671TECHNIQUES FOR INDICATING A WRITE LINK ERRORFebruary 2024April 2025Allow1320YesNo
18588819CHECKING DATA INTEGRITY BY COMPARING ERROR-CHECK SIGNALS GENERATING ON DIFFERENT CLOCKS CYCLESFebruary 2024June 2025Allow1600NoNo
18584385MEMORY DIE FAULT DETECTION USING A CALIBRATION PINFebruary 2024May 2025Allow1400NoNo
18444482APPARATUSES AND METHODS FOR VARIABLE INPUT ECC CIRCUITSFebruary 2024June 2025Allow1600YesNo
18444320MEMORY DEVICE AND REPAIR METHOD WITH COLUMN-BASED ERROR CODE TRACKINGFebruary 2024December 2024Allow1010NoNo
18439236QUANTUM SYSTEM CONTROLLER CONFIGURED FOR QUANTUM ERROR CORRECTIONFebruary 2024October 2024Allow800NoNo
18438993TEST SYSTEMFebruary 2024June 2025Allow1610YesNo
18435652DYNAMIC CONTROL OF ERROR MANAGEMENT AND SIGNALINGFebruary 2024January 2025Allow1110NoNo
18431279REDUCING READ ERROR HANDLING OPERATIONS DURING POWER UP OF A MEMORY DEVICEFebruary 2024June 2025Allow1710YesNo
18428471Configurable Testing and Repair System for Non-Volatile MemoryJanuary 2024February 2025Allow1300NoNo
18423107SYSTEMS AND METHODS FOR REDUCING ERROR LOG REQUIRED SPACE IN SEMICONDUCTOR TESTINGJanuary 2024April 2025Allow1510YesNo
18420877ELECTRONIC DEVICES AND METHODS OF OPERATING THE SAMEJanuary 2024April 2025Allow1500NoNo
18421304METHODS AND SYSTEMS FOR DATA TRANSMISSIONJanuary 2024August 2024Allow700YesNo
18421389SELECTIVELY USING HEROIC DATA RECOVERY METHODS IN A MEMORY DEVICEJanuary 2024February 2025Allow1310NoNo
18420849STORAGE DEVICE INCLUDING A READ RECLAIM MODULE AND A RECLAIM OPERATION METHOD THEREOFJanuary 2024June 2025Allow1600NoNo
18420486INFRASTRUCTURE BACKUP AND RECOVERYJanuary 2024October 2024Allow800NoNo
18419432MAGNETIC REPRODUCING PROCESSING DEVICE, MAGNETIC RECORDING/REPRODUCING DEVICE AND MAGNETIC REPRODUCING METHODJanuary 2024March 2025Allow1400NoNo
18418348LOW-DENSITY PARITY-CHECK (LDPC) DATA DECODING USING ITERATION-VARIABLE ACCURACYJanuary 2024June 2025Allow1710YesNo
18416967DATA RECOVERY USING ORDERED DATA REQUESTSJanuary 2024December 2024Allow1110NoNo
18417517DYNAMIC WORD LINE ALLOCATION IN MEMORY SYSTEMSJanuary 2024June 2025Allow1710NoNo
18415672CLOCK CONTROL CIRCUIT AND METHODJanuary 2024April 2025Allow1400NoNo
18415632BURST CORRECTION REED SOLOMON DECODING FOR MEMORY APPLICATIONSJanuary 2024January 2025Allow1200NoNo
18415634DECODER FOR BURST CORRECTION READ SOLOMON DECODING FOR MEMORY APPLICATIONSJanuary 2024May 2025Allow1610NoNo
18415631DECODER FOR INTERLEAVED REED-SOLOMON (IRS) WITH ERASURE/COLLABORATIVEJanuary 2024March 2025Allow1400NoNo
18410939MIN-SUM DECODING FOR IRREGULAR LOW-DENSITY PARITY CHECK CODES IN MEMORY DEVICESJanuary 2024February 2025Allow1300NoNo
18576756TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHODJanuary 2024January 2025Allow1300NoNo
18406067SAVING AND RESTORING SCAN STATESJanuary 2024February 2025Allow1400NoNo
18403019IN-MEMORY READ THRESHOLD ADAPTATIONJanuary 2024June 2025Allow1810NoNo
18403623SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITSJanuary 2024March 2025Allow1500YesNo
18399864MEMORY DEVICE AND OPERATION METHOD THEREOFDecember 2023June 2025Allow1710YesNo
18400256STORAGE DEVICE AND OPERATING METHOD OF STORAGE CONTROLLERDecember 2023January 2025Allow1310YesNo
18398186Method And Apparatus For LDPC Code Construction In CommunicationsDecember 2023May 2025Allow1710NoNo
18397399TECHNIQUES FOR MANAGING MEMORY EXCEPTION HANDLINGDecember 2023January 2025Allow1300NoNo
18397612SYSTEM AND METHOD FOR DISTRIBUTION STORAGE OF BLOCKCHAIN TRANSACTION DATA BASED ON ERASURE CODEDecember 2023February 2025Allow1300NoNo
18397450CHANNEL MODULATION FOR A MEMORY DEVICEDecember 2023February 2025Allow1320NoNo
18397481Automatic Test Pattern Generation-Based Circuit Verification Method and ApparatusDecember 2023February 2025Allow1300NoNo
18393510APPARATUS, SYSTEMS, AND METHODS FOR DYNAMICALLY RECONFIGURED SEMICONDUCTOR TESTER FOR VOLATILE AND NON-VOLATILE MEMORIESDecember 2023June 2025Allow1810YesNo
18392740AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICESDecember 2023November 2024Allow1100NoNo
18544572MEMORY CHIPS AND OPERATING METHODS THEREOFDecember 2023April 2025Allow1600NoNo
18543790TECHNIQUES FOR CONTROLLING SMALL ANGLE M�LMER-S�RENSEN GATES AND FOR HANDLING ASYMMETRIC SPAM ERRORSDecember 2023February 2025Allow1410NoNo
18543737MEMORY SYSTEM, METHOD OF OPERATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAMEDecember 2023June 2025Allow1810YesNo
18541159SYSTEMS AND METHODS FOR QUANTUM-ENABLED ERROR CORRECTIONDecember 2023May 2025Allow1710NoNo
18540351ERRONEOUS BIT DISCOVERY IN MEMORY SYSTEMDecember 2023March 2025Allow1520YesNo
18538692DEVICE AND METHOD FOR PROVIDING PHYSICALLY UNCLONABLE FUNCTION WITH HIGH RELIABILITYDecember 2023April 2025Allow1610YesNo
18537401MEMORY DEVICE PPR FAILURE HANDLING SYSTEMDecember 2023April 2025Allow1600NoNo
18536011LOWER-BOUNDING DISTANCE OF STABILIZER CHANNEL SEQUENCEDecember 2023March 2025Allow1500NoNo
18536051Identifying Severe Hook Faults of Stabilizer ChannelDecember 2023June 2025Allow1810YesNo
18534727ELECTRONIC FUSE DEVICE AND OPERATION METHOD THEREOFDecember 2023April 2025Allow1610NoNo
18533655MINIMIZING REDUNDANCY FOR STUCK BIT CODINGDecember 2023March 2025Allow1600NoNo
18531061METHOD AND APPARATUS FOR EFFICIENTLY UTILIZING HARQ PROCESSES FOR SEMI-PERSISTENT AND DYNAMIC DATA TRANSMISSIONSDecember 2023January 2025Allow1310YesNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2111.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
202
Examiner Affirmed
151
(74.8%)
Examiner Reversed
51
(25.2%)
Reversal Percentile
15.3%
Lower than average

What This Means

With a 25.2% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
630
Allowed After Appeal Filing
214
(34.0%)
Not Allowed After Appeal Filing
416
(66.0%)
Filing Benefit Percentile
55.6%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 34.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2111 - Prosecution Statistics Summary

Executive Summary

Art Unit 2111 is part of Group 2110 in Technology Center 2100. This art unit has examined 11,763 patent applications in our dataset, with an overall allowance rate of 84.3%. Applications typically reach final disposition in approximately 27 months.

Comparative Analysis

Art Unit 2111's allowance rate of 84.3% places it in the 77% percentile among all USPTO art units. This art unit has a significantly higher allowance rate than most art units at the USPTO.

Prosecution Patterns

Applications in Art Unit 2111 receive an average of 1.63 office actions before reaching final disposition (in the 33% percentile). The median prosecution time is 27 months (in the 60% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.