USPTO Art Unit 2111 Prosecution Statistics

Art Unit Information

Art Unit: 2111
Group: 2110
Tech Center: 2100
Total Cases: 11,511
Last Active: August 2025

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
19298065METHOD AND SYSTEM FOR PERFORMING TRANSFER FUNCTION MEASUREMENTS ON A DEVICEAugust 2025October 2025Allow200NoNo
19258231Quantum Redundancy and AI-Enhanced Cybersecurity MethodJuly 2025November 2025Allow410NoNo
19139196Memory Processing Method Based on a Server and Apparatus, Processor and Electronic DeviceJune 2025February 2026Allow800NoNo
19048535Anti-Fragile Storage SystemsFebruary 2025April 2025Allow200NoNo
19044864QUANTUM ERROR CORRECTION WITH RUNTIME TRIGGER EVENTSFebruary 2025August 2025Allow610YesNo
18872721GRAY MAPPING FOR VARIABLE-TO-FIXED DISTRIBUTION MATCHINGDecember 2024March 2026Allow1500NoNo
18864841OPTIMIZATION OF THE COMPUTATION OF PARITY CHECK MESSAGES IN A MIN-SUM LDPC DECODING METHODNovember 2024March 2025Allow400YesNo
18864829STOP CRITERION FOR DECODING AN LDPC CODENovember 2024April 2025Allow500YesNo
18939967ELECTRONIC DEVICENovember 2024March 2026Allow1600NoNo
18920941FLASH MEMORY CONTROLLER AND FLASH MEMORY ACCESS METHODOctober 2024February 2026Allow1500NoNo
18916809OpenFEC error markingOctober 2024February 2026Allow1600NoNo
18908311CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONSOctober 2024February 2026Allow1600NoNo
18900854UNIVERSAL TEST CHIPLETSeptember 2024February 2025Allow410NoNo
18899981TESTER CHANNEL MULTIPLEXING IN TEST EQUIPMENTSeptember 2024December 2025Allow1500NoNo
18891216METHOD FOR ENCODED DIAGNOSTICS IN A FUNCTIONAL SAFETY SYSTEMSeptember 2024February 2026Allow1700NoNo
18886878DATA INTEGRITY VERIFICATION FOR NETWORK FILE SYSTEMSSeptember 2024January 2026Allow1600NoNo
18882713METHOD AND APPARATUS FOR PERFORMING DATA ACCESS CONTROL OF MEMORY DEVICESeptember 2024December 2025Allow1500NoNo
18830204DEVICE DATA PATH MONITORSeptember 2024March 2026Allow1810YesNo
18816685REAL-TIME DEBUG IN LOW-POWER DEVICESAugust 2024February 2026Allow1700NoNo
18813896ERROR CORRECTIONAugust 2024February 2026Allow1810NoNo
18808433RECOVERING DATA FROM DE-SEQUENCED ENCODED DATA SLICESAugust 2024March 2026Allow1910YesNo
18804352MEMORY SYSTEM SUPPORTING MULTI-CHANNEL INTERFACEAugust 2024March 2026Allow1910YesNo
18798321PROCESSOR-BASED SYSTEM SUPPORTING IN-FIELD TESTING USING EXTERNAL DYNAMIC RANDOM ACCESS MEMORY (DRAM) FOR STORING AND ACCESSING TEST SCAN DATAAugust 2024November 2025Allow1500NoNo
18798499MEMORY DEVICE DETECTING FAIL OF THROUGH-SILICON VIAAugust 2024December 2025Allow1600YesNo
18798040MEMORY SYSTEMAugust 2024December 2025Allow1600NoNo
18791443TESTING METHOD AND TESTING SYSTEMAugust 2024January 2026Allow1700YesNo
18792138JTAG-BASED APPARATUS AND METHOD FOR INPUT CLOCK FREQUENCY MEASUREMENTAugust 2024November 2025Allow1600NoNo
18791155SYSTEM FOR HANDLING REPEATED PROGRAMMING ERRORSJuly 2024November 2025Allow1600NoNo
18790407METHODS AND SYSTEM WITH DYNAMIC ECC VOLTAGE AND FREQUENCYJuly 2024January 2026Allow1710NoNo
18789454STORING STATUS INFORMATION USING REDUNDANT COLUMNSJuly 2024January 2026Allow1800NoNo
18788635MACHINE-LEARNING-BASED SYSTEM HEALTH MONITORING OF A MEMORY DEVICEJuly 2024November 2025Allow1500NoNo
18789557METHOD OF TESTING A MEMORY CIRCUIT AND MEMORY CIRCUITJuly 2024January 2026Allow1810NoNo
18789201SEMICONDUCTOR MEMORY DEVICE-DIRECTED ERROR CHECK AND SCRUBJuly 2024January 2026Allow1800YesNo
18787949APPARATUSES AND METHODS FOR DISTRIBUTING AND PROVIDING DATA PROTECTION FOR AUXILIARY DATAJuly 2024October 2025Allow1400NoNo
18787270DEEP NEURAL NETWORK IMPLEMENTATION FOR SOFT DECODING OF BCH CODEJuly 2024March 2026Allow2010YesNo
18786481MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICEJuly 2024October 2025Allow1400NoNo
18785170Test Data Transfer in Multi-Die SystemsJuly 2024September 2025Allow1400NoNo
18783136NON-VOLATILE MEMORY AND REWRITE CONTROL METHOD THEREOFJuly 2024October 2025Allow1500NoNo
18783001ERROR DECODING WITH ITERATIVE PARAMETER UPDATINGJuly 2024March 2026Allow2010YesNo
18782806SYSTEMS AND METHODS FOR PROBABILISTIC QUADRATURE AMPLITUDE MODULATION (QAM)July 2024November 2025Allow1600NoNo
18781064CORRECTING LATCH UPSET EVENTS IN A TRIM REGISTERJuly 2024January 2026Allow1810YesNo
18779811BIN-BASED READ ERROR HANDLING FLOWS USING A FAST CORRECTIVE READ OPERATIONJuly 2024February 2026Allow1910YesNo
18779058POLAR CODE ENCODING METHOD, POLAR CODE DECODING METHOD, AND APPARATUSES THEREOFJuly 2024March 2026Allow1910NoNo
18776478AUTOMOTIVE TOUCH CIRCUIT DEVICE WITH ESD PROTECTIONJuly 2024November 2025Allow1600NoNo
18775804LOCKED RAID MEMORY DEVICESJuly 2024February 2026Allow1910NoNo
18775848READ THRESHOLD MANAGEMENT USING PAGE TYPEJuly 2024March 2026Allow2010NoNo
18729195MEMORY BUILT-IN SELF-TEST WITH ADDRESS SKIPPING TRIM SEARCHJuly 2024September 2025Allow1400NoNo
18774464PAGE-BY-PAGE LEVEL SHAPINGJuly 2024March 2026Allow2010NoNo
18774452INDICATING DATA CORRUPTIONJuly 2024February 2026Allow1910YesNo
18774652CORRECTION MATRIX RESETJuly 2024February 2026Allow1910YesNo
18774787SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMSJuly 2024January 2026Allow1810NoNo
18772997BASE STATION, TERMINAL AND COMMUNICATION METHODJuly 2024January 2026Allow1810NoNo
18772604METHOD AND SYSTEM FOR ON-ASIC ERROR CONTROL ENCODINGJuly 2024October 2025Allow1510NoNo
18773006RANDOM ACCESS MEMORY AND CORRESPONDING METHOD FOR MANAGING A RANDOM ACCESS MEMORYJuly 2024February 2026Allow1910NoNo
18771866SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAMEJuly 2024May 2025Allow1010YesNo
18771392ERROR CORRECTION CIRCUITJuly 2024February 2026Allow1910YesNo
18771829VALLEY SEARCH IN READ ERROR RECOVERY FOR A MEMORY DEVICE USING LOW-DENSITY PARITY CHECK SYNDROME WEIGHT AND AUTO-READ CALIBRATIONJuly 2024February 2026Allow1910NoNo
18770975MULTI-PORT MEDIA ACCESS CHANNEL (MAC) WITH FLEXIBLE DATA-PATH WIDTHJuly 2024March 2025Allow800NoNo
18771080ERROR DETECTION AND CHECKING IN WIRELESS COMMUNICATION SYSTEMSJuly 2024October 2025Allow1510NoNo
18770809Scan Flip-Flops With Pre-Setting Combinational LogicJuly 2024January 2026Allow1810NoNo
18770435SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOFJuly 2024September 2025Allow1400NoNo
18769924MANAGEMENT OF MESSAGE TRANSMISSION USING FORWARD ERROR CORRECTIONJuly 2024May 2025Allow1010NoNo
18768178MEMORY SYSTEMJuly 2024May 2025Allow1010NoNo
18768011DATA CHECK METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNITJuly 2024February 2026Allow1910NoNo
18767098MULTI-LEVEL CELL DATA ENCODINGJuly 2024January 2026Allow1810NoNo
18766219DETECTING ERRORS WITHIN DATA PATH CIRCUITRY OF A MEMORY DEVICEJuly 2024March 2026Allow2010YesNo
18764870MEMORY DEVICE AND A METHOD OF OPERATING THE SAME DEVICEJuly 2024February 2026Allow1910YesNo
18726670HIGH-THROUGHPUT SCAN ARCHITECTUREJuly 2024January 2026Allow1910NoNo
18762642MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAMEJuly 2024November 2025Allow1621NoNo
18761586COMPUTE-IN-MEMORY USING NEURAL NETWORKS STORED IN A NON-VOLATILE MEMORY FOR PREDICTIVE BLOCK HEALTH ASSESSMENT OF THE NON-VOLATILE MEMORYJuly 2024February 2026Allow1900NoNo
18761725MEMORY SYSTEM AND METHODJuly 2024September 2025Allow1400NoNo
18761045METHODS AND SYSTEMS FOR SLC COPYBACK OPERATIONSJuly 2024September 2025Allow1400NoNo
18758583NON-VOLATILE STORAGE DEVICE OFFLOADING IN A MULTI-DATA NODE ENVIRONMENTJune 2024January 2026Allow1910YesNo
18758495NON-VOLATILE STORAGE DEVICE OFFLOADINGJune 2024September 2025Allow1500NoNo
18725676MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFERJune 2024February 2026Allow1910NoNo
18755800SCAN TEST IN A SINGLE-WIRE BUS CIRCUITJune 2024July 2025Allow1310NoNo
18757268Energy-Efficient Error-Correction-Detection StorageJune 2024June 2025Allow1110NoNo
18754683INTEGRATED CIRCUIT DIE TEST ARCHITECTUREJune 2024January 2025Allow700NoNo
18753410MEMORY CONTROLLER MANAGING READ LEVEL INFORMATION, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY CONTROLLERJune 2024August 2025Allow1300NoNo
18752645Hybrid Scan Chains with Flip-flops and LatchesJune 2024March 2026Allow2110YesNo
18752634A Scannable Memory Array and A Method for Scanning MemoryJune 2024November 2024Allow410YesNo
18750192SENDING METHOD, RECEIVING METHOD, APPARATUS, SYSTEM, DEVICE, AND STORAGE MEDIUMJune 2024February 2026Allow2010NoNo
18749984METHOD FOR ACCESSING A DATA BLOCK, STORED IN A MEMORY UNIT OF A COMPUTING UNIT, OF A NUMBER OF DATA BLOCKSJune 2024August 2025Allow1400NoNo
18749644COUNTING CIRCUIT, SEMICONDUCTOR MEMORY, AND COUNTING METHODJune 2024February 2026Allow1910NoNo
18749823METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORSJune 2024January 2026Allow1900NoNo
18747676APPARATUSES AND METHODS FOR ALTERNATE MEMORY DIE METADATA STORAGEJune 2024January 2026Allow1910NoNo
18747877DATA PROCESSING APPARATUS, MEMORY FAILURE DETERMINATION METHOD, AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUMJune 2024January 2026Allow1910YesNo
18743554MEMORY CONTROLLER AND MEMORY SYSTEMJune 2024December 2025Allow1810NoNo
18743994APPARATUSES AND METHODS FOR SHARED CODEWORD IN 2-PASS ACCESS OPERATIONSJune 2024December 2025Allow1800YesNo
18742891METHOD AND SYSTEM FOR CONTEXT-BASED RETRANSMISSION OF LOST PACKETSJune 2024September 2025Allow1500NoNo
18742474SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING AN ELECTRONIC CIRCUITJune 2024November 2025Allow1820NoNo
18740683TRANSMISSION SIDE TRANSMISSION DEVICE AND REDUNDANCY METHOD OF TRANSMISSION SIDE TRANSMISSION DEVICEJune 2024April 2025Allow1010NoNo
18740058NARX ARCHITECTURE FOR TASK CONTENTION MODELS USING TIME-SERIES AND FINE-GRAIN INSTRUMENTATION FOR MPSoCsJune 2024March 2026Allow2110YesNo
18740001STORAGE CLASS MEMORY, DATA PROCESSING METHOD, AND PROCESSOR SYSTEMJune 2024December 2025Allow1810NoNo
18740412INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTINGJune 2024March 2026Allow2110NoNo
18647867CENTRALIZED ERROR CORRECTION CIRCUITJune 2024September 2025Allow1610NoNo
18735483Data Error Correction Method and Apparatus, Memory Controller, and SystemJune 2024January 2026Allow2010NoNo
18735554PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAMEJune 2024March 2025Allow1010NoNo
18735981COMMAND ADDRESS FAULT DETECTIONJune 2024August 2025Allow1420YesNo
18735599TEST PATTERN RESET CONTROL CIRCUITJune 2024July 2025Allow1300NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2111.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
250
Examiner Affirmed
187
(74.8%)
Examiner Reversed
63
(25.2%)
Reversal Percentile
16.0%
Lower than average

What This Means

With a 25.2% reversal rate, the PTAB affirms the examiner's rejections in the vast majority of cases. This reversal rate is in the bottom 25% across the USPTO, indicating that appeals face significant challenges here.

Strategic Value of Filing an Appeal

Total Appeal Filings
731
Allowed After Appeal Filing
238
(32.6%)
Not Allowed After Appeal Filing
493
(67.4%)
Filing Benefit Percentile
51.8%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 32.6% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

⚠ Appeals to PTAB face challenges. Ensure your case has strong merit before committing to full Board review.

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Art Unit 2111 - Prosecution Statistics Summary

Executive Summary

Art Unit 2111 is part of Group 2110 in Technology Center 2100. This art unit has examined 11,511 patent applications in our dataset, with an overall allowance rate of 82.3%. Applications typically reach final disposition in approximately 28 months.

Comparative Analysis

Art Unit 2111's allowance rate of 82.3% places it in the 72% percentile among all USPTO art units. This art unit has an above-average allowance rate compared to other art units.

Prosecution Patterns

Applications in Art Unit 2111 receive an average of 1.74 office actions before reaching final disposition (in the 38% percentile). The median prosecution time is 28 months (in the 64% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more favorable examination environment compared to the USPTO average.
  • With fewer office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.