USPTO Examiner HOSSAIN SAZZAD - Art Unit 2111

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18421304METHODS AND SYSTEMS FOR DATA TRANSMISSIONJanuary 2024August 2024Allow700YesNo
18485303POLAR CODE ENCODING METHOD AND APPARATUS IN WIRELESS COMMUNICATIONSOctober 2023September 2024Allow1200YesNo
18231514BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONSAugust 2023November 2024Allow1510YesNo
18225841TRANSMITTER AND PUNCTURING METHOD THEREOFJuly 2023March 2024Allow800YesNo
18215588CACHE LINE DATA PROTECTIONJune 2023October 2024Allow1610YesNo
18303401Built-in Self-Test for Die-to-Die Physical InterfacesApril 2023November 2023Allow700YesNo
18129028MEMORY DEVICE WITH COMPRESSED SOFT INFORMATION AND ASSOCIATED CONTROL METHODMarch 2023November 2024Allow1910YesNo
18192272PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICEMarch 2023January 2024Allow1010YesNo
18179146INTEGRITY CHECK DEVICE FOR SAFETY SENSITIVE DATA AND ELECTRONIC DEVICE INCLUDING THE SAMEMarch 2023October 2024Allow1910YesNo
18154075QUANTUM CODE FOR REDUCED FREQUENCY COLLISIONS IN QUBIT LATTICESJanuary 2023June 2024Allow1720YesNo
18151219TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOFJanuary 2023June 2023Allow600YesNo
18149302MEMORY DEVICE FOR COLUMN REPAIRJanuary 2023September 2023Allow910YesNo
18066710TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOFDecember 2022September 2023Allow910YesNo
18051327ELECTRONIC DEVICE AND DATA TRANSMISSION METHOD THEREOFOctober 2022June 2024Abandon1910NoNo
18049775INTEGRATED CIRCUIT HAVING TEST CIRCUITRY FOR MEMORY SUB-SYSTEMSOctober 2022September 2024Allow2310NoNo
18049771ADAPTIVE READ RECOVERY FOR NAND FLASH MEMORY DEVICESOctober 2022June 2024Allow2010YesNo
17921131WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION METHODOctober 2022August 2024Allow2220NoNo
17953689EARLY DETECTION OF SINGLE BIT ERROR ON ADDRESS AND DATASeptember 2022September 2024Allow2420YesNo
17907048METHOD FOR PERFORMING LDPC SOFT DECODING, MEMORY, AND ELECTRONIC DEVICESeptember 2022April 2024Allow1910NoNo
17949655SYNDROME DECODING SYSTEMSeptember 2022August 2024Allow2310YesNo
17942059SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHESSeptember 2022December 2023Allow1510YesNo
17891697MEMORY DEVICE HAVING AN ENHANCED ESD PROTECTION AND A SECURE ACCESS FROM A TESTING MACHINEAugust 2022April 2023Allow800YesNo
17877484MEMORY AND OPERATION METHOD OF MEMORYJuly 2022June 2024Allow2210YesNo
17796564STATION APPARATUS AND COMMUNICATION METHODJuly 2022March 2024Abandon2010NoNo
17877607METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORSJuly 2022March 2024Allow2010YesNo
17874212ECC MEMORY CHIP ENCODER AND DECODERJuly 2022March 2024Allow2020YesNo
17857038FUSE BLOWING METHOD AND APPARATUS FOR MEMORY, STORAGE MEDIUM, AND ELECTRONIC DEVICEJuly 2022April 2024Abandon2210NoNo
17856827PREDETERMINED PATTERN PROGRAM OPERATIONSJuly 2022August 2024Allow2530YesNo
17855012HYBRID SOLVER FOR INTEGRATED CIRCUIT DIAGNOSTICS AND TESTINGJune 2022March 2024Allow2110YesNo
17810254COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINEJune 2022December 2024Allow3030YesNo
17849729METHOD AND APPARATUS FOR TESTING MEMORY CHIP, STORAGE MEDIUM, AND ELECTRONIC DEVICEJune 2022September 2024Abandon2720NoNo
17847421SYSTEMS AND METHODS FOR SCAN CHAIN STITCHINGJune 2022February 2024Allow2010YesNo
17836313SEMICONDUCTOR DEVICESJune 2022January 2025Allow3230YesNo
17750581STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICESMay 2022January 2025Allow3130YesNo
17777561TEST METHOD AND APPARATUS OF COMMUNICATION CHIP, DEVICE AND MEDIUMMay 2022January 2024Allow2010YesNo
17717239TRANSMITTER AND PUNCTURING METHOD THEREOFApril 2022April 2023Allow1200YesNo
17707473PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICEMarch 2022March 2023Allow1200YesNo
17693995RECEIVER RECEIVING A SIGNAL INCLUDING PHYSICAL LAYER FRAMES, AND INCLUDING A CONVOLUTIONAL DEINTERLEAVER AND A DEINTERLEAVER SELECTORMarch 2022October 2024Allow3130YesNo
17668715ERROR CORRECTION SYSTEMFebruary 2022June 2023Allow1600YesNo
17592054METHODS AND SYSTEMS FOR DATA TRANSMISSIONFebruary 2022September 2023Allow1910YesNo
17573190TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOFJanuary 2022July 2023Allow1810YesNo
17573257TEST ACCESS PORT ARCHITECTURE TO FACILITATE MULTIPLE TESTING MODESJanuary 2022March 2024Allow2620YesNo
17569163TRANSMITTER AND ADDITIONAL PARITY GENERATING METHOD THEREOFJanuary 2022July 2023Allow1810YesNo
17567587RATE MATCHING FOR BLOCK ENCODINGJanuary 2022December 2023Allow2320YesNo
17549377MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORINGDecember 2021May 2023Allow1710NoNo
17545113SCAN TEST IN A SINGLE-WIRE BUS CIRCUITDecember 2021April 2024Allow2920NoNo
17542875COMPOSITE DATA RECOVERY PROCEDUREDecember 2021September 2023Allow2210YesNo
17595452TEST METHOD FOR CONTROL CHIP AND RELATED DEVICENovember 2021September 2023Allow2210YesNo
17454443APPARATUSES AND METHODS FOR REPAIRING DEFECTIVE MEMORY CELLS BASED ON A SPECIFIED ERROR RATE FOR CERTAIN MEMORY CELLSNovember 2021January 2024Allow2620YesNo
17513233PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICEOctober 2021February 2024Allow2720YesNo
17510602AUTOMATIC TEST PATTERN GENERATION CIRCUITRY IN MULTI POWER DOMAIN SYSTEM ON A CHIPOctober 2021February 2023Allow1500YesNo
17500453SYSTEM AND METHOD FOR SCHEDULE-BASED I/O MULTIPLEXING FOR INTEGRATED CIRCUIT (IC) SCAN TESTOctober 2021November 2023Allow2511YesNo
17491529POLAR CODE ENCODING METHOD AND APPARATUS IN WIRELESS COMMUNICATIONSOctober 2021June 2023Allow2110YesNo
17482315RATE MATCHING AND CHANNEL INTERLEAVING FOR PROBABILISTIC SHAPINGSeptember 2021January 2024Allow2720NoNo
17479067NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICESeptember 2021December 2023Allow2720YesNo
17478736PERFORMING TESTING UTILIZING STAGGERED CLOCKSSeptember 2021April 2023Allow1920NoNo
17447743BUILT IN SELF TEST (BIST) FOR CLOCK GENERATION CIRCUITRYSeptember 2021May 2023Allow2010NoNo
17468066METHOD AND CIRCUIT FOR SCAN DUMP OF LATCH ARRAYSeptember 2021April 2022Allow810YesNo
17468024METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAYSeptember 2021April 2022Allow810YesNo
174614823-Dimensional NAND Flash Layer Variation Aware SSD RaidAugust 2021March 2023Allow1810YesNo
17409359ERROR CORRECTION BASED ON RATE ADAPTIVE LOW DENSITY PARITY CHECK (LDPC) CODES WITH FLEXIBLE COLUMN WEIGHTS IN THE PARITY CHECK MATRICESAugust 2021March 2022Allow700NoNo
17378176APPARATUS AND METHOD FOR USING AN ERROR CORRECTION CODE IN A MEMORY SYSTEMJuly 2021April 2022Allow900YesNo
17344180SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAMEJune 2021February 2023Allow2010YesNo
17333101TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOFMay 2021August 2022Allow1500YesNo
17330881MEMORY AND OPERATION METHOD OF MEMORYMay 2021May 2022Allow1110NoNo
17329870TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOFMay 2021September 2022Allow1600YesNo
17329779TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOFMay 2021August 2022Allow1500YesNo
17329215SCAN TEST DEVICE AND SCAN TEST METHODMay 2021July 2023Allow2630NoNo
17320165BUILT-IN SELF-TEST FOR DIE-TO-DIE PHYSICAL INTERFACESMay 2021January 2023Allow2010YesNo
17318168DEVICES AND METHODS FOR SAFETY MECHANISMSMay 2021November 2022Allow1920YesYes
17245568MEMORY DEVICE FOR COLUMN REPAIRApril 2021September 2022Allow1710YesNo
17240956Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good DieApril 2021November 2022Abandon1910NoNo
17240804BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAMEApril 2021November 2022Allow1910NoNo
17240801BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAMEApril 2021November 2022Allow1910YesNo
17216516TESTING MEMORY ELEMENTS USING AN INTERNAL TESTING INTERFACEMarch 2021June 2022Allow1510YesNo
17205490CONTROLLER STRUCTURAL TESTING WITH AUTOMATED TEST VECTORSMarch 2021October 2022Allow1910YesNo
17199874SCALABLE SCAN ARCHITECTURE FOR MULTI-CIRCUIT BLOCK ARRAYSMarch 2021January 2023Allow2230YesNo
17198091LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAMEMarch 2021May 2022Allow1410NoNo
17192030DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCEMarch 2021January 2024Allow3540YesNo
17272354INFRASTRUCTURE EQUIPMENT, COMMUNICATIONS DEVICE AND METHODSMarch 2021May 2022Allow1410NoNo
17179955INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, METHOD FOR OPERATING AN INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, MULTI-CORE PROCESSOR DEVICE AND METHOD FOR OPERATING A MULTI-CORE PROCESSOR DEVICEFebruary 2021November 2022Allow2110YesNo
17167382TEST METHOD AND TEST SYSTEMFebruary 2021December 2021Allow1110NoNo
17165831BOUNDARY TEST CIRCUIT, MEMORY AND BOUNDARY TEST METHODFebruary 2021January 2022Allow1210NoNo
17248661TESTING A MEMORY WHICH INCLUDES CONSERVATIVE REVERSIBLE LOGICFebruary 2021May 2022Allow1500NoNo
17135125PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICEDecember 2020July 2021Allow710YesNo
17132028MEMORY CONTROLLERS, MEMORY SYSTEMS AND MEMORY MODULESDecember 2020March 2022Allow1510YesNo
17250202STORAGE CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHODDecember 2020March 2023Abandon2720NoNo
17119572CORRECTING MEMORY DATA USING AN ERROR CODE AND A MEMORY TEST RESULTDecember 2020January 2024Allow3830YesNo
17108386METHODS AND SYSTEMS FOR DATA TRANSMISSIONDecember 2020September 2021Allow1000YesNo
17059499APPARATUS AND METHOD FOR SENDING SIDE-CHANNEL BITS ON AN ETHERNET CABLENovember 2020August 2023Abandon3240NoNo
17100647TEST ACCESS PORT ARCHITECTURE TO FACILITATE MULTIPLE TESTING MODESNovember 2020September 2021Allow1000YesNo
16950176Trajectory-Optimized Test Pattern Generation for Built-In Self-TestNovember 2020October 2022Allow2310NoNo
17064952MEMORY DEVICEOctober 2020April 2022Allow1910NoNo
17033989PACKET RECONSTRUCTION AND ERROR CORRECTION FOR NETWORK ENDPOINTSSeptember 2020October 2024Abandon4850NoYes
17030069INTEGRATED CIRCUIT SELF-REPAIR METHOD AND INTEGRATED CIRCUIT THEREOFSeptember 2020March 2023Allow3020NoNo
17027301DATA PROCESSING SYSTEM, MEMORY CONTROLLER THEREFOR, AND OPERATING METHOD THEREOFSeptember 2020October 2022Allow2520NoNo
17024798FAULT INJECTION IN A CLOCK MONITOR UNITSeptember 2020November 2022Allow2610NoNo
17021080METHOD AND APPARATUS FOR TESTING ARTIFICIAL INTELLIGENCE CHIP, DEVICE AND STORAGE MEDIUMSeptember 2020March 2023Allow3020NoNo
17012598DATA PROCESSING APPARATUS AND DATA PROCESSING METHODSeptember 2020August 2021Allow1100YesNo
17004557PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICEAugust 2020November 2021Allow1510NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner HOSSAIN, SAZZAD.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
4
Examiner Affirmed
2
(50.0%)
Examiner Reversed
2
(50.0%)
Reversal Percentile
70.6%
Higher than average

What This Means

With a 50.0% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
18
Allowed After Appeal Filing
9
(50.0%)
Not Allowed After Appeal Filing
9
(50.0%)
Filing Benefit Percentile
76.3%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 50.0% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is in the top 25% across the USPTO, indicating that filing appeals is particularly effective here. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner HOSSAIN, SAZZAD - Prosecution Strategy Guide

Executive Summary

Examiner HOSSAIN, SAZZAD works in Art Unit 2111 and has examined 271 patent applications in our dataset. With an allowance rate of 88.9%, this examiner has an above-average tendency to allow applications. Applications typically reach final disposition in approximately 25 months.

Allowance Patterns

Examiner HOSSAIN, SAZZAD's allowance rate of 88.9% places them in the 67% percentile among all USPTO examiners. This examiner has an above-average tendency to allow applications.

Office Action Patterns

On average, applications examined by HOSSAIN, SAZZAD receive 1.99 office actions before reaching final disposition. This places the examiner in the 64% percentile for office actions issued. This examiner issues a slightly above-average number of office actions.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by HOSSAIN, SAZZAD is 25 months. This places the examiner in the 65% percentile for prosecution speed. Prosecution timelines are slightly faster than average with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +22.6% benefit to allowance rate for applications examined by HOSSAIN, SAZZAD. This interview benefit is in the 72% percentile among all examiners. Recommendation: Interviews provide an above-average benefit with this examiner and are worth considering.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 31.4% of applications are subsequently allowed. This success rate is in the 56% percentile among all examiners. Strategic Insight: RCEs show above-average effectiveness with this examiner. Consider whether your amendments or new arguments are strong enough to warrant an RCE versus filing a continuation.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 17.4% of cases where such amendments are filed. This entry rate is in the 13% percentile among all examiners. Strategic Recommendation: This examiner rarely enters after-final amendments compared to other examiners. You should generally plan to file an RCE or appeal rather than relying on after-final amendment entry. Per MPEP § 714.12, primary examiners have discretion in entering after-final amendments, and this examiner exercises that discretion conservatively.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 85.7% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 63% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 78.9% of appeals filed. This is in the 67% percentile among all examiners. Of these withdrawals, 60.0% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner shows above-average willingness to reconsider rejections during appeals. The mandatory appeal conference (MPEP § 1207.01) provides an opportunity for reconsideration.

Petition Practice

When applicants file petitions regarding this examiner's actions, 0.0% are granted (fully or in part). This grant rate is in the 1% percentile among all examiners. Strategic Note: Petitions are rarely granted regarding this examiner's actions compared to other examiners. Ensure you have a strong procedural basis before filing a petition, as the Technology Center Director typically upholds this examiner's decisions.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 0.0% of allowed cases (in the 7% percentile). This examiner rarely makes examiner's amendments compared to other examiners. You should expect to make all necessary claim amendments yourself through formal amendment practice.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.8% of allowed cases (in the 54% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Plan for RCE after final rejection: This examiner rarely enters after-final amendments. Budget for an RCE in your prosecution strategy if you receive a final rejection.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.