USPTO Examiner BRITT CYNTHIA H - Art Unit 2111

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18872721GRAY MAPPING FOR VARIABLE-TO-FIXED DISTRIBUTION MATCHINGDecember 2024March 2026Allow1500NoNo
18816685REAL-TIME DEBUG IN LOW-POWER DEVICESAugust 2024February 2026Allow1700NoNo
18798321PROCESSOR-BASED SYSTEM SUPPORTING IN-FIELD TESTING USING EXTERNAL DYNAMIC RANDOM ACCESS MEMORY (DRAM) FOR STORING AND ACCESSING TEST SCAN DATAAugust 2024November 2025Allow1500NoNo
18798499MEMORY DEVICE DETECTING FAIL OF THROUGH-SILICON VIAAugust 2024December 2025Allow1600YesNo
18785170Test Data Transfer in Multi-Die SystemsJuly 2024September 2025Allow1400NoNo
18779058POLAR CODE ENCODING METHOD, POLAR CODE DECODING METHOD, AND APPARATUSES THEREOFJuly 2024March 2026Allow1910NoNo
18776478AUTOMOTIVE TOUCH CIRCUIT DEVICE WITH ESD PROTECTIONJuly 2024November 2025Allow1600NoNo
18771866SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAMEJuly 2024May 2025Allow1010YesNo
18771392ERROR CORRECTION CIRCUITJuly 2024February 2026Allow1910YesNo
18726670HIGH-THROUGHPUT SCAN ARCHITECTUREJuly 2024January 2026Allow1910NoNo
18754683INTEGRATED CIRCUIT DIE TEST ARCHITECTUREJune 2024January 2025Allow700NoNo
18752634A Scannable Memory Array and A Method for Scanning MemoryJune 2024November 2024Allow410YesNo
18750192SENDING METHOD, RECEIVING METHOD, APPARATUS, SYSTEM, DEVICE, AND STORAGE MEDIUMJune 2024February 2026Allow2010NoNo
18742891METHOD AND SYSTEM FOR CONTEXT-BASED RETRANSMISSION OF LOST PACKETSJune 2024September 2025Allow1500NoNo
18742474SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING AN ELECTRONIC CIRCUITJune 2024November 2025Allow1820NoNo
187342263D STACKED DIE TEST ARCHITECTUREJune 2024July 2025Allow1310NoNo
18680660BANDWIDTH UTILIZATION TECHNIQUES FOR IN-BAND REDUNDANT DATAMay 2024April 2025Allow1100NoNo
18672282Analyzing bit error data to determine a root cause of errors in a digital systemMay 2024November 2025Allow1810YesNo
18671394ELECTRONIC DEVICE WITH ERASURE CODING ACCELERATION FOR DISTRIBUTED FILE SYSTEMS AND OPERATING METHOD THEREOFMay 2024April 2025Allow1110NoNo
18671560INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTINGMay 2024February 2026Allow2110YesNo
18659942LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAMEMay 2024July 2025Allow1400NoNo
18654208SYSTEMS AND METHODS FOR COMPRESSED SENSING MEASUREMENT OF LONG-RANGE CORRELATED NOISEMay 2024January 2025Allow810YesNo
18704027Cyclic redundancy check for a communication methodApril 2024October 2025Allow1810NoNo
18637901TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENTApril 2024May 2025Allow1320NoNo
18701496METHOD AND DEVICE FOR QUANTUM ERROR FILTERING USING QUANTUM ERROR FILTERING CODEApril 2024January 2026Allow2210NoNo
18631416ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHODApril 2024September 2025Allow1710NoNo
18630484ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHODApril 2024September 2025Allow1710NoNo
18620071TRANSMISSION METHOD AND APPARATUSMarch 2024January 2026Abandon2210NoNo
18617433METHOD FOR POLAR CODE DESIGN WITH PARITY CHECK BITSMarch 2024May 2025Allow1400NoNo
18617034CODE DESIGNS FOR NONUNIFORM SOURCESMarch 2024December 2025Allow2101NoNo
18608711LOW PIN COUNT SCAN WITH NO DEDICATED SCAN ENABLE PINMarch 2024July 2025Allow1600NoNo
18607764SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND EVALUATION SYSTEMMarch 2024February 2026Allow2320NoNo
18607368SCAN CHAIN CONTROLMarch 2024November 2025Allow2010YesNo
18688393TEMPLATIZED MEMORY PATTERN GENERATOR AND METHODMarch 2024August 2025Allow1700NoNo
18592227JTAG STANDARD PIN TEST SYSTEMFebruary 2024August 2025Allow1710YesNo
18590333INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND COMPUTER-PROGRAM PRODUCTFebruary 2024January 2026Allow2311NoNo
18588819CHECKING DATA INTEGRITY BY COMPARING ERROR-CHECK SIGNALS GENERATED ON DIFFERENT CLOCK CYCLESFebruary 2024June 2025Allow1600NoNo
18438860MULTIPLE ACCESS PORT CIRCUITSFebruary 2024September 2025Allow1910NoNo
18439236QUANTUM SYSTEM CONTROLLER CONFIGURED FOR QUANTUM ERROR CORRECTIONFebruary 2024October 2024Allow800NoNo
18420877ELECTRONIC DEVICES AND METHODS OF OPERATING THE SAMEJanuary 2024April 2025Allow1500NoNo
18419432MAGNETIC REPRODUCING PROCESSING DEVICE, MAGNETIC RECORDING/REPRODUCING DEVICE AND MAGNETIC REPRODUCING METHODJanuary 2024March 2025Allow1400NoNo
18406852PROGRAM PULSE MODIFICATIONJanuary 2024August 2025Allow1910NoNo
18576756TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHODJanuary 2024January 2025Allow1300NoNo
18541159SYSTEMS AND METHODS FOR QUANTUM-ENABLED ERROR CORRECTIONDecember 2023May 2025Allow1710NoNo
18539172Receiver Performance Measurement System and Method ThereofDecember 2023September 2025Allow2110YesNo
18569311A METHOD TO FACILITATE ADAPTIVE BIT LOADING BY INSERTION OF DUMMY BITS PRIOR TO INTERLEAVINGDecember 2023September 2025Abandon2100NoNo
18536011LOWER-BOUNDING DISTANCE OF STABILIZER CHANNEL SEQUENCEDecember 2023March 2025Allow1500NoNo
18524900INTERPOSER CIRCUITNovember 2023February 2025Allow1500NoNo
18504324APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOFNovember 2023July 2025Allow2020YesNo
18289644DECODING OF SERIES-CONCATENATED TURBO CODESNovember 2023April 2025Allow1810NoNo
18386301AT-SPEED TEST ACCESS PORT OPERATIONSNovember 2023July 2024Allow800NoNo
18499743APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY FOR AT-SPEED TESTINGNovember 2023May 2025Allow1910YesNo
18384267OPTICAL TRANSMITTER WITH ENCODER ENCODING PROCESSED DATA INCLUDING CONCATENATING PARITY BITS TO GENERATE FEC DATA BLOCKSOctober 2023April 2025Allow1710YesNo
18491612SHORT LATENCY FAST RETRANSMISSION TRIGGERINGOctober 2023September 2024Allow1110NoNo
18487955MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATIONOctober 2023October 2024Allow1210NoNo
18379686Test device for testing on-chip clock controller having debug functionOctober 2023March 2025Allow1710YesNo
18475047TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERNSeptember 2023May 2025Allow1910NoNo
18372784SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDSSeptember 2023December 2023Allow210NoNo
18552091METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING SIGNALS OF TERMINAL AND BASE STATION IN WIRELESS COMMUNICATION SYSTEMSeptember 2023March 2025Allow1810NoNo
18551408COMMUNICATION DEVICE, COMMUNICATION METHOD, AND COMMUNICATION SYSTEMSeptember 2023March 2025Allow1710NoNo
18471096Functional Circuit Block Harvesting in Computer SystemsSeptember 2023March 2025Allow1810YesNo
18550903DYNAMIC CODE BLOCK GROUP (CBG) ALLOCATIONSeptember 2023February 2025Allow1710NoNo
18463535MEMORY SYSTEM AND NONVOLATILE MEMORYSeptember 2023October 2024Allow1300NoNo
18244162SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUITSeptember 2023June 2025Allow2100NoNo
18246673SYSTEM FOR AUTONOMOUS STABILISATION OF QUANTUM STATES HAVING A PREDETERMINED PARITY FOR ERROR CORRECTIONSeptember 2023July 2025Allow2810NoNo
18240143ERROR RECOVERY AND POWER MANAGEMENT BETWEEN NODES OF AN INTERCONNECTION NETWORKAugust 2023August 2024Allow1110NoNo
18240162NEURAL-NETWORK-OPTIMIZED DEGREE-SPECIFIC WEIGHTS FOR LDPC MINSUM DECODINGAugust 2023April 2025Allow2010NoNo
18458966SYSTEM ARCHITECTURE OF NETWORK CODING AT USER PLANE FUNCTIONAugust 2023January 2025Allow1600NoNo
18457537FAULT TOLERANT SYNCHRONIZERAugust 2023October 2024Allow1310NoNo
18237573ADDRESSABLE TEST ACCESS PORTAugust 2023March 2024Allow700NoNo
18234003SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDSAugust 2023July 2025Allow2320NoNo
18447969LOG LIKELIHOOD RATIOS ADJUSTMENT BASED ON ERROR TRACKERAugust 2023November 2024Allow1500NoNo
18447868STORAGE-FREE MESSAGE AUTHENTICATORS FOR ERROR-CORRECTING-CODESAugust 2023August 2024Allow1300NoNo
18264730INSTRUCTION ENCODING-BASED DATA PROCESSING METHOD AND APPARATUS, AND DEVICEAugust 2023November 2024Allow1500NoNo
18363734STORAGE DEVICE AND READ RECOVERY METHOD THEREOFAugust 2023November 2024Allow1500NoNo
18226924INTEGRATED CIRCUIT DIE TEST ARCHITECTUREJuly 2023February 2024Allow700NoNo
18223121DECODING OF ERROR CORRECTION CODES BASED ON REVERSE DIFFUSIONJuly 2023February 2025Allow1911NoNo
18353538POLAR CODER FOR CHANNEL ENCODING CHAIN FOR WIRELESS COMMUNICATIONSJuly 2023August 2024Allow1300NoNo
18349712MEMORY CONTROLLER PERFORMING ERROR CORRECTION AND OPERATING METHOD THEREOFJuly 2023February 2025Allow1910NoNo
18342819SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICEJune 2023June 2025Allow2320YesNo
18213828SELECTABLE MULTI-STAGE ERROR DETECTION AND CORRECTIONJune 2023March 2025Allow2100NoNo
18268517TEST CIRCUIT, TEST METHOD, AND COMPUTING SYSTEM COMPRISING TEST CIRCUIT FOR TESTING SEQUENTIAL CIRCUIT IN PIPELINE STAGEJune 2023July 2025Allow2510NoNo
18211353TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITYJune 2023August 2024Allow1410NoNo
18210823Soft FEC With Parity CheckJune 2023May 2024Allow1110NoNo
182083663D STACKED DIE TEST ARCHITECTUREJune 2023February 2024Allow800YesNo
18200047DEVICE ACCESS PORT SELECTIONMay 2023September 2024Allow1600NoNo
18198301SPEED DETECTION CIRCUIT AND ASSOCIATED CHIPMay 2023October 2025Allow2910YesNo
18316913DECODING METADATA ENCODED IN ERROR CORRECTION CODESMay 2023November 2024Allow1810YesNo
18252360SEMICONDUCTOR CIRCUIT INCLUDING LATCH CIRCUIT FOR ERROR CORRECTIONMay 2023August 2024Allow1610NoNo
18144848Process for Scan Chain in a MemoryMay 2023January 2024Allow810NoNo
18251659ENCODING METHOD, DECODING METHOD, ELECTRONIC DEVICE AND STORAGE MEDIUMMay 2023September 2024Allow1710NoNo
18310362Error Correction Incident TrackingMay 2023April 2025Allow2320NoNo
18310016TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENTMay 2023December 2023Allow700NoNo
18309806STORAGE DEVICE DETERMINING QUICKLY WHETHER ERROR CORRECTION DECODING HAS FAILED AND METHOD OF OPERATING THE STORAGE DEVICEApril 2023November 2024Allow1910NoNo
18306563TRANSMISSION METHOD, APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUMApril 2023December 2023Allow800NoNo
18137716TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHODApril 2023February 2024Allow910NoNo
18302847ERROR CORRECTION FOR COMPUTATIONAL MEMORY MODULESApril 2023December 2024Allow2010NoNo
18135367INTERFACE TO FULL AND REDUCED PIN JTAG DEVICESApril 2023June 2024Allow1410NoNo
18296640MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUITApril 2023February 2025Allow2310NoNo
18193973TESTING MULTI-CYCLE PATHS USING SCAN TESTMarch 2023August 2025Allow2810NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner BRITT, CYNTHIA H.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
1
Examiner Affirmed
0
(0.0%)
Examiner Reversed
1
(100.0%)
Reversal Percentile
92.2%
Higher than average

What This Means

With a 100.0% reversal rate, the PTAB has reversed the examiner's rejections more often than affirming them. This reversal rate is in the top 25% across the USPTO, indicating that appeals are more successful here than in most other areas.

Strategic Value of Filing an Appeal

Total Appeal Filings
7
Allowed After Appeal Filing
3
(42.9%)
Not Allowed After Appeal Filing
4
(57.1%)
Filing Benefit Percentile
70.5%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 42.9% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner BRITT, CYNTHIA H - Prosecution Strategy Guide

Executive Summary

Examiner BRITT, CYNTHIA H works in Art Unit 2111 and has examined 467 patent applications in our dataset. With an allowance rate of 98.3%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 19 months.

Allowance Patterns

Examiner BRITT, CYNTHIA H's allowance rate of 98.3% places them in the 91% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by BRITT, CYNTHIA H receive 1.00 office actions before reaching final disposition. This places the examiner in the 10% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by BRITT, CYNTHIA H is 19 months. This places the examiner in the 94% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a -0.6% benefit to allowance rate for applications examined by BRITT, CYNTHIA H. This interview benefit is in the 11% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 41.6% of applications are subsequently allowed. This success rate is in the 93% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 67.2% of cases where such amendments are filed. This entry rate is in the 90% percentile among all examiners. Strategic Recommendation: This examiner is highly receptive to after-final amendments compared to other examiners. Per MPEP § 714.12, after-final amendments may be entered "under justifiable circumstances." Consider filing after-final amendments with a clear showing of allowability rather than immediately filing an RCE, as this examiner frequently enters such amendments.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 0.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 4% percentile among all examiners. Note: Pre-appeal conferences show limited success with this examiner compared to others. While still worth considering, be prepared to proceed with a full appeal brief if the PAC does not result in favorable action.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 87.5% of appeals filed. This is in the 80% percentile among all examiners. Of these withdrawals, 28.6% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 45.5% are granted (fully or in part). This grant rate is in the 39% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 4.3% of allowed cases (in the 84% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 14.4% of allowed cases (in the 91% percentile). Per MPEP § 714.14, a Quayle action indicates that all claims are allowable but formal matters remain. This examiner frequently uses Quayle actions compared to other examiners, which is a positive indicator that once substantive issues are resolved, allowance follows quickly.

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • Consider after-final amendments: This examiner frequently enters after-final amendments. If you can clearly overcome rejections with claim amendments, file an after-final amendment before resorting to an RCE.
  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.