USPTO Examiner TABONE JR JOHN J - Art Unit 2111

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
18916809OpenFEC error markingOctober 2024February 2026Allow1600NoNo
18899981TESTER CHANNEL MULTIPLEXING IN TEST EQUIPMENTSeptember 2024December 2025Allow1500NoNo
18792138JTAG-BASED APPARATUS AND METHOD FOR INPUT CLOCK FREQUENCY MEASUREMENTAugust 2024November 2025Allow1600NoNo
18791155SYSTEM FOR HANDLING REPEATED PROGRAMMING ERRORSJuly 2024November 2025Allow1600NoNo
18790407METHODS AND SYSTEM WITH DYNAMIC ECC VOLTAGE AND FREQUENCYJuly 2024January 2026Allow1710NoNo
18789201SEMICONDUCTOR MEMORY DEVICE-DIRECTED ERROR CHECK AND SCRUBJuly 2024January 2026Allow1800YesNo
18786481MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICEJuly 2024October 2025Allow1400NoNo
18779811BIN-BASED READ ERROR HANDLING FLOWS USING A FAST CORRECTIVE READ OPERATIONJuly 2024February 2026Allow1910YesNo
18774787SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMSJuly 2024January 2026Allow1810NoNo
18770809Scan Flip-Flops With Pre-Setting Combinational LogicJuly 2024January 2026Allow1810NoNo
18770435SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOFJuly 2024September 2025Allow1400NoNo
18769924MANAGEMENT OF MESSAGE TRANSMISSION USING FORWARD ERROR CORRECTIONJuly 2024May 2025Allow1010NoNo
18762642MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAMEJuly 2024November 2025Allow1621NoNo
18761586COMPUTE-IN-MEMORY USING NEURAL NETWORKS STORED IN A NON-VOLATILE MEMORY FOR PREDICTIVE BLOCK HEALTH ASSESSMENT OF THE NON-VOLATILE MEMORYJuly 2024February 2026Allow1900NoNo
18761725MEMORY SYSTEM AND METHODJuly 2024September 2025Allow1400NoNo
18725676MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFERJune 2024February 2026Allow1910NoNo
18749823METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORSJune 2024January 2026Allow1900NoNo
18743994APPARATUSES AND METHODS FOR SHARED CODEWORD IN 2-PASS ACCESS OPERATIONSJune 2024December 2025Allow1800YesNo
18740412INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTINGJune 2024March 2026Allow2110NoNo
18735599TEST PATTERN RESET CONTROL CIRCUITJune 2024July 2025Allow1300NoNo
18736001Directional Control of Scan Capture Through Shared Wrapper CellsJune 2024August 2025Allow1400YesNo
18733984REDUCING VOLTAGE DROOPING IN A MICROELECTRONIC CHIPJune 2024September 2025Allow1500NoNo
18673628HANDLING NON-CORRECTABLE ERRORSMay 2024March 2025Allow1010YesNo
18665596DATA PROCESSING SYSTEM, STORAGE DEVICE, OPERATING METHOD OF STORAGE DEVICEMay 2024July 2025Allow1400NoNo
18665946DATA CHARACTERISTIC-BASED ERROR CORRECTION SYSTEMS AND METHODSMay 2024February 2026Allow2110YesNo
18663701METHODS, DEVICES, AND MEDIUM FOR COMMUNICATIONMay 2024April 2025Allow1110NoNo
18661526TEMPERATURE SENSOR MANAGEMENT DURING ERROR HANDLING OPERATIONS IN A MEMORY SUB-SYSTEMMay 2024June 2025Allow1300NoNo
18660055VARIABLE CONFIGURATIONS OF NFRP RU TONE SETS IN WIRELESS NETWORKSMay 2024May 2025Allow1210NoNo
18654962CLOCK GLITCH DETECTORMay 2024December 2025Allow2010YesNo
18649009CONFIGURABLE IN-ARRAY EVENT TRACKINGApril 2024October 2025Allow1700NoNo
18648992INTERFACE, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEMApril 2024August 2025Allow1610YesNo
18647738SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 1/2 CODE RATEApril 2024October 2025Allow1810YesNo
18647663SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 1/2 CODE RATEApril 2024January 2026Allow2010YesNo
18645817POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALINGApril 2024November 2024Allow700NoNo
18645810MEMORY CONTROLLER FOR CONTROLLING BACKGROUND OPERATION AND OPERATION METHOD THEREOFApril 2024December 2025Allow2010YesNo
18641942SOLID-STATE DRIVE WITH MULTIMODE COMPRESSION AND ERROR CORRECTIONApril 2024May 2025Allow1300NoNo
18642287FORWARD ERROR CORRECTION WITH FLEXIBLE MATRIX FOR DYNAMIC INPUT DATA RATEApril 2024August 2025Allow1600NoNo
18701331MANAGING DATA STORAGE IN A COMMUNICATIONS SYSTEMApril 2024November 2025Allow1910NoNo
18628831DATA STORAGE DEVICE AND SEARCHING METHOD FOR READING VOLTAGE THEREOFApril 2024May 2025Allow1300NoNo
18620534CIRCUITRY INCLUDING SCAN AND NON-SCAN REGISTERSMarch 2024December 2025Allow2020YesNo
18612251RESET FOR SCAN MODE EXIT FOR DEVICES WITH POWER-ON RESET GENERATION CIRCUITRYMarch 2024May 2025Allow1400NoNo
18607152MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATIONMarch 2024June 2025Allow1520YesNo
18590671TECHNIQUES FOR INDICATING A WRITE LINK ERRORFebruary 2024April 2025Allow1320YesNo
18444482APPARATUSES AND METHODS FOR VARIABLE INPUT ECC CIRCUITSFebruary 2024June 2025Allow1600YesNo
18444320MEMORY DEVICE AND REPAIR METHOD WITH COLUMN-BASED ERROR CODE TRACKINGFebruary 2024December 2024Allow1010NoNo
18438917CO-DEBUG OF PROCESSING CONDITIONS OF LOGIC DEVICESFebruary 2024June 2025Allow1600NoNo
18422934TRANSIENT FAULT DETECTION IN MEMORY USING DYNAMIC BISTJanuary 2024June 2025Allow1600NoNo
18420849STORAGE DEVICE INCLUDING A READ RECLAIM MODULE AND A RECLAIM OPERATION METHOD THEREOFJanuary 2024June 2025Allow1600NoNo
18415631DECODER FOR INTERLEAVED REED-SOLOMON (IRS) WITH ERASURE/COLLABORATIVEJanuary 2024March 2025Allow1400NoNo
18406067SAVING AND RESTORING SCAN STATESJanuary 2024February 2025Allow1400NoNo
18397481Automatic Test Pattern Generation-Based Circuit Verification Method and ApparatusDecember 2023February 2025Allow1300NoNo
18391145Scan Data Transfer Circuits for Multi-die Chip TestingDecember 2023August 2025Allow2010YesNo
18544572MEMORY CHIPS AND OPERATING METHODS THEREOFDecember 2023April 2025Allow1600NoNo
18540351ERRONEOUS BIT DISCOVERY IN MEMORY SYSTEMDecember 2023March 2025Allow1520YesNo
18538692DEVICE AND METHOD FOR PROVIDING PHYSICALLY UNCLONABLE FUNCTION WITH HIGH RELIABILITYDecember 2023April 2025Allow1610YesNo
18534458SYSTEMS AND METHODS FOR VERIFYING DATA IN MEMORYDecember 2023September 2025Allow2210YesNo
18531548SCAN CHAIN FORMATION FOR IMPROVING CHAIN RESOLUTIONDecember 2023March 2025Allow1500NoNo
18530457Data Storage Based On Characteristics of Storage MediaDecember 2023September 2024Allow1010NoNo
18529408HARQ RTT Timer Adjustment for Multi-TB SchedulingDecember 2023February 2025Allow1510YesNo
18520797SYSTEM AND METHOD FOR FAULT SEQUENCE RECORDINGNovember 2023November 2024Allow1200NoNo
18516121GLITCH DETECTIONNovember 2023August 2025Allow2110NoNo
18504302APPARATUSES AND METHODS FOR CONFIGURABLE ECC MODESNovember 2023March 2025Allow1710NoNo
18492140METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEMOctober 2023May 2024Allow700NoNo
18381883MEMORY TEST SYSTEM AND MEMORY TEST METHODOctober 2023November 2024Allow1320YesNo
18490675Error Detection and Recovery When Streaming DataOctober 2023June 2024Allow800NoNo
18489276Method and Chip for Cyclic Code Encoding, Circuit Component, and Electronic DeviceOctober 2023February 2025Allow1600NoNo
18487116DATA TRANSMISSION APPARATUS AND METHOD OF CROSS-DOMAIN DATA TRANSMISSIONOctober 2023January 2025Allow1500NoNo
18378488NR Broadcast Channel TransmissionOctober 2023August 2024Allow1110YesNo
18553929DATA RECOVERY METHOD FOR FLASH MEMORYOctober 2023October 2024Allow1300NoNo
183681953D TAP & SCAN PORT ARCHITECTURESSeptember 2023August 2024Allow1110YesNo
18243598OPTIMIZATIONS OF MEMORY-UTILIZATION AND PCM PROCESSING SCHEDULES FOR AN LDPC DECODERSeptember 2023January 2025Allow1610YesNo
18462497DATA PROCESSING METHOD AND DEVICE, AND DATA TRANSMISSION SYSTEMSeptember 2023February 2025Allow1710NoNo
18456318TECHNIQUES FOR CONSTRUCTING A HYBRID AUTOMATIC REPEAT REQUEST ACKNOWLEDGEMENT CODEBOOKAugust 2023December 2024Allow1510NoNo
18237809SUPERCONDUCTIVE INTEGRATED CIRCUIT DEVICES WITH ON-CHIP TESTINGAugust 2023February 2025Allow1700YesNo
18449775ELECTRONIC CIRCUIT WITH LOCAL CONFIGURATION CHECKERS WITH UNIQUE ID CODESAugust 2023August 2024Allow1210NoNo
18450280FAST CONVERGING LOW-DENSITY PARITY-CHECK TECHNIQUESAugust 2023January 2025Allow1700NoNo
18264625INFORMATION BIT DETERMINATION METHOD AND MAPPING GENERATION METHOD FOR POLAR-CODED MODULATION, AND DEVICEAugust 2023April 2025Allow2010NoNo
18365668METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN COMMUNICATION OR BROADCASTING SYSTEMAugust 2023March 2024Allow700YesNo
18362550SCAN COMPRESSION THROUGH PIN DATA ENCODINGJuly 2023June 2024Allow1110YesNo
18361995ACCESSING ERROR STATISTICS FROM DRAM MEMORIES HAVING INTEGRATED ERROR CORRECTIONJuly 2023July 2024Allow1110NoNo
18225689METHOD AND DEVICE IN UE AND BASE STATION FOR CHANNEL CODINGJuly 2023February 2024Allow700NoNo
18225313GENERALIZED LDPC ENCODER, GENERALIZED LDPC ENCODING METHOD AND STORAGE DEVICEJuly 2023November 2024Allow1600NoNo
18354501SCAN CHAIN CIRCUIT AND CORRESPONDING METHODJuly 2023September 2024Allow1410YesNo
18354509WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION METHOD, CONTROL DEVICE, AND CONTROL METHODJuly 2023October 2024Allow1500NoNo
18351709MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAMEJuly 2023September 2024Allow1500NoNo
18350776SYSTEM AND METHOD OF REDUCING LOGIC FOR MULTI-BIT ERROR CORRECTING CODESJuly 2023August 2024Allow1300NoNo
18350877MANAGING ERROR CORRECTIONS FOR MEMORY SYSTEMSJuly 2023August 2024Allow1300NoNo
18213766ACCELERATED ERASURE CODING SYSTEM AND METHODJune 2023September 2024Allow1510YesNo
18338635SYSTEMS AND METHODS FOR TESTING ERROR CORRECTION CODE (ECC) LOGIC OF AUTOMOTIVE SAFETY SYSTEMS FOR FAULTSJune 2023September 2025Allow2710NoNo
18336285SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICEJune 2023August 2024Allow1400NoNo
18334938System and Method for Protecting DataJune 2023February 2025Allow2010NoNo
18208886MULTIPLE CLOCK AND CLOCK CYCLE SELECTION FOR X-TOLERANT LOGIC BUILT IN SELF TEST (XLBIST)June 2023July 2024Allow1300NoNo
18204821MEMORY ADDRESS TRANSLATION FOR DATA PROTECTION AND RECOVERYJune 2023April 2025Allow2200NoNo
18327642MEDIA SCAN IN MEMORY SYSTEMSJune 2023January 2025Allow2010YesNo
18326717ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUITMay 2023September 2024Allow1500NoNo
18325999MEMORY DEVICE PERFORMING SENSING OPERATION AND METHOD OF OPERATING THE SAMEMay 2023August 2024Allow1500NoNo
18318840METHOD AND APPARATUS TO INJECT ERRORS IN A MEMORY BLOCK AND VALIDATE DIAGNOSTIC ACTIONS FOR MEMORY BUILT-IN-SELF-TEST (MBIST) FAILURESMay 2023August 2024Allow1500NoNo
18318655CONTROLLER, STORAGE DEVICE AND TEST SYSTEMMay 2023December 2024Allow1910YesNo
18036600UE PROCESSING LOAD INDICATIONMay 2023September 2024Allow1610NoNo
18036636OpenFEC error markingMay 2023July 2024Allow1410NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for examiner TABONE JR, JOHN J.

Strategic Value of Filing an Appeal

Total Appeal Filings
11
Allowed After Appeal Filing
4
(36.4%)
Not Allowed After Appeal Filing
7
(63.6%)
Filing Benefit Percentile
59.4%
Higher than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 36.4% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is above the USPTO average, suggesting that filing an appeal can be an effective strategy for prompting reconsideration.

Strategic Recommendations

✓ Filing a Notice of Appeal is strategically valuable. The act of filing often prompts favorable reconsideration during the mandatory appeal conference.

Examiner TABONE JR, JOHN J - Prosecution Strategy Guide

Executive Summary

Examiner TABONE JR, JOHN J works in Art Unit 2111 and has examined 453 patent applications in our dataset. With an allowance rate of 97.4%, this examiner allows applications at a higher rate than most examiners at the USPTO. Applications typically reach final disposition in approximately 18 months.

Allowance Patterns

Examiner TABONE JR, JOHN J's allowance rate of 97.4% places them in the 88% percentile among all USPTO examiners. This examiner is more likely to allow applications than most examiners at the USPTO.

Office Action Patterns

On average, applications examined by TABONE JR, JOHN J receive 0.81 office actions before reaching final disposition. This places the examiner in the 5% percentile for office actions issued. This examiner issues significantly fewer office actions than most examiners.

Prosecution Timeline

The median time to disposition (half-life) for applications examined by TABONE JR, JOHN J is 18 months. This places the examiner in the 96% percentile for prosecution speed. Applications move through prosecution relatively quickly with this examiner.

Interview Effectiveness

Conducting an examiner interview provides a +2.8% benefit to allowance rate for applications examined by TABONE JR, JOHN J. This interview benefit is in the 24% percentile among all examiners. Note: Interviews show limited statistical benefit with this examiner compared to others, though they may still be valuable for clarifying issues.

Request for Continued Examination (RCE) Effectiveness

When applicants file an RCE with this examiner, 41.4% of applications are subsequently allowed. This success rate is in the 93% percentile among all examiners. Strategic Insight: RCEs are highly effective with this examiner compared to others. If you receive a final rejection, filing an RCE with substantive amendments or arguments has a strong likelihood of success.

After-Final Amendment Practice

This examiner enters after-final amendments leading to allowance in 50.0% of cases where such amendments are filed. This entry rate is in the 75% percentile among all examiners. Strategic Recommendation: This examiner shows above-average receptiveness to after-final amendments. If your amendments clearly overcome the rejections and do not raise new issues, consider filing after-final amendments before resorting to an RCE.

Pre-Appeal Conference Effectiveness

When applicants request a pre-appeal conference (PAC) with this examiner, 80.0% result in withdrawal of the rejection or reopening of prosecution. This success rate is in the 62% percentile among all examiners. Strategic Recommendation: Pre-appeal conferences show above-average effectiveness with this examiner. If you have strong arguments, a PAC request may result in favorable reconsideration.

Appeal Withdrawal and Reconsideration

This examiner withdraws rejections or reopens prosecution in 100.0% of appeals filed. This is in the 88% percentile among all examiners. Of these withdrawals, 55.6% occur early in the appeal process (after Notice of Appeal but before Appeal Brief). Strategic Insight: This examiner frequently reconsiders rejections during the appeal process compared to other examiners. Per MPEP § 1207.01, all appeals must go through a mandatory appeal conference. Filing a Notice of Appeal may prompt favorable reconsideration even before you file an Appeal Brief.

Petition Practice

When applicants file petitions regarding this examiner's actions, 42.3% are granted (fully or in part). This grant rate is in the 34% percentile among all examiners. Strategic Note: Petitions show below-average success regarding this examiner's actions. Ensure you have a strong procedural basis before filing.

Examiner Cooperation and Flexibility

Examiner's Amendments: This examiner makes examiner's amendments in 6.6% of allowed cases (in the 89% percentile). Per MPEP § 1302.04, examiner's amendments are used to place applications in condition for allowance when only minor changes are needed. This examiner frequently uses this tool compared to other examiners, indicating a cooperative approach to getting applications allowed. Strategic Insight: If you are close to allowance but minor claim amendments are needed, this examiner may be willing to make an examiner's amendment rather than requiring another round of prosecution.

Quayle Actions: This examiner issues Ex Parte Quayle actions in 0.5% of allowed cases (in the 54% percentile). This examiner issues Quayle actions more often than average when claims are allowable but formal matters remain (MPEP § 714.14).

Prosecution Strategy Recommendations

Based on the statistical analysis of this examiner's prosecution patterns, here are tailored strategic recommendations:

  • RCEs are effective: This examiner has a high allowance rate after RCE compared to others. If you receive a final rejection and have substantive amendments or arguments, an RCE is likely to be successful.
  • Appeal filing as negotiation tool: This examiner frequently reconsiders rejections during the appeal process. Filing a Notice of Appeal may prompt favorable reconsideration during the mandatory appeal conference.
  • Examiner cooperation: This examiner frequently makes examiner's amendments to place applications in condition for allowance. If you are close to allowance, the examiner may help finalize the claims.

Relevant MPEP Sections for Prosecution Strategy

  • MPEP § 713.10: Examiner interviews - available before Notice of Allowance or transfer to PTAB
  • MPEP § 714.12: After-final amendments - may be entered "under justifiable circumstances"
  • MPEP § 1002.02(c): Petitionable matters to Technology Center Director
  • MPEP § 1004: Actions requiring primary examiner signature (allowances, final rejections, examiner's answers)
  • MPEP § 1207.01: Appeal conferences - mandatory for all appeals
  • MPEP § 1214.07: Reopening prosecution after appeal

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.