USPTO Art Unit 2811 Prosecution Statistics

Art Unit Information

Art Unit: 2811
Group: 2810
Tech Center: 2800
Total Cases: 17,591
Last Active: November 2024

Recent Applications

Detailed information about the 100 most recent patent applications.

Application NumberTitleFiling DateDisposal DateDispositionTime (months)Office ActionsRestrictionsInterviewAppeal
189590333D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERSNovember 2024June 2025Allow700NoNo
18887821ELECTRICAL CONTACT CAVITY STRUCTURE AND METHODS OF FORMING THE SAMESeptember 2024February 2025Allow510YesNo
18823093Backside Integrated Voltage Regulator For Integrated CircuitsSeptember 2024November 2024Allow210NoNo
18770678MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT AND ITS FABRICATION PROCESSJuly 2024March 2025Allow800NoNo
18766644TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOFJuly 2024April 2025Allow900NoNo
18764426THREE-STATE MEMORY DEVICEJuly 2024April 2025Allow1000YesNo
18758898SEMICONDUCTOR DEVICE STRUCTURE WITH NANOSTRUCTUREJune 2024June 2025Allow1110NoNo
18755693LAYOUT PATTERN OF MAGNETORESISTIVE RANDOM ACCESS MEMORYJune 2024March 2025Allow900NoNo
18753052CHIP STRUCTURE WITH CONDUCTIVE LAYERJune 2024May 2025Allow1010NoNo
18752381SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFJune 2024March 2025Allow910NoNo
18752112Self-Aligned Metal Gate for Multigate DeviceJune 2024May 2025Allow1110NoNo
18749014FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAMEJune 2024March 2025Allow910NoNo
18746288SEMICONDUCTOR DEVICES WITH BACKSIDE POWER RAIL AND BACKSIDE SELF-ALIGNED VIAJune 2024May 2025Allow1110NoNo
18745029SEMICONDUCTOR DEVICE STRUCTURE WITH BACKSIDE CONTACTJune 2024May 2025Allow1110NoNo
18743135DIODE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJune 2024March 2025Allow900NoNo
18741987Semiconductor Devices Including Backside Vias and Methods of Forming the SameJune 2024January 2025Allow700NoNo
18739519Gate Structures For Semiconductor DevicesJune 2024May 2025Allow1110YesNo
18738390Semiconductor Structure with Staggered Selective GrowthJune 2024May 2025Allow1210NoNo
18736589SEMICONDUCTOR STRUCTUREJune 2024April 2025Allow1110NoNo
18737616INTEGRATED CIRCUIT STRUCTURES INCLUDING A TITANIUM SILICIDE MATERIALJune 2024May 2025Allow1110NoNo
18679459NANOWIRE TRANSISTOR AND METHOD FOR FABRICATING THE SAMEMay 2024January 2025Allow810NoNo
18679004SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFMay 2024January 2025Allow800NoNo
18679375ELECTRONIC DEVICEMay 2024April 2025Allow1010NoNo
18678251EMBEDDED SEMICONDUCTOR PACKAGES AND METHODS THEREOFMay 2024March 2025Allow900YesNo
18676056Integrated Assemblies and Methods of Forming Integrated AssembliesMay 2024March 2025Allow1010NoNo
18674889SEMICONDUCTOR DEVICEMay 2024December 2024Allow700NoNo
18673960SEMICONDUCTOR DEVICE FABRICATION METHODS AND STRUCTURES THEREOFMay 2024April 2025Allow1110NoNo
18672218GAP-INSULATED SEMICONDUCTOR DEVICEMay 2024April 2025Allow1110NoNo
18670123SEMICONDUCTOR DEVICE HAVING FINS AND METHOD OF FABRICATING THE SAMEMay 2024April 2025Allow1110YesNo
18669052AIR GAP IN INNER SPACERS AND METHODS OF FABRICATING THE SAME IN FIELD-EFFECT TRANSISTORSMay 2024January 2025Allow800NoNo
18669199EFFECTIVE WORK FUNCTION TUNING VIA SILICIDE INDUCED INTERFACE DIPOLE MODULATION FOR METAL GATESMay 2024April 2025Allow1110NoNo
18666322SELECTIVE DUAL SILICIDE FORMATIONMay 2024December 2024Allow700NoNo
18665572TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTORMay 2024December 2024Allow700NoNo
18665600SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAMEMay 2024January 2025Allow800NoNo
18664222SEMICONDUCTOR STRUCTUREMay 2024March 2025Allow1010NoNo
18661741SEMICONDUCTOR DEVICE STRUCTUREMay 2024March 2025Allow1010NoNo
18662544SEMICONDUCTOR DEVICEMay 2024June 2025Allow1320YesNo
18655832FinFET Device and MethodMay 2024May 2025Allow1310YesNo
18655973Source/Drain Contacts and Methods of Forming SameMay 2024March 2025Allow1010NoNo
18652079Assemblies having Conductive Interconnects which are Laterally and Vertically Offset Relative to One AnotherMay 2024June 2025Allow1420NoNo
18650157METALLIZATION LAYER AND FABRICATION METHODApril 2024June 2025Allow1310NoNo
18648876METHODS FOR FORMING MULTI-GATE TRANSISTORSApril 2024March 2025Allow1110NoNo
18646773SEMICONDUCTOR DEVICE WITH MULTICHANNEL HETEROSTRUCTURE AND MANUFACTURING METHOD THEREOFApril 2024April 2025Allow1110NoNo
18638997SEMICONDUCTOR DEVICEApril 2024June 2025Allow1410NoNo
18638337NITRIDE SEMICONDUCTOR DEVICEApril 2024February 2025Allow1010NoNo
18636217SEMICONDUCTOR DEVICE, FINFET DEVICE AND METHODS OF FORMING THE SAMEApril 2024February 2025Allow1010NoNo
18635378SEMICONDUCTOR DEVICE STRUCTURE WITH STACKED CONDUCTIVE PLUGS AND METHOD FOR PREPARING THE SAMEApril 2024January 2025Allow910NoNo
18634620SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUSApril 2024April 2025Allow1200YesNo
18634782INTEGRATED CIRCUIT WITH BACKSIDE POWER RAIL AND BACKSIDE INTERCONNECTApril 2024May 2025Allow1310NoNo
18633002SEMICONDUCTOR DEVICESApril 2024March 2025Allow1110NoNo
18630549FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAMEApril 2024March 2025Allow1110NoNo
18628933ARRAY SUBSTRATE AND DISPLAY APPARATUSApril 2024January 2025Allow1010NoNo
18627362Semiconductor Structures and Manufacturing Methods ThereofApril 2024January 2025Allow921YesNo
18625282SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOFApril 2024April 2025Allow1210YesNo
18626145SEMICONDUCTOR APPARATUS AND EQUIPMENTApril 2024April 2025Allow1310NoNo
18624983SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICEApril 2024June 2025Allow1410NoNo
18623143MULTI-GATE DEVICES AND FABRICATING THE SAME WITH ETCH RATE MODULATIONApril 2024January 2025Allow1010NoNo
18623390ISOLATION STRUCTURES IN MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAMEApril 2024February 2025Allow1110NoNo
18614718ELECTRONIC DEVICEMarch 2024March 2025Allow1110NoNo
18613296SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAMEMarch 2024March 2025Allow1110NoNo
18609424DISPLAY SUBSTRATE AND DISPLAY APPARATUSMarch 2024January 2025Allow1010NoNo
18606944DECOUPLING CAPACITORS WITH BACK SIDE POWER RAILSMarch 2024February 2025Allow1110NoNo
18603424IMAGE-CAPTURE ELEMENT AND IMAGE CAPTURE DEVICEMarch 2024January 2025Allow1010NoNo
18602174MRAM CELL AND MRAMMarch 2024April 2025Allow1300NoNo
18600826METHOD OF FORMING AN INTEGRATED CIRCUIT STRUCTURE INCLUDING A RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLMarch 2024December 2024Allow900NoNo
18600403SEMICONDUCTOR DEVICEMarch 2024October 2024Allow810NoNo
18598934NANOSHEET FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMINGMarch 2024March 2025Allow1220NoNo
18598689SUPER-STEEP SWITCHING DEVICE AND INVERTER DEVICE USING THE SAMEMarch 2024November 2024Allow810YesNo
18598781SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOFMarch 2024September 2024Allow700NoNo
18597440SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAMEMarch 2024November 2024Allow910NoNo
18595542SEMICONDUCTOR DEVICESMarch 2024January 2025Allow1100NoNo
18594073LOW RESISTANCE FILL METAL LAYER MATERIAL AS STRESSOR IN METAL GATESMarch 2024April 2025Allow1320NoNo
18591089INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND FILLER CELLFebruary 2024November 2024Allow800NoNo
18590985MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEFebruary 2024November 2024Allow910NoNo
18590820SEMICONDUCTOR DEVICES WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOFFebruary 2024April 2025Allow1320NoNo
18585211Interconnect Layout for Semiconductor DeviceFebruary 2024June 2025Allow1610YesNo
18584862GATE ALL AROUND TRANSISTOR WITH DUAL INNER SPACERSFebruary 2024January 2025Allow1110NoNo
18581096SEMICONDUCTOR DEVICESFebruary 2024January 2025Allow1110NoNo
18444889WELL PICK-UP REGION DESIGN FOR IMPROVING MEMORY MACRO PERFORMANCEFebruary 2024December 2024Allow1000NoNo
18441767Stack of Horizontally Extending and Vertically Overlapping Features, Methods of Forming Circuitry Components, and Methods of Forming an Array of Memory CellsFebruary 2024January 2025Allow1100NoNo
18441507SEMICONDUCTOR DEVICEFebruary 2024September 2024Allow700NoNo
18439859METHOD FOR FORMING LONG CHANNEL BACK-SIDE POWER RAIL DEVICEFebruary 2024March 2025Allow1411NoNo
18440526GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING EMBEDDED GESNB SOURCE OR DRAIN STRUCTURESFebruary 2024December 2024Allow1010NoNo
18439095SELF-ALIGNED CONTACT AIR GAP FORMATIONFebruary 2024April 2025Allow1420NoNo
18437625METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICEFebruary 2024December 2024Allow1010NoNo
18437199SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICEFebruary 2024January 2025Allow1210NoNo
18435140Transistor Gate Structure and Method of FormingFebruary 2024May 2025Allow1520NoNo
18434028SEMICONDUCTOR DEVICE STRUCTURE WITH METAL GATE STACKFebruary 2024February 2025Allow1210NoNo
18432740PARASITIC CAPACITANCE REDUCTION IN GAN-ON-SILICON DEVICESFebruary 2024November 2024Allow900YesNo
18433217INTEGRATED CIRCUIT DEVICE WITH SOURCE/DRAIN BARRIERFebruary 2024January 2025Allow1210NoNo
18430771METAL OXIDE AND TRANSISTOR INCLUDING METAL OXIDEFebruary 2024December 2024Allow1010NoNo
18429734SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAMEFebruary 2024January 2025Allow1210NoNo
18426859PROCESS WINDOW CONTROL FOR GATE FORMATION IN SEMICONDUCTOR DEVICESJanuary 2024September 2024Allow810NoNo
18421398SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTUREJanuary 2024December 2024Allow1110NoNo
18420684SYSTEM ARCHITECTURE, STRUCTURE AND METHOD FOR HYBRID RANDOM ACCESS MEMORY IN A SYSTEM-ON-CHIPJanuary 2024April 2025Allow1430YesNo
18420209Methods of Forming Spacers for Semiconductor Devices Including Backside Power RailsJanuary 2024December 2024Allow1110NoNo
18420327SEMICONDUCTOR STRUCTUREJanuary 2024December 2024Allow1110NoNo
18420686PACKAGE STRUCTUREJanuary 2024December 2024Allow1110YesNo
18420138SEMICONDUCTOR DEVICESJanuary 2024May 2025Allow1610YesNo
18418678Gate Structures in Transistors and Method of Forming SameJanuary 2024December 2024Allow1110NoNo

Appeals Overview

This analysis examines appeal outcomes and the strategic value of filing appeals for art-unit 2811.

Patent Trial and Appeal Board (PTAB) Decisions

Total PTAB Decisions
206
Examiner Affirmed
133
(64.6%)
Examiner Reversed
73
(35.4%)
Reversal Percentile
64.3%
Higher than average

What This Means

With a 35.4% reversal rate, the PTAB reverses the examiner's rejections in a meaningful percentage of cases. This reversal rate is above the USPTO average, indicating that appeals have better success here than typical.

Strategic Value of Filing an Appeal

Total Appeal Filings
832
Allowed After Appeal Filing
256
(30.8%)
Not Allowed After Appeal Filing
576
(69.2%)
Filing Benefit Percentile
38.4%
Lower than average

Understanding Appeal Filing Strategy

Filing a Notice of Appeal can sometimes lead to allowance even before the appeal is fully briefed or decided by the PTAB. This occurs when the examiner or their supervisor reconsiders the rejection during the mandatory appeal conference (MPEP § 1207.01) after the appeal is filed.

In this dataset, 30.8% of applications that filed an appeal were subsequently allowed. This appeal filing benefit rate is below the USPTO average, suggesting that filing an appeal has limited effectiveness in prompting favorable reconsideration.

Strategic Recommendations

✓ Appeals to PTAB show good success rates. If you have a strong case on the merits, consider fully prosecuting the appeal to a Board decision.

⚠ Filing a Notice of Appeal shows limited benefit. Consider other strategies like interviews or amendments before appealing.

Art Unit 2811 - Prosecution Statistics Summary

Executive Summary

Art Unit 2811 is part of Group 2810 in Technology Center 2800. This art unit has examined 17,591 patent applications in our dataset, with an overall allowance rate of 77.5%. Applications typically reach final disposition in approximately 26 months.

Comparative Analysis

Art Unit 2811's allowance rate of 77.5% places it in the 49% percentile among all USPTO art units. This art unit has a below-average allowance rate compared to other art units.

Prosecution Patterns

Applications in Art Unit 2811 receive an average of 1.91 office actions before reaching final disposition (in the 58% percentile). The median prosecution time is 26 months (in the 70% percentile).

Strategic Considerations

When prosecuting applications in this art unit, consider the following:

  • The art unit's allowance rate suggests a more challenging examination environment compared to the USPTO average.
  • With more office actions than average, plan for relatively streamlined prosecution.
  • The median prosecution time is shorter than average and should be factored into your continuation and client communication strategies.
  • Review individual examiner statistics within this art unit to identify examiners with particularly favorable or challenging prosecution patterns.

Important Disclaimer

Not Legal Advice: The information provided in this report is for informational purposes only and does not constitute legal advice. You should consult with a qualified patent attorney or agent for advice specific to your situation.

No Guarantees: We do not provide any guarantees as to the accuracy, completeness, or timeliness of the statistics presented above. Patent prosecution statistics are derived from publicly available USPTO data and are subject to data quality limitations, processing errors, and changes in USPTO practices over time.

Limitation of Liability: Under no circumstances will IronCrow AI be liable for any outcome, decision, or action resulting from your reliance on the statistics, analysis, or recommendations presented in this report. Past prosecution patterns do not guarantee future results.

Use at Your Own Risk: While we strive to provide accurate and useful prosecution statistics, you should independently verify any information that is material to your prosecution strategy and use your professional judgment in all patent prosecution matters.